temac_controller.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/temac_controller.vhd,v $                                                  *
--*  $Revision: 2.4.2.4 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:46 $                                                    *


--*                                                            *
--**************************************************************

--------------------------------------------------------------------------------
--
--
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
--     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
--     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
--     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
--     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
--     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
--     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
--     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
--     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
--     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
--     FOR A PARTICULAR PURPOSE.
--     
--     (c) Copyright 2005 Xilinx, Inc.
--     All rights reserved.
-- 
------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;




entity temac_controller is
  port (
    TXVLD_N        : out   std_logic;
    gmii_col       : in    std_logic;
    gmii_crs       : in    std_logic;
    gmii_rx_clk    : in    std_logic;
    gmii_rx_dv     : in    std_logic;
    gmii_rx_er     : in    std_logic;
    gmii_rxd       : in    std_logic_vector (0 to 7);
    mii_tx_clk     : in    std_logic;
    gmii_tx_clk    : out   std_logic;
    gmii_tx_en     : out   std_logic;
    gmii_tx_er     : out   std_logic;
    gmii_txd       : out   std_logic_vector(0 to 7);
    MDC_0          : out   std_logic;
    mdio           : inout std_logic;
    phy_mii_int    : out   std_logic;
    sys_rst        : in    std_logic;
    sys_clk        : in    std_logic;
    dcm1_locked    : out   std_logic;
    tx_fifo_data   : in    std_logic_vector (0 to 31);
    tx_fifo_wren   : in    std_logic;
    tx_fifo_full   : out   std_logic;
    tx_fifo_lock_n : in    std_logic;
    EMPTY          : out   std_logic;
    rx_fifo_rst    : in    std_logic;
    rx_fifo_data   : out   std_logic_vector (0 to 31);
    rx_fifo_rden   : in    std_logic;
    clk_100mhz     : in    std_logic
    );
end temac_controller;


architecture temac_controller_arc of temac_controller is


  component xtemac is
    port(
      -- Client Receiver Interface - EMAC0
      EMAC0CLIENTRXCLIENTCLKOUT : out std_logic;
      CLIENTEMAC0RXCLIENTCLKIN  : in  std_logic;
      EMAC0CLIENTRXD            : out std_logic_vector(7 downto 0);
      EMAC0CLIENTRXDVLD         : out std_logic;
      EMAC0CLIENTRXDVLDMSW      : out std_logic;
      EMAC0CLIENTRXGOODFRAME    : out std_logic;
      EMAC0CLIENTRXBADFRAME     : out std_logic;
      EMAC0CLIENTRXFRAMEDROP    : out std_logic;
      EMAC0CLIENTRXDVREG6       : out std_logic;
      EMAC0CLIENTRXSTATS        : out std_logic_vector(6 downto 0);
      EMAC0CLIENTRXSTATSVLD     : out std_logic;
      EMAC0CLIENTRXSTATSBYTEVLD : out std_logic;

      -- Client Transmitter Interface - EMAC0
      EMAC0CLIENTTXCLIENTCLKOUT  : out std_logic;
      CLIENTEMAC0TXCLIENTCLKIN   : in  std_logic;
      CLIENTEMAC0TXD             : in  std_logic_vector(7 downto 0);
      CLIENTEMAC0TXDVLD          : in  std_logic;
      CLIENTEMAC0TXDVLDMSW       : in  std_logic;
      EMAC0CLIENTTXACK           : out std_logic;
      CLIENTEMAC0TXFIRSTBYTE     : in  std_logic;
      CLIENTEMAC0TXUNDERRUN      : in  std_logic;
      EMAC0CLIENTTXCOLLISION     : out std_logic;
      EMAC0CLIENTTXRETRANSMIT    : out std_logic;
      CLIENTEMAC0TXIFGDELAY      : in  std_logic_vector(7 downto 0);
      EMAC0CLIENTTXSTATS         : out std_logic;
      EMAC0CLIENTTXSTATSVLD      : out std_logic;
      EMAC0CLIENTTXSTATSBYTEVLD  : out std_logic;
      -- MAC Control Interface - EMAC0
      CLIENTEMAC0PAUSEREQ        : in  std_logic;
      CLIENTEMAC0PAUSEVAL        : in  std_logic_vector(15 downto 0);
      -- Clock Signal - EMAC0
      GTX_CLK_0                  : in  std_logic;
      EMAC0CLIENTTXGMIIMIICLKOUT : out std_logic;
      CLIENTEMAC0TXGMIIMIICLKIN  : in  std_logic;
      -- GMII Interface - EMAC0
      GMII_TXD_0                 : out std_logic_vector(7 downto 0);
      GMII_TX_EN_0               : out std_logic;
      GMII_TX_ER_0               : out std_logic;
      GMII_TX_CLK_0              : out std_logic;
      GMII_RXD_0                 : in  std_logic_vector(7 downto 0);
      GMII_RX_DV_0               : in  std_logic;
      GMII_RX_ER_0               : in  std_logic;
      GMII_RX_CLK_0              : in  std_logic;
      MII_TX_CLK_0               : in  std_logic;
      GMII_COL_0                 : in  std_logic;
      GMII_CRS_0                 : in  std_logic;
      -- MDIO Interface - EMAC0
      MDC_0                      : out std_logic;
      MDIO_IN_0                  : in  std_logic;
      MDIO_OUT_0                 : out std_logic;
      MDIO_TRI_0                 : out std_logic;
      HOSTCLK                    : in  std_logic;
      -- Asynchronous Reset
      RESET                      : in  std_logic
      );
  end component;


  component bcm_emac_fifo
    port (
      din    : in  std_logic_vector(8 downto 0);
      rd_clk : in  std_logic;
      rd_en  : in  std_logic;
      rst    : in  std_logic;
      wr_clk : in  std_logic;
      wr_en  : in  std_logic;
      dout   : out std_logic_vector(8 downto 0);
      empty  : out std_logic;
      full   : out std_logic);
  end component;


  component bcm_emac_fifo_rx
    port(
      din    : in  std_logic_vector(8 downto 0);
      rd_clk : in  std_logic;
      rd_en  : in  std_logic;
      rst    : in  std_logic;
      wr_clk : in  std_logic;
      wr_en  : in  std_logic;
      dout   : out std_logic_vector(8 downto 0);
      empty  : out std_logic;
      full   : out std_logic
      );
  end component;


  component extend_test
    generic (
      LEN : integer range 0 to 63 := 2
      );
    port(
      CLK  : in  std_logic;
      RES  : in  std_logic;
      A    : in  std_logic;
      ENDM : out std_logic;
      Y    : out std_logic
      );
  end component;


  component edge
    port(
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic
      );
  end component;


  component period_check
    generic (
      PERIOD : integer range 0 to 255);
    port (
      CLK : in  std_logic;
      RES : in  std_logic;
      EN  : in  std_logic;
      A   : in  std_logic;
      Y   : out std_logic
      );
  end component;

-- DCM Signals
  signal gtx_clk_bufg_in                                 : std_logic;
  signal dcm1_clk0_i                                     : std_logic;
  signal dcm1_clk0_o                                     : std_logic;
-- EMAC signal
  signal gnd_i, dcm1_lock, lock_i                        : std_logic;
  signal reset_i, fifo_rst                               : std_logic;
  signal gtx_clk_bufg_0_i                                : std_logic;
  signal rx_client_clk_out_0_i                           : std_logic;
  signal rx_client_clk_in_0_i                            : std_logic;
  signal tx_client_clk_out_0_i                           : std_logic;
  signal tx_client_clk_in_0_i                            : std_logic;
  signal tx_gmii_mii_clk_out_0_i                         : std_logic;
  signal tx_gmii_mii_clk_in_0_i                          : std_logic;
  signal gmii_tx_clk_0_i                                 : std_logic;
  signal gmii_tx_en_0_i                                  : std_logic;
  signal gmii_tx_er_0_i                                  : std_logic;
  signal gmii_txd_0_i                                    : std_logic_vector(7 downto 0);
  signal gmii_tx_en_0_r                                  : std_logic;
  signal gmii_tx_er_0_r                                  : std_logic;
  signal gmii_txd_0_r                                    : std_logic_vector(7 downto 0);
  signal mii_tx_clk_0_i                                  : std_logic;
  signal gmii_col_0_i                                    : std_logic;
  signal gmii_crs_0_i                                    : std_logic;
  signal gmii_rx_clk_ibufg_0_i                           : std_logic;
  signal gmii_rx_clk_0_i                                 : std_logic;
  signal gmii_rx_dv_0_i                                  : std_logic;
  signal gmii_rx_dv_delay_0_i                            : std_logic;
  signal gmii_rx_er_0_i                                  : std_logic;
  signal gmii_rx_er_delay_0_i                            : std_logic;
  signal gmii_rxd_0_i                                    : std_logic_vector(7 downto 0);
  signal gmii_rxd_delay_0_i                              : std_logic_vector(7 downto 0);
  signal gmii_rx_dv_0_r                                  : std_logic;
  signal gmii_rx_er_0_r                                  : std_logic;
  signal gmii_rxd_0_r                                    : std_logic_vector(7 downto 0);
  -- MDIO signals
  signal MDIO_IN_0                                       : std_logic;
  signal MDIO_OUT_0                                      : std_logic;
  signal MDIO_TRI_0                                      : std_logic;
  signal mdc_0_obuf                                      : std_logic;
  signal emac_mdc                                        : std_logic;
  signal emac_mdio_in                                    : std_logic;
  signal emac_mdio_out                                   : std_logic;
  signal emac_mdio_tri                                   : std_logic;
-- EMAC Receive interface to rx_fifo
  signal rx_valid                                        : std_logic;
  signal rx_good_frame                                   : std_logic;
  signal rx_bad_frame                                    : std_logic;
  signal rx_data                                         : std_logic_vector (0 to 7);
  signal rx_clk                                          : std_logic;
  signal rx_fifo_DO                                      : std_logic_vector (7 downto 0);
  signal rx_fifo_wren                                    : std_logic;
  signal rx_fifo_full                                    : std_logic;
  signal rx_valid_fifo                                   : std_logic;
  signal rx_fifo_rderr                                   : std_logic;
-- EMAC Transmit interface to rx_fifo
  signal tx_data                                         : std_logic_vector (7 downto 0);
  signal tx_valid, tx_valid_i                            : std_logic := '0';
  signal n_tx_valid, macen                               : std_logic := '0';
  signal tx_ack                                          : std_logic := '0';
  signal tx_ack_delay                                    : std_logic := '0';
  signal tx_fifo_empty                                   : std_logic := '0';
  signal tx_fifo_rden                                    : std_logic := '0';
  signal tx_fifo_di                                      : std_logic_vector (8 downto 0);
  signal edge_txclk, mac_clk_pres                        : std_logic;
  signal tx_fifo_rden_start                              : std_logic := '0';
  signal n_tx_fifo_di8, n_tx_fifo_di8_l, n_tx_fifo_di8_p : std_logic;

  alias tx_clk is tx_client_clk_in_0_i;

begin

  EMPTY <= tx_fifo_empty;

-- tx fifo supporting logic
  tx_fifo_di   <= tx_fifo_data(23 to 31);
  tx_fifo_rden <= (tx_fifo_rden_start or tx_ack_delay or tx_ack);
  --EMPTY <= not tx_valid;


  extender : extend_test
    generic map (LEN => 20)
    port map(
      CLK  => clk_100mhz,
      RES  => sys_rst ,
      ENDM => open,
      A    => n_tx_fifo_di8,
      Y    => n_tx_fifo_di8_l
      );


  pulser : edge port map(
    CLK   => tx_clk ,
    A     => n_tx_fifo_di8_l,
    PULSE => n_tx_fifo_di8_p
    );


  rden_start : process (tx_clk, sys_rst)
  begin
    if sys_rst = '1' then
      tx_fifo_rden_start <= '0';
    elsif tx_clk'event and tx_clk = '1' then
      tx_fifo_rden_start <= n_tx_fifo_di8_p;
    end if;
  end process rden_start;


  ack_delay : process (tx_clk, sys_rst)
  begin
    if sys_rst = '1' then
      tx_ack_delay <= '0';
    elsif tx_clk'event and tx_clk = '1' then
      if tx_valid = '0' then
        tx_ack_delay <= '0';
      elsif tx_ack = '1' then
        tx_ack_delay <= '1';
      end if;
    end if;
  end process ack_delay;


  mac_en : process(tx_clk, sys_rst)
  begin
    if sys_rst = '1' then
      macen <= '0';
    elsif tx_clk'event and tx_clk = '1' then
      if tx_fifo_rden_start = '1' then
        macen <= '1';
      elsif tx_valid = '0' then
        macen <= '0';
      else
        macen <= macen;
      end if;
    end if;
  end process mac_en;

-- rx FIFO supporting logic
  rx_fifo_wren           <= (rx_valid or rx_good_frame or rx_bad_frame) and (not rx_fifo_rst);
-- connection to  ppc from rx fifo
  rx_fifo_data(24 to 31) <= rx_fifo_DO;     -- 7 downto 0
  rx_fifo_data(8)        <= rx_fifo_rderr;  -- 23
  rx_fifo_data(11)       <= rx_valid_fifo;  -- 20
  rx_fifo_data(13)       <= rx_fifo_full;   -- 18
  rx_fifo_data(0 to 7)   <= "00000000";     -- 31 downto 24
  rx_fifo_data(9)        <= rx_good_frame;  -- 22
  rx_fifo_data(10)       <= rx_bad_frame;   -- 21
  rx_fifo_data(12)       <= rx_valid;       -- 19
  rx_fifo_data(14 to 23) <= "0000000000";   -- 17 downto 8

-----------------------------------------------------------------------------------
--ETHERNET SIGNALS, BUFFERS, FLIPFLOPS, AND EMAC
-----------------------------------------------------------------------------------

--    phy_mii_int<= not phy_mii_int_n_IBUF;
--     ibuf_29 : IBUF port map(
--     I=> phy_mii_int_n,
--     O=> phy_mii_int_n_IBUF
--     );

  phy_mii_int <= '0';

  obuf55 : OBUF
    port map(
      I => mdc_0_obuf,
      O => mdc_0 
      );
  gnd_i <= '0';

  reset_i <= sys_rst;
  iobuf_56 : IOBUF
    port map(
      I  => MDIO_OUT_0,
      IO => mdio,
      O  => MDIO_IN_0,
      T   => MDIO_TRI_0
      );


  mdio_reg1 : process (sys_clk)
  begin
    if sys_clk'event and sys_clk = '1' then
      mdc_0_obuf <= emac_mdc;
      MDIO_OUT_0 <= emac_mdio_out;
      MDIO_TRI_0 <= emac_mdio_tri;
    end if;


  end process mdio_reg1;
  mdio_reg2 : process (mdc_0_obuf)
  begin
    if mdc_0_obuf'event and mdc_0_obuf = '0' then
      emac_mdio_in <= MDIO_IN_0;
    end if;
  end process mdio_reg2;

  --********** EMAC0 **********
  ----------------------------------------------------------------------------

  gtx : BUFG
    port map (
      I => gtx_clk_bufg_in,
      O => gtx_clk_bufg_0_i
      );

  tx_gmii_mii_clk_0_bufg : BUFG
    port map (
      I => tx_gmii_mii_clk_out_0_i,
      O => tx_gmii_mii_clk_in_0_i
      );

  ----------------------------------------------------------------------------

  gmii_tx_clk_0_obuf : OBUF
    port map (
      I => gmii_tx_clk_0_i,
      O => gmii_tx_clk
      );

  ----------------------------------------------------------------------------



  gmii_output_ffs_0 : process (tx_gmii_mii_clk_in_0_i, reset_i)
  begin
    if reset_i = '1' then
      gmii_tx_en_0_r <= '0';
      gmii_tx_er_0_r <= '0';
      gmii_txd_0_r   <= (others => '0');
    elsif tx_gmii_mii_clk_in_0_i'event and tx_gmii_mii_clk_in_0_i = '1' then
      gmii_tx_en_0_r <= gmii_tx_en_0_i;
      gmii_tx_er_0_r <= gmii_tx_er_0_i;
      gmii_txd_0_r   <= gmii_txd_0_i;
    end if;
  end process gmii_output_ffs_0;


  gmii_tx_en_0_obuf : OBUF port map (I => gmii_tx_en_0_r, O => gmii_tx_en);

  gmii_tx_er_0_obuf : OBUF port map (I => gmii_tx_er_0_r, O => gmii_tx_er);

  gmii_txd_0_bus    : for I in 7 downto 0 generate
    gmii_txd_0_obuf : OBUF
      port map (
        I => gmii_txd_0_r(I),
        O => gmii_txd(I)
        );
  end generate;

  ----------------------------------------------------------------------------

  gmii_rx_clk_0_ibufg : IBUFG
    port map (
      I => gmii_rx_clk,
      O => gmii_rx_clk_ibufg_0_i
      );

  gmii_rx_clk_0_i <= gmii_rx_clk_ibufg_0_i;

  ----------------------------------------------------------------------------





  gmii_rx_dv_0_ibuf : IBUF port map (I => gmii_rx_dv, O => gmii_rx_dv_0_i);


  gmii_rx_dv_0_delay : IDELAY
    port map (
      I   => gmii_rx_dv_0_i,
      O   => gmii_rx_dv_delay_0_i,
      C   => gnd_i ,
      CE  => gnd_i,
      INC => gnd_i,
      RST => gnd_i
      );

  gmii_rx_er_0_ibuf : IBUF port map (I => gmii_rx_er, O => gmii_rx_er_0_i);


  gmii_rx_er_0_delay : IDELAY
    port map (
      I   => gmii_rx_er_0_i,
      O   => gmii_rx_er_delay_0_i,
      C   => gnd_i ,
      CE  => gnd_i,
      INC => gnd_i,
      RST => gnd_i
      );

  gmii_rxd_0_bus : for I in 7 downto 0 generate
    gmii_rxd_0_ibuf : IBUF
      port map (
        I => gmii_rxd(I),
        O => gmii_rxd_0_i(I)
        );

    gmii_rxd_0_delay : IDELAY
      port map (
        I   => gmii_rxd_0_i(I),
        O   => gmii_rxd_delay_0_i(I),
        C   => gnd_i ,
        CE  => gnd_i ,
        INC => gnd_i ,
        RST => gnd_i 
        );
  end generate;


  gmii_input_ffs_0 : process (gmii_rx_clk_0_i, reset_i)
  begin
    if reset_i = '1' then
      gmii_rx_dv_0_r <= '0';
      gmii_rx_er_0_r <= '0';
      gmii_rxd_0_r   <= (others => '0');
    elsif gmii_rx_clk_0_i'event and gmii_rx_clk_0_i = '1' then
      gmii_rx_dv_0_r <= gmii_rx_dv_delay_0_i;
      gmii_rx_er_0_r <= gmii_rx_er_delay_0_i;
      gmii_rxd_0_r   <= gmii_rxd_delay_0_i;
    end if;
  end process gmii_input_ffs_0;


  mii_tx_clk_0_ibufg : IBUFG
    port map (
      I => mii_tx_clk,
      O => mii_tx_clk_0_i
      );


  -- auto generate IBUFs
  gmii_col_0_i <= gmii_col;
  gmii_crs_0_i <= gmii_crs;

  -- Half Duplex signals for tri-speed mode
  --gmii_col_0_obuf : IBUF port map (I => gmii_col, O => gmii_col_0_i);
  --gmii_crs_0_obuf : IBUF port map (I => gmii_crs, O => gmii_crs_0_i);

  ----------------------------------------------------------------------------
  -- Receive & Transmit Client Clock Management when configured in 8-bit mode
  ----------------------------------------------------------------------------

  BUFR_inst : BUFR
    generic map (
      BUFR_DIVIDE => "BYPASS",  -- "BYPASS", "1", "2", "3", "4", "5", "6", "7", "8
      SIM_DEVICE  => "VIRTEX4")  -- Specify target device, "VIRTEX4" or "VIRTEX5
    port map (
      O   => tx_client_clk_in_0_i,      -- Clock buffer output
      CE  => '1' ,                       -- Clock enable input
      CLR => '0' ,                       -- Clock buffer reset input
      I   => tx_client_clk_out_0_i      -- Clock buffer input
      );
  rx_client_clk_in_0_i <= rx_client_clk_out_0_i;
  rx_clk               <= rx_client_clk_in_0_i;

  ----------------------------------------------------------------------------

  v4_emac_top : xtemac
    port map (
      -- Client Receiver Interface - EMAC0
      EMAC0CLIENTRXCLIENTCLKOUT  => rx_client_clk_out_0_i,
      CLIENTEMAC0RXCLIENTCLKIN   => rx_client_clk_in_0_i,
      EMAC0CLIENTRXD             => rx_data,
      EMAC0CLIENTRXDVLD          => rx_valid,
      EMAC0CLIENTRXDVLDMSW       => open,
      EMAC0CLIENTRXGOODFRAME     => rx_good_frame,
      EMAC0CLIENTRXBADFRAME      => rx_bad_frame,
      EMAC0CLIENTRXFRAMEDROP     => open,
      EMAC0CLIENTRXDVREG6        => open,
      EMAC0CLIENTRXSTATS         => open,
      EMAC0CLIENTRXSTATSVLD      => open,
      EMAC0CLIENTRXSTATSBYTEVLD  => open,
      -- Client Transmitter Interface - EMAC0
      EMAC0CLIENTTXCLIENTCLKOUT  => tx_client_clk_out_0_i,
      CLIENTEMAC0TXCLIENTCLKIN   => tx_client_clk_in_0_i,
      CLIENTEMAC0TXD             => tx_data,
      CLIENTEMAC0TXDVLD          => macen,
      CLIENTEMAC0TXDVLDMSW       => '0',
      EMAC0CLIENTTXACK           => tx_ack,
      CLIENTEMAC0TXFIRSTBYTE     => '0',
      CLIENTEMAC0TXUNDERRUN      => '0',
      EMAC0CLIENTTXCOLLISION     => open,
      EMAC0CLIENTTXRETRANSMIT    => open,
      CLIENTEMAC0TXIFGDELAY      => "00000000",
      EMAC0CLIENTTXSTATS         => open,
      EMAC0CLIENTTXSTATSVLD      => open,
      EMAC0CLIENTTXSTATSBYTEVLD  => open,
      -- MAC Control Interface - EMAC0
      CLIENTEMAC0PAUSEREQ        => '0',
      CLIENTEMAC0PAUSEVAL        => "0000000000000000",
      -- Clock Signal - EMAC0
      GTX_CLK_0                  => gtx_clk_bufg_0_i,
      EMAC0CLIENTTXGMIIMIICLKOUT => tx_gmii_mii_clk_out_0_i,
      CLIENTEMAC0TXGMIIMIICLKIN  => tx_gmii_mii_clk_in_0_i,
      -- GMII Interface - EMAC0
      GMII_TXD_0                  => gmii_txd_0_i,
      GMII_TX_EN_0               => gmii_tx_en_0_i,
      GMII_TX_ER_0               => gmii_tx_er_0_i,
      GMII_TX_CLK_0              => gmii_tx_clk_0_i,
      GMII_RXD_0                 => gmii_rxd_0_r,
      GMII_RX_DV_0               => gmii_rx_dv_0_r,
      GMII_RX_ER_0               => gmii_rx_er_0_r,
      GMII_RX_CLK_0              => gmii_rx_clk_0_i,
      MII_TX_CLK_0               => mii_tx_clk_0_i,
      GMII_COL_0                 => gmii_col_0_i,
      GMII_CRS_0                 => gmii_crs_0_i,
      -- MDIO Interface - EMAC0
      MDC_0                       => emac_mdc,
      MDIO_IN_0                  => emac_mdio_in,
      MDIO_OUT_0                 => emac_mdio_out,
      MDIO_TRI_0                 => emac_mdio_tri,
      HOSTCLK                     => sys_clk,
      -- Asynchronous Reset
      RESET                      => reset_i
      );


  clk_checker : edge port map(
    CLK   => clk_100mhz,
    A     => tx_clk ,
    PULSE => edge_txclk
    );


  clk_checker_cnt : process(clk_100mhz)
    variable cnt : integer range 0 to 10 := 0;
  begin
    if clk_100mhz'event and clk_100mhz = '1' then
      if sys_rst = '1' then
        cnt          := 0;
        mac_clk_pres <= '0';
      else
        if edge_txclk = '1' then
          if mac_clk_pres = '0' then
            cnt := cnt + 1;
            if cnt = 4 then
              mac_clk_pres <= '1';
            end if;
          else
            cnt := cnt;
          end if;
        end if;
      end if;
    end if;
  end process clk_checker_cnt;


  MAC_DCM : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 2.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 4,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 5,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 10.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS" ,  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0" 
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => dcm1_clk0_o ,          -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => open,                 -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => gtx_clk_bufg_in,      -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      LOCKED   => dcm1_lock,            -- DCM LOCK status output
      CLKFB    => dcm1_clk0_i ,          -- DCM clock feedback
      CLKIN    => clk_100mhz ,      -- Clock input (from IBUFG, BUFG or DCM)
      RST      => sys_rst                -- DCM asynchronous reset input
      );

  lock_i <= dcm1_lock and mac_clk_pres;

  dcmfb : bufg port map (O => dcm1_clk0_i, I => dcm1_clk0_o);


  mac_clk_chk : period_check
    generic map (
      PERIOD  => 8 )
    port map (
      CLK => clk_100mhz,
      RES => sys_rst ,
      EN  => lock_i ,
      A   => tx_clk ,
      Y   => dcm1_locked
      );


  rx_fifo : bcm_emac_fifo_rx
    port map (
      din(7 downto 0)  => rx_data,
      din(8)            => rx_valid ,
      rd_clk           => sys_clk,
      rd_en             => rx_fifo_rden,
      rst               => sys_rst,
      wr_clk            => rx_clk,
      wr_en            => rx_fifo_wren,
      dout(7 downto 0) => rx_fifo_DO,
      dout(8)          => rx_valid_fifo,
      empty            => open,
      full             => rx_fifo_full
      );

  rx_fifo_rderr <= '0';


  tx_fifo : bcm_emac_fifo
    port map (
      din(7 downto 4)  => tx_fifo_di(3 downto 0),
      din(3 downto 0)  => tx_fifo_di(7 downto 4),
      din(8)           => tx_fifo_di(8),
      rd_clk            => tx_clk,
      rd_en             => tx_fifo_rden,
      rst               => fifo_rst,
      wr_clk           => sys_clk,
      wr_en            => tx_fifo_wren,
      dout(7 downto 4) => tx_data(3 downto 0),
      dout(3 downto 0) => tx_data(7 downto 4),
      dout(8)          => tx_valid_i,
      empty            => tx_fifo_empty,
      full             => tx_fifo_full
      );

  fifo_rst      <= sys_rst or (not dcm1_lock);
  tx_valid      <= tx_valid_i when tx_fifo_rden = '1' else '1';
  n_tx_valid    <= not tx_valid;
  n_tx_fifo_di8 <= not tx_fifo_di(8);
  TXVLD_N       <= n_tx_valid;

end architecture temac_controller_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:06 2008 for BCM-AAA by  1.5.7.1-20081012