BCM-AAA: mem_interface_top_top

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_top_0.vhd,v $                                                  *
00015 --*  $Revision: 1.3.2.3 $                                                *
00016 --*  $Name: dev $                                                    *
00017 --*  $Author: mniegl $                                                  *
00018 --*  $Date: 2008/11/03 17:57:44 $                                                    *
00019 --*                                                            *
00020 --**************************************************************
00021 -------------------------------------------------------------------------------
00022 -- Copyright (c) 2005 Xilinx, Inc.
00023 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00024 -------------------------------------------------------------------------------
00025 --   ____  ____
00026 --  /   /\/   /
00027 -- /___/  \  / Vendor: Xilinx
00028 -- \   \   \/ Version: 1.6
00029 --  \   \ Application : MIG
00030 --  /   / Filename: mem_interface_top_top_0.vhd
00031 -- /___/   /\ Date Last Modified:  Wed Jun 1 2005
00032 -- \   \  /  \Date Created: Mon May 2 2005
00033 --  \___\/\___\
00034 -- Device: Virtex-4
00035 -- Design Name: DDR1_SDRAM
00036 -- Description: Instantiates the main design logic of memory interface and interfaces
00037 --              with the user.
00038 -------------------------------------------------------------------------------
00039 
00040 
00041 library ieee;
00042 
00043 use ieee.std_logic_1164.all;
00044 
00045 library unisim;
00046 
00047 use unisim.vcomponents.all;
00048 use work.mem_interface_top_parameters_0.all;
00049 
00050 entity mem_interface_top_top_0 is
00051         port( clk_0             : in std_logic;
00052               clk_90            : in std_logic;
00053               clk_50            : in std_logic;
00054               ref_clk           : in std_logic;
00055               idelay_ctrl_rdy   : in std_logic;
00056               sys_rst_ref_clk_1 : in std_logic;
00057               sys_rst           : in std_logic;
00058               sys_rst90         : in std_logic;
00059               DDR_RAS_N              : out std_logic;  
00060               DDR_CAS_N              : out std_logic;  
00061               DDR_WE_N               : out std_logic;  
00062               DDR_CKE                : out std_logic; 
00063               DDR_CS_N               : out std_logic; 
00064               DDR_DQ                 : inout std_logic_vector((data_width-1) downto 0);        
00065               DDR_DQS                : inout std_logic_vector((data_strobe_width-1) downto 0); 
00066               
00067               DDR_DM                 : out std_logic_vector((data_mask_width-1) downto 0); 
00068               APP_MASK_DATA          : in std_logic_vector((data_mask_width*2 -1) downto 0); 
00069  
00070               
00071               DDR_CK                 : out std_logic_vector((clk_width-1) downto 0);  
00072               DDR_CK_N               : out std_logic_vector((clk_width-1) downto 0);  
00073               DDR_BA                 : out std_logic_vector((bank_address-1) downto 0);  
00074               DDR_A                  : out std_logic_vector((row_address-1) downto 0);   
00075               WDF_ALMOST_FULL        : out std_logic;  
00076               AF_ALMOST_FULL         : out std_logic;  
00077               BURST_LENGTH           : out std_logic_vector(2 downto 0); 
00078               READ_DATA_VALID        : out std_logic;   
00079               READ_DATA_FIFO_OUT     : out std_logic_vector((data_width*2 -1) downto 0);  
00080               APP_AF_ADDR            : in std_logic_vector(35 downto 0); 
00081               APP_AF_WREN            : in std_logic; 
00082               APP_WDF_DATA           : in std_logic_vector((data_width*2 -1) downto 0); 
00083               APP_WDF_WREN           : in std_logic;  
00084               CLK_TB                 : out std_logic;   
00085               RESET_TB               : out std_logic
00086             );
00087 end mem_interface_top_top_0;
00088 
00089 architecture arch of mem_interface_top_top_0 is
00090 
00091 component mem_interface_top_data_path_0
00092         port( 
00093                 CLK                     : in std_logic;                
00094                 CLK90                   : in std_logic;
00095                 CAL_CLK                 : in std_logic;
00096                 RESET0                  : in std_logic;
00097                 RESET90                 : in std_logic;
00098                 RESET_CAL_CLK           : in std_logic;
00099                 idelay_ctrl_rdy         : in std_logic;
00100                 dummy_write_pattern     : in std_logic;
00101                 CTRL_DUMMYREAD_START    : in std_logic;
00102                 WDF_DATA                : in std_logic_vector((data_width*2 -1) downto 0);
00103                 MASK_DATA               : in std_logic_vector((data_mask_width*2 -1) downto 0);
00104                 CTRL_WREN               : in std_logic;
00105                 CTRL_DQS_RST            : in std_logic;
00106                 CTRL_DQS_EN             : in std_logic;           
00107                 dqs_delayed             : in std_logic_vector((data_strobe_width -1) downto 0);            
00108                 data_idelay_inc         : out std_logic_vector((ReadEnable - 1) downto 0);
00109                 data_idelay_ce          : out std_logic_vector((ReadEnable - 1) downto 0);
00110                 data_idelay_rst         : out std_logic_vector((ReadEnable - 1) downto 0);
00111                 dqs_idelay_inc          : out std_logic_vector((ReadEnable - 1) downto 0);
00112                 dqs_idelay_ce           : out std_logic_vector((ReadEnable - 1) downto 0);
00113                 dqs_idelay_rst          : out std_logic_vector((ReadEnable - 1) downto 0);
00114                 SEL_DONE                : out std_logic;
00115                 dqs_rst                 : out std_logic;
00116                 dqs_en                  : out std_logic;
00117                 wr_en                   : out std_logic;
00118                 wr_data_rise            : out std_logic_vector((data_width -1) downto 0);
00119                 wr_data_fall            : out std_logic_vector((data_width -1) downto 0);
00120                 mask_data_rise          : out std_logic_vector((data_mask_width -1) downto 0);
00121                 mask_data_fall          : out std_logic_vector((data_mask_width -1) downto 0)
00122         );
00123 end component;
00124 
00125 component mem_interface_top_iobs_0
00126         port( CAL_CLK                   : in std_logic;
00127               DDR_CK                    : out std_logic_vector((clk_width-1) downto 0);
00128               DDR_CK_N                  : out std_logic_vector((clk_width-1) downto 0);
00129               CLK                       : in std_logic;
00130               CLK90                     : in std_logic;
00131               RESET0                    : in std_logic;
00132               RESET90                   : in std_logic;
00133               dqs_idelay_inc            : in std_logic_vector((ReadEnable-1) downto 0);
00134               dqs_idelay_ce             : in std_logic_vector((ReadEnable-1) downto 0);
00135               dqs_idelay_rst            : in std_logic_vector((ReadEnable-1) downto 0);
00136               data_idelay_inc           : in std_logic_vector((ReadEnable-1) downto 0);
00137               data_idelay_ce            : in std_logic_vector((ReadEnable-1) downto 0);
00138               data_idelay_rst           : in std_logic_vector((ReadEnable-1) downto 0);
00139               dqs_rst                   : in std_logic;
00140               dqs_en                    : in std_logic;
00141               wr_en                     : in std_logic;
00142               wr_data_rise              : in std_logic_vector((data_width-1) downto 0);
00143               wr_data_fall              : in std_logic_vector((data_width-1) downto 0);
00144               mask_data_rise            : in std_logic_vector((data_mask_width-1) downto 0);
00145               mask_data_fall            : in std_logic_vector((data_mask_width-1) downto 0);
00146               rd_data_rise              : out std_logic_vector((data_width-1) downto 0);
00147               rd_data_fall              : out std_logic_vector((data_width-1) downto 0);
00148               dqs_delayed               : out std_logic_vector((data_strobe_width-1) downto 0);
00149               DDR_DQ                    : inout std_logic_vector((data_width-1) downto 0);
00150               DDR_DQS                   : inout std_logic_vector((data_strobe_width-1) downto 0);
00151               DDR_DM                    : out std_logic_vector((data_mask_width-1) downto 0);
00152               ctrl_ddr_address          : in std_logic_vector((row_address-1) downto 0);
00153               ctrl_ddr_ba               : in std_logic_vector((bank_address-1) downto 0);
00154               ctrl_ddr_ras_L            : in std_logic;
00155               ctrl_ddr_cas_L            : in std_logic;
00156               ctrl_ddr_we_L             : in std_logic;
00157               ctrl_ddr_cs_L             : in std_logic;
00158               ctrl_ddr_cke              : in std_logic;
00159               DDR_ADDRESS               : out std_logic_vector((row_address-1) downto 0);
00160               DDR_BA                    : out std_logic_vector((bank_address-1) downto 0);
00161               DDR_RAS_L                 : out std_logic;
00162               DDR_CAS_L                 : out std_logic;
00163               DDR_WE_L                  : out std_logic;
00164               DDR_CKE                   : out std_logic;
00165               ddr_cs_L                  : out std_logic
00166             );
00167 end component;
00168 
00169 component mem_interface_top_user_interface_0
00170         port( CLK                       : in std_logic;
00171               clk90                     : in std_logic;
00172               RESET                     : in std_logic;
00173               ctrl_rden                 : in std_logic;
00174               READ_DATA_RISE            : in std_logic_vector((data_width -1) downto 0); 
00175               READ_DATA_Fall            : in std_logic_vector((data_width -1) downto 0); 
00176               READ_DATA_FIFO_OUT        : out std_logic_vector((data_width*2 -1) downto 0);
00177               comp_done                 : out std_logic;
00178               READ_DATA_VALID           : out std_logic;
00179               AF_EMPTY                  : out std_logic;
00180               AF_ALMOST_FULL            : out std_logic;
00181               APP_AF_ADDR               : in std_logic_vector(35 downto 0);
00182               APP_AF_WREN               : in std_logic;
00183               CTRL_AF_RDEN              : in std_logic;
00184               AF_ADDR                   : out std_logic_vector(35 downto 0);
00185               APP_WDF_DATA              : in std_logic_vector((data_width*2 -1) downto 0);
00186               APP_MASK_DATA             : in std_logic_vector((data_mask_width*2 -1) downto 0);
00187               APP_WDF_WREN              : in std_logic; 
00188               CTRL_WDF_RDEN             : in std_logic; 
00189               WDF_DATA                  : out std_logic_vector((data_width*2 -1) downto 0);      
00190               MASK_DATA                 : out std_logic_vector((data_mask_width*2 -1) downto 0); 
00191               WDF_ALMOST_FULL           : out std_logic
00192              );
00193 end component;
00194 
00195 component  mem_interface_top_ddr_controller_0 
00196         port( 
00197                 clk_0                   : in std_logic; 
00198                 refresh_clk             : in std_logic; 
00199                 rst                     : in std_logic; 
00200                 af_addr                 : in std_logic_vector(35 downto 0);
00201                 af_empty                : in std_logic; 
00202                 comp_done               : in std_logic;
00203                 phy_Dly_Slct_Done       : in std_logic; 
00204                 ctrl_Dummyread_Start    : out std_logic;
00205                 ctrl_af_RdEn            : out std_logic;
00206                 ctrl_Wdf_RdEn           : out std_logic;
00207                 ctrl_Dqs_Rst            : out std_logic;
00208                 ctrl_Dqs_En             : out std_logic;
00209                 ctrl_WrEn               : out std_logic;
00210                 ctrl_RdEn               : out std_logic;
00211                 ctrl_ddr_address        : out std_logic_vector((row_address - 1) downto 0);
00212                 ctrl_ddr_ba             : out std_logic_vector((bank_address - 1) downto 0);
00213                 ctrl_ddr_ras_L          : out std_logic;
00214                 ctrl_ddr_cas_L          : out std_logic;
00215                 ctrl_ddr_we_L           : out std_logic;
00216                 ctrl_ddr_cs_L           : out std_logic;
00217                 ctrl_ddr_cke            : out std_logic;
00218                 dummy_write_pattern     : out std_logic;
00219                 burst_length            : out std_logic_vector(2 downto 0)
00220             );
00221 end component;
00222 
00223 
00224 
00225 signal wr_df_data               : std_logic_vector((data_width*2 -1) downto 0);
00226 signal mask_df_data             : std_logic_vector((data_mask_width*2 -1) downto 0);
00227 signal rd_data_rise             : std_logic_vector((data_width -1) downto 0);
00228 signal rd_data_fall             : std_logic_vector((data_width -1) downto 0);
00229 signal af_empty_w               : std_logic;
00230 signal dq_tap_sel_done          : std_logic;
00231 signal af_addr                  : std_logic_vector(35 downto 0);
00232 signal ctrl_af_rden             : std_logic;
00233 signal ctrl_wr_df_rden          : std_logic;
00234 signal ctrl_dummy_rden          : std_logic;
00235 signal ctrl_dqs_enable          : std_logic;
00236 signal ctrl_dqs_reset           : std_logic;
00237 signal ctrl_wr_en               : std_logic;
00238 signal ctrl_rden                : std_logic;
00239 signal dqs_idelay_inc           : std_logic_vector((ReadEnable-1) downto 0);                       
00240 signal dqs_idelay_ce            : std_logic_vector((ReadEnable-1) downto 0);                       
00241 signal dqs_idelay_rst           : std_logic_vector((ReadEnable-1) downto 0);                       
00242 signal data_idelay_inc          : std_logic_vector((ReadEnable-1) downto 0);
00243 signal data_idelay_ce           : std_logic_vector((ReadEnable-1) downto 0);
00244 signal data_idelay_rst          : std_logic_vector((ReadEnable-1) downto 0);
00245 signal wr_en                    : std_logic;
00246 signal dqs_rst                  : std_logic;
00247 signal dqs_en                   : std_logic;
00248 signal wr_data_rise             : std_logic_vector((data_width -1) downto 0);
00249 signal wr_data_fall             : std_logic_vector((data_width -1) downto 0);
00250 signal dqs_delayed              : std_logic_vector((data_strobe_width-1) downto 0);
00251 signal mask_data_fall           : std_logic_vector((data_mask_width-1) downto 0);
00252 signal mask_data_rise           : std_logic_vector((data_mask_width-1) downto 0);
00253 signal ctrl_ddr_address         : std_logic_vector((row_address - 1) downto 0); 
00254 signal ctrl_ddr_ba              : std_logic_vector((bank_address - 1) downto 0);
00255 signal ctrl_ddr_ras_L           : std_logic;
00256 signal ctrl_ddr_cas_L           : std_logic;
00257 signal ctrl_ddr_we_L            : std_logic;
00258 signal ctrl_ddr_cs_L            : std_logic; 
00259 signal ctrl_ddr_cke             : std_logic;
00260 signal comp_done                : std_logic;
00261 signal dummy_write_pattern      : std_logic;
00262 
00263 
00264 
00265 begin
00266 
00267 CLK_TB   <= clk_0;      
00268 RESET_TB <= sys_rst; 
00269 
00270 
00271 
00272 data_path_00: mem_interface_top_data_path_0 port map
00273               ( 
00274                 CLK                     => clk_0,
00275                 CLK90                   => clk_90,
00276                 CAL_CLK                 => clk_50,
00277                 RESET0                  => sys_rst,
00278                 RESET90                 => sys_rst90,
00279                 RESET_CAL_CLK           => sys_rst_ref_clk_1,
00280                 idelay_ctrl_rdy         => idelay_ctrl_rdy,
00281                 dummy_write_pattern     => dummy_write_pattern,
00282                 CTRL_DUMMYREAD_START    => ctrl_dummy_rden,
00283                 WDF_DATA                => wr_df_data,
00284                 MASK_DATA                => mask_df_data ,
00285                 CTRL_WREN                => ctrl_wr_en,
00286                 CTRL_DQS_RST            => ctrl_dqs_reset,
00287                 CTRL_DQS_EN             => ctrl_dqs_enable,
00288                 dqs_delayed             => dqs_delayed,           
00289                 data_idelay_inc         => data_idelay_inc,
00290                 data_idelay_ce          => data_idelay_ce,
00291                 data_idelay_rst         => data_idelay_rst,
00292                 dqs_idelay_inc          => dqs_idelay_inc,
00293                 dqs_idelay_ce           => dqs_idelay_ce,
00294                 dqs_idelay_rst          => dqs_idelay_rst,
00295                 SEL_DONE                => dq_tap_sel_done,
00296                 dqs_rst                 => dqs_rst,
00297                 dqs_en                  => dqs_en,
00298                 wr_en                   => wr_en,                       
00299                 wr_data_rise            => wr_data_rise,                
00300                 wr_data_fall            => wr_data_fall,                
00301                 mask_data_rise          => mask_data_rise,              
00302                 mask_data_fall          => mask_data_fall         
00303         );                               
00304                                          
00305 iobs_00: mem_interface_top_iobs_0       port map                 
00306             ( CAL_CLK                   => clk_50,
00307               DDR_CK                     => DDR_CK,
00308               DDR_CK_N                  => DDR_CK_N,
00309               CLK                        => clk_0,
00310               CLK90                      => clk_90,
00311               RESET0                    => sys_rst,
00312               RESET90                    => sys_rst90,
00313               dqs_idelay_inc            => dqs_idelay_inc,    
00314               dqs_idelay_ce             => dqs_idelay_ce,    
00315               dqs_idelay_rst            => dqs_idelay_rst,    
00316               data_idelay_inc           => data_idelay_inc,     
00317               data_idelay_ce            => data_idelay_ce,    
00318               data_idelay_rst           => data_idelay_rst,   
00319               dqs_rst                   => dqs_rst,             
00320               dqs_en                     => dqs_en,         
00321               wr_en                      => wr_en,   
00322               wr_data_rise              => wr_data_rise,   
00323               wr_data_fall              => wr_data_fall,   
00324               mask_data_rise            => mask_data_rise,      
00325               mask_data_fall            => mask_data_fall, 
00326               rd_data_rise              => rd_data_rise,      
00327               rd_data_fall              => rd_data_fall,      
00328               dqs_delayed               => dqs_delayed,       
00329               DDR_DQ                    => DDR_DQ,              
00330               DDR_DQS                    => DDR_DQS ,           
00331               DDR_DM                     => DDR_DM,            
00332               ctrl_ddr_address          => ctrl_ddr_address,  
00333               ctrl_ddr_ba               => ctrl_ddr_ba, 
00334               ctrl_ddr_ras_L            => ctrl_ddr_ras_L,    
00335               ctrl_ddr_cas_L            => ctrl_ddr_cas_L,    
00336               ctrl_ddr_we_L             => ctrl_ddr_we_L,     
00337               ctrl_ddr_cs_L             => ctrl_ddr_cs_L,     
00338               ctrl_ddr_cke              => ctrl_ddr_cke,        
00339               DDR_ADDRESS               => DDR_A,
00340               DDR_BA                     => DDR_BA,
00341               DDR_RAS_L                 => DDR_RAS_N,
00342               DDR_CAS_L                 => DDR_CAS_N,
00343               DDR_WE_L                  => DDR_WE_N,
00344               DDR_CKE                    => DDR_CKE ,
00345               ddr_cs_L                  => DDR_CS_N 
00346             );                          
00347                                         
00348 user_interface_00: mem_interface_top_user_interface_0 port map
00349             ( CLK                       => clk_0,
00350               clk90                     => clk_90,
00351               RESET                     => sys_rst,
00352               ctrl_rden                 => ctrl_rden,
00353               READ_DATA_RISE            => rd_data_rise,
00354               READ_DATA_Fall            => rd_data_fall,
00355               READ_DATA_FIFO_OUT        => READ_DATA_FIFO_OUT,
00356               comp_done                 => comp_done,
00357               READ_DATA_VALID           => READ_DATA_VALID,
00358               AF_EMPTY                  => af_empty_w,
00359               AF_ALMOST_FULL            => AF_ALMOST_FULL,      
00360               APP_AF_ADDR               => APP_AF_ADDR, 
00361               APP_AF_WREN               => APP_AF_WREN, 
00362               CTRL_AF_RDEN              => ctrl_af_rden,
00363               AF_ADDR                   => af_addr,
00364               APP_WDF_DATA              => APP_WDF_DATA,
00365               APP_MASK_DATA             => APP_MASK_DATA,       
00366               APP_WDF_WREN              => APP_WDF_WREN,
00367               CTRL_WDF_RDEN             => ctrl_wr_df_rden,
00368               WDF_DATA                  => wr_df_data,
00369               MASK_DATA                 => mask_df_data,
00370               WDF_ALMOST_FULL           => WDF_ALMOST_FULL
00371              );                         
00372                                         
00373 ddr_controller_00:  mem_interface_top_ddr_controller_0 port map
00374              (                          
00375                 clk_0                   => clk_0,
00376                 refresh_clk             => ref_clk,
00377                 rst                     => sys_rst,
00378                 af_addr                 => af_addr,
00379                 af_empty                => af_empty_w,
00380                 phy_Dly_Slct_Done       => dq_tap_sel_done,
00381                 comp_done                => comp_done,
00382                 ctrl_Dummyread_Start    => ctrl_dummy_rden,
00383                 ctrl_af_RdEn            => ctrl_af_rden,
00384                 ctrl_Wdf_RdEn           => ctrl_wr_df_rden,
00385                 ctrl_Dqs_Rst            => ctrl_dqs_reset,
00386                 ctrl_Dqs_En             => ctrl_dqs_enable,
00387                 ctrl_WrEn                => ctrl_wr_en,
00388                 ctrl_RdEn                => ctrl_rden,
00389                 ctrl_ddr_address        => ctrl_ddr_address,
00390                 ctrl_ddr_ba             => ctrl_ddr_ba, 
00391                 ctrl_ddr_ras_L          => ctrl_ddr_ras_L,      
00392                 ctrl_ddr_cas_L          => ctrl_ddr_cas_L,      
00393                 ctrl_ddr_we_L           => ctrl_ddr_we_L,       
00394                 ctrl_ddr_cs_L           => ctrl_ddr_cs_L,       
00395                 ctrl_ddr_cke            => ctrl_ddr_cke,
00396                 dummy_write_pattern     => dummy_write_pattern,
00397                 burst_length            => BURST_LENGTH
00398             );  
00399 
00400             
00401 end arch;