mem_interface_top_infrastructure_iobs_0.vhd

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_infrastructure_iobs_0.vhd,v $                                                  *
--*  $Revision: 1.3.2.3 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:43 $                                                    *
--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_infrastructure_iobs_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: The DDR memory clocks are generated here using the differential buffers
--              and the ODDR elemnts in the IOBs.
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_infrastructure_iobs_0 is
        port( CLK       : in std_logic;  
              DDR_CK    : out std_logic_vector((clk_width-1) downto 0); 
              DDR_CK_N  : out std_logic_vector((clk_width-1) downto 0)
            );
end mem_interface_top_infrastructure_iobs_0;

architecture arch of mem_interface_top_infrastructure_iobs_0 is

component OBUFDS
   port (

         I   : in std_logic;
         O   : out  std_logic;
         OB  : out  std_logic
        );
end component;

component ODDR
        generic( SRTYPE         : string := "SYNC";
                 DDR_CLK_EDGE   : string := "OPPOSITE_EDGE"
               );
        port( Q   : out std_logic;
              C   : in std_logic; 
              CE  : in std_logic; 
              D1  : in std_logic; 
              D2  : in std_logic; 
              R   : in std_logic; 
              S   : in std_logic
            );
end component;     

signal DDR_CK_q         : std_logic_vector((clk_width-1) downto 0);   
signal DDR_CK_N_q       : std_logic_vector((clk_width-1) downto 0); 
signal vcc : std_logic;
signal gnd : std_logic;





begin

vcc      <= '1';
gnd      <= '0';
--DDR_CK         <=  DDR_CK_q;    
--DDR_CK_N <= DDR_CK_N_q; 


oddr_clk0: ODDR
        port map( Q   => DDR_CK_q(0),
                  C   => CLK ,
                  CE  => vcc ,
                  D1  => gnd ,
                  D2  => vcc ,
                  R   => gnd ,
                  S   => gnd 
                );       
               


oddr_clk1: ODDR
        port map( Q   => DDR_CK_q(1),
                  C   => CLK ,
                  CE  => vcc ,
                  D1  => gnd ,
                  D2  => vcc ,
                  R   => gnd ,
                  S   => gnd 
                );       
               



oddr_clk0n: ODDR
        port map( Q   => DDR_CK_N_q(0),
                  C   => CLK ,
                  CE  => vcc ,
                  D1  => vcc ,
                  D2  => gnd ,
                  R   => gnd ,
                  S   => gnd 
                );
                 


oddr_clk1n: ODDR
        port map( Q   => DDR_CK_N_q(1),
                  C   => CLK ,
                  CE  => vcc ,
                  D1  => vcc ,
                  D2  => gnd ,
                  R   => gnd ,
                  S   => gnd 
                );
                 


OBUFDS0 : OBUFDS 
        port map (
                   I  => DDR_CK_q(0),
                   O  => DDR_CK(0),
                   OB => DDR_CK_N(0)
                 );


OBUFDS1 : OBUFDS 
        port map (
                   I  => DDR_CK_q(1),
                   O  => DDR_CK(1),
                   OB => DDR_CK_N(1)
                 );



end arch;               

---

Author: M.Niegl

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