00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_v4_dqs_iob.vhd,v $
00015 --* $Revision: 1.3.2.4 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 18:48:14 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 -- Copyright (c) 2005 Xilinx, Inc.
00025 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00026 -------------------------------------------------------------------------------
00027 -- ____ ____
00028 -- / /\/ /
00029 -- /___/ \ / Vendor: Xilinx
00030 -- \ \ \/ Version: 1.6
00031 -- \ \ Application : MIG
00032 -- / / Filename: ddr2_mem_v4_dqs_iob.vhd
00033 -- /___/ /\ Date Last Modified: Wed Jun 1 2005
00034 -- \ \ / \Date Created: Mon May 2 2005
00035 -- \___\/\___\
00036 --
00037 -- Device: Virtex-4
00038 -- Design Name: DDR2_V4
00039 -------------------------------------------------------------------------------
00040
00041
00042 library ieee;
00043
00044 use ieee.std_logic_1164.all;
00045
00046 use ieee.std_logic_unsigned.all;
00047
00048 use ieee.numeric_std.all;
00049
00050 library unisim;
00051
00052 use unisim.vcomponents.all;
00053
00054
00055
00056 entity ddr2_mem_v4_dqs_iob is
00057 port (
00058 CLK : in ;
00059 CAL_CLK : in ;
00060 RESET : in ;
00061 DLYINC : in ;
00062 DLYCE : in ;
00063 DLYRST : in ;
00064 CTRL_DQS_RST : in ;
00065 CTRL_DQS_EN : in ;
00066 DDR_DQS : inout ;
00067 DDR_DQS_L : inout ;
00068 DQS_RISE : out
00069 );
00070 end entity;
00071
00072
00073
00074 architecture arc_v4_dqs_iob of ddr2_mem_v4_dqs_iob is
00075
00076
00077 component FD
00078 port(
00079 Q : out ;
00080 C : in ;
00081 D : in
00082 );
00083 end component;
00084
00085
00086 component IDELAY
00087 generic(
00088 IOBDELAY_TYPE : := "VARIABLE";
00089 IOBDELAY_VALUE : := 0
00090 );
00091 port(
00092 O : out ;
00093 C : in ;
00094 CE : in ;
00095 I : in ;
00096 INC : in ;
00097 RST : in
00098 );
00099 end component;
00100
00101
00102 component IDDR
00103 generic(
00104 DDR_CLK_EDGE : := "SAME_EDGE_PIPELINED";
00105 SRTYPE : := "SYNC"
00106 );
00107 port(
00108 Q1 : out ;
00109 Q2 : out ;
00110 C : in ;
00111 CE : in ;
00112 D : in ;
00113 R : in ;
00114 S : in
00115 );
00116 end component;
00117
00118
00119 component ODDR
00120 generic(
00121 DDR_CLK_EDGE : := "OPPOSITE_EDGE";
00122 SRTYPE : := "SYNC"
00123 );
00124 port(
00125 Q : out ;
00126 C : in ;
00127 CE : in ;
00128 D1 : in ;
00129 D2 : in ;
00130 R : in ;
00131 S : in
00132 );
00133 end component;
00134
00135
00136 component IOBUFDS
00137 port(
00138 O : out ;
00139 IO : inout ;
00140 IOB : inout ;
00141 I : in ;
00142 T : in
00143 );
00144 end component;
00145
00146 signal dqs_in : ;
00147 signal dqs_out : ;
00148 signal dqs_out_l : ;
00149 signal dqs_delayed : ;
00150 signal ctrl_dqs_en_r1 : ;
00151 signal vcc : ;
00152 signal gnd : ;
00153 signal clk180 : ;
00154 signal data1 : ;
00155 signal data2 : ;
00156 signal DQS_UNUSED : ;
00157
00158
00159
00160 begin
00161
00162 vcc <= '1';
00163 gnd <= '0';
00164 clk180 <= not CLK;
00165
00166
00167 process(clk180)
00168 begin
00169 if clk180'event and clk180 = '1' then
00170 if (CTRL_DQS_RST = '1') then
00171 data1 <= '0';
00172 else
00173 data1 <= '1';
00174 end if;
00175 end if;
00176 end process;
00177
00178
00179 process(clk180)
00180 begin
00181 if clk180'event and clk180 = '1' then
00182 if (CTRL_DQS_RST = '1') then
00183 data2 <= '1';
00184 else
00185 data2 <= '0';
00186 end if;
00187 end if;
00188 end process;
00189
00190
00191 idelay_dqs : IDELAY
00192 generic map(
00193 IOBDELAY_TYPE => "VARIABLE",
00194 IOBDELAY_VALUE => 0
00195 )
00196
00197 port map (
00198 O => dqs_delayed,
00199 I => dqs_in ,
00200 C => CAL_CLK ,
00201 CE => DLYCE,
00202 INC => DLYINC,
00203 RST => DLYRST
00204 );
00205
00206
00207 iddr_dqs : IDDR
00208 generic map(
00209 DDR_CLK_EDGE => "SAME_EDGE_PIPELINED",
00210 SRTYPE => "SYNC"
00211 )
00212 port map (
00213 Q1 => DQS_RISE ,
00214 Q2 => DQS_UNUSED,
00215 C => CLK ,
00216 CE => vcc ,
00217 D => dqs_delayed,
00218 R => RESET ,
00219 S => gnd
00220 );
00221
00222
00223 oddr_dqs : ODDR
00224 generic map(
00225 DDR_CLK_EDGE => "OPPOSITE_EDGE",
00226 SRTYPE => "SYNC"
00227 )
00228
00229 port map (
00230 Q => dqs_out,
00231 C => clk180 ,
00232 CE => vcc ,
00233 D1 => data1,
00234 D2 => gnd ,
00235 R => gnd ,
00236 S => gnd
00237 );
00238
00239
00240 oddr_dqs_l : ODDR
00241 generic map(
00242 DDR_CLK_EDGE => "OPPOSITE_EDGE",
00243 SRTYPE => "SYNC"
00244 )
00245 port map (
00246 Q => dqs_out_l,
00247 C => clk180 ,
00248 CE => vcc ,
00249 D1 => data2,
00250 D2 => vcc ,
00251 R => gnd ,
00252 S => gnd
00253 );
00254
00255
00256 tri_state_dqs : FD
00257 port map (
00258 D => CTRL_DQS_EN,
00259 Q => ctrl_dqs_en_r1,
00260 C => clk180
00261 );
00262
00263
00264 iobuf_dqs : IOBUFDS
00265 port map (
00266 O => dqs_in ,
00267 IO => DDR_DQS ,
00268 IOB => DDR_DQS_L,
00269 I => dqs_out ,
00270 T => ctrl_dqs_en_r1
00271 );
00272
00273 end arc_v4_dqs_iob;
00274