00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_rd_wr_addr_fifo_0.vhd,v $
00015 --* $Revision: 1.3.2.4 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 22:24:28 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 -- Copyright (c) 2005 Xilinx, Inc.
00025 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00026 -------------------------------------------------------------------------------
00027 -- ____ ____
00028 -- / /\/ /
00029 -- /___/ \ / Vendor: Xilinx
00030 -- \ \ \/ Version: 1.6
00031 -- \ \ Application : MIG
00032 -- / / Filename: ddr2_mem_rd_wr_addr_fifo_0.vhd
00033 -- /___/ /\ Date Last Modified: Wed Jun 1 2005
00034 -- \ \ / \Date Created: Mon May 2 2005
00035 -- \___\/\___\
00036 --
00037 -- Device: Virtex-4
00038 -- Design Name: DDR2_V4
00039 -------------------------------------------------------------------------------
00040
00041
00042 library ieee;
00043
00044 use ieee.std_logic_1164.all;
00045
00046 use ieee.std_logic_unsigned.all;
00047 library work;
00048 use work.ddr2_mem_parameters_0.all;
00049
00050 library unisim;
00051
00052 use unisim.vcomponents.all;
00053
00054
00055
00056
00057 entity ddr2_mem_rd_wr_addr_fifo_0 is
00058 port(
00059 clk0 : in ;
00060 clk90 : in ;
00061 rst : in ;
00062 app_af_addr : in (35 downto 0);
00063 app_af_WrEn : in ;
00064 ctrl_af_RdEn : in ;
00065 af_addr : out (35 downto 0);
00066 af_Empty : out ;
00067 af_Almost_full : out
00068 );
00069 end entity;
00070
00071
00072
00073
00074 architecture arc_rd_wr_addr_fifo of ddr2_mem_rd_wr_addr_fifo_0 is
00075
00076
00077 component FIFO16
00078 generic (
00079 ALMOST_FULL_OFFSET : bit_vector;
00080 ALMOST_EMPTY_OFFSET : bit_vector;
00081 DATA_WIDTH : ;
00082 FIRST_WORD_Fall_THROUGH :
00083 );
00084 port (
00085 ALMOSTEMPTY : out ;
00086 ALMOSTFULL : out ;
00087 DO : out (31 downto 0);
00088 DOP : out (3 downto 0);
00089 EMPTY : out ;
00090 FULL : out ;
00091 RDCOUNT : out (11 downto 0);
00092 RDERR : out ;
00093 WRCOUNT : out (11 downto 0);
00094 WRERR : out ;
00095 DI : in (31 downto 0);
00096 DIP : in (3 downto 0);
00097 RDCLK : in ;
00098 RDEN : in ;
00099 RST : in ;
00100 WRCLK : in ;
00101 WREN : in
00102 );
00103 end component;
00104
00105 signal fifo_input_write_addr : (35 downto 0);
00106 signal fifo_output_write_addr : (35 downto 0);
00107 signal compare_value_r : (35 downto 0);
00108 signal app_af_addr_r : (35 downto 0);
00109 signal fifo_input_addr_r : (35 downto 0);
00110 signal af_en_r : ;
00111 signal af_en_2r : ;
00112 signal compare_result : ;
00113 signal clk270 : ;
00114 signal af_al_full_0 : ;
00115 signal af_al_full_180 : ;
00116 signal af_al_full_90 : ;
00117 signal af_en_2r_270 : ;
00118 signal fifo_input_270 : (35 downto 0);
00119
00120 begin
00121
00122 clk270 <= not clk90;
00123 fifo_input_write_addr(35 downto 0) <= (compare_result & app_af_addr_r(34 downto 0));
00124 af_addr(35 downto 0) <= fifo_output_write_addr(35 downto 0);
00125 compare_result <= '0' when (compare_value_r(chip_address + bank_address + row_address + col_ap_width- 1 downto col_ap_width) =
00126 fifo_input_write_addr(chip_address + bank_address + row_address + col_ap_width- 1 downto col_ap_width))
00127 else '1';
00128
00129 process(clk0)
00130 begin
00131 if clk0'event and clk0 = '1' then
00132 if (rst = '1') then
00133 compare_value_r(35 downto 0) <= (others => '0');
00134 app_af_addr_r(35 downto 0) <= (others => '0');
00135 fifo_input_addr_r(35 downto 0) <= (others => '0');
00136 af_en_r <= '0';
00137 af_en_2r <= '0';
00138 else
00139 if (af_en_r = '1') then
00140 compare_value_r <= fifo_input_write_addr;
00141 end if;
00142 app_af_addr_r(35 downto 0) <= app_af_addr(35 downto 0);
00143 fifo_input_addr_r(35 downto 0) <= fifo_input_write_addr(35 downto 0);
00144 af_en_r <= app_af_WrEn;
00145 af_en_2r <= af_en_r;
00146 end if;
00147 end if;
00148 end process;
00149
00150
00151 process(clk270)
00152 begin
00153 if (clk270'event and clk270 = '1') then
00154 af_en_2r_270 <= af_en_2r;
00155 fifo_input_270 <= fifo_input_addr_r;
00156 end if;
00157 end process;
00158
00159
00160 process(clk0)
00161 begin
00162 if (clk0'event and clk0 = '0') then
00163 af_al_full_180 <= af_al_full_0;
00164 end if;
00165 end process;
00166
00167
00168 process(clk90)
00169 begin
00170 if (clk90'event and clk90 = '1') then
00171 af_al_full_90 <= af_al_full_180;
00172 end if;
00173 end process;
00174
00175
00176 process(clk0)
00177 begin
00178 if (clk0'event and clk0 = '1') then
00179 af_Almost_Full <= af_al_full_90;
00180 end if;
00181 end process;
00182
00183
00184 Waf_fifo16 : FIFO16
00185 generic map (
00186 ALMOST_EMPTY_OFFSET => X"007",
00187 ALMOST_FULL_OFFSET => X"00F",
00188 DATA_WIDTH => 36,
00189 FIRST_WORD_FALL_THROUGH => true
00190 )
00191 port map (
00192 ALMOSTEMPTY => open,
00193 ALMOSTFULL => af_al_full_0,
00194 DO => fifo_output_write_addr(31 downto 0),
00195 DOP => fifo_output_write_addr(35 downto 32),
00196 EMPTY => af_Empty,
00197 FULL => open,
00198 RDCOUNT => open,
00199 RDERR => open,
00200 WRCOUNT => open,
00201 WRERR => open,
00202 DI => fifo_input_270(31 downto 0),
00203 DIP => fifo_input_270(35 downto 32),
00204 RDCLK => clk0,
00205 RDEN => ctrl_af_RdEn,
00206 RST => rst,
00207 WRCLK => clk270,
00208 WREN => af_en_2r_270
00209 );
00210
00211 end arc_rd_wr_addr_fifo;
00212