buffer_3ST.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/lcd/buffer_3ST.vhd,v $
--*  $Revision: 1.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;




entity buffer_3ST is
  port (D_IN   : in  std_logic_vector (7 downto 0);
        D_OUT  : out std_logic_vector (7 downto 0);
        ENABLE : in  std_logic
        );
end buffer_3ST;




architecture buffer_3ST_arc of buffer_3ST is

begin

  D_OUT <= D_IN when ENABLE = '1' else "ZZZZZZZZ";

end buffer_3ST_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012