gt11_init_rx.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/gt11_init_rx.vhd,v $                                                  *
--*  $Revision: 1.4.2.6 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:47 $                                                    *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
--$Date: 2008/11/03 17:57:47 $
--$RCSfile: gt11_init_rx.vhd,v $
--$Revision: 1.4.2.6 $
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 1.4
--  \   \         Application : RocketIO Wizard 
--  /   /         Filename : gt11_init_rx.vhd
-- /___/   /\     Timestamp : 
-- \   \  /  \ 
--  \___\/\___\ 
--
--
-- Module GT11_INIT_RX
-- Generated by Xilinx RocketIO Wizard


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
-- synopsys translate_off

library unisim;

use unisim.vcomponents.all;
-- synopsys translate_on

--***********************************Entity Declaration*******************************

entity GT11_INIT_RX is
  generic (
    C_SIMULATION : integer := 0
    );
  port
    (
      CLK           : in  std_logic;
      START_INIT    : in  std_logic;
      LOCK          : in  std_logic;
      USRCLK_STABLE : in  std_logic;
      PCS_ERROR     : in  std_logic;
      PMA_RESET     : out std_logic;
      SYNC          : out std_logic;
      PCS_RESET     : out std_logic;
      READY         : out std_logic
      );
end GT11_INIT_RX;


architecture rtl of GT11_INIT_RX is

--********************************Parameter Declarations**********************
------------------------------------------------------------------------------
-- Delays - these numbers are defined by the number of USRCLK needed in each
--          state for each reset.  Refer to the User Guide on the block
--          diagrams on the reset and the required delay.
------------------------------------------------------------------------------

  constant C_DELAY_PMA_RESET  : unsigned(2 downto 0) := "011";

  constant C_DELAY_SYNC       : unsigned(7 downto 0) := "01000000";

  constant C_DELAY_PCS_RESET  : unsigned(2 downto 0) := "011";

  constant C_DELAY_LOCK       : unsigned(4 downto 0) := "10000";

  constant C_DELAY_WAIT_PCS   : unsigned(3 downto 0) := "0101";

  constant C_DELAY_WAIT_READY : unsigned(7 downto 0) := "01000000";

  constant C_PCS_ERROR_COUNT  : unsigned(4 downto 0) := "10000";

  constant C_RESET            : unsigned(7 downto 0) := "00000001";

  constant C_PMA_RESET        : unsigned(7 downto 0) := "00000010";

  constant C_WAIT_LOCK        : unsigned(7 downto 0) := "00000100";

  constant C_SYNC             : unsigned(7 downto 0) := "00001000";

  constant C_PCS_RESET        : unsigned(7 downto 0) := "00010000";

  constant C_WAIT_PCS         : unsigned(7 downto 0) := "00100000";

  constant C_ALMOST_READY     : unsigned(7 downto 0) := "01000000";

  constant C_READY            : unsigned(7 downto 0) := "10000000";

--*******************************Register Declarations************************
  signal reset_r                   : unsigned(1 downto 0);
  signal lock_r                    : std_logic;
  signal lock_r2                   : std_logic;
  signal pcs_error_r1              : std_logic;
  signal pcs_error_r2              : std_logic;
  signal pma_reset_count_r         : unsigned(2 downto 0);
  signal sync_count_r              : unsigned(7 downto 0);
  signal pcs_reset_count_r         : unsigned(2 downto 0);
  signal wait_pcs_count_r          : unsigned(3 downto 0);
  signal pcs_error_count_r         : unsigned(4 downto 0);
  signal wait_ready_count_r        : unsigned(7 downto 0);
  signal init_state_r              : unsigned(7 downto 0);
  signal init_next_state_r         : unsigned(7 downto 0);
  signal init_fsm_name             : unsigned(40*7 downto 0);
  signal init_fsm_wait_lock_check  : std_logic;
--*******************************Wire Declarations****************************
  signal pma_reset_done_i          : std_logic;
  signal lock_pulse_i              : std_logic;
  signal stage_1_enable_i          : std_logic;
  signal stage_2_enable_i          : std_logic;
  signal stage_3_enable_i          : std_logic;
  signal lockupdate_ready_i        : std_logic;
  signal shift_register_1_enable_i : std_logic;
  signal shift_register_2_enable_i : std_logic;
  signal shift_register_3_enable_i : std_logic;
  signal shift_register_0_d_i      : std_logic;
  signal shift_register_1_d_i      : std_logic;
  signal shift_register_2_d_i      : std_logic;
  signal shift_register_3_d_i      : std_logic;
  signal shift_register_0_q_i      : std_logic;
  signal shift_register_1_q_i      : std_logic;
  signal shift_register_2_q_i      : std_logic;
  signal shift_register_3_q_i      : std_logic;
  signal sync_done_i               : std_logic;
  signal pcs_reset_done_i          : std_logic;
  signal wait_pcs_done_i           : std_logic;
  signal pcs_error_count_done_i    : std_logic;
  signal wait_ready_done_i         : std_logic;
  signal tied_to_ground_i          : std_logic;
  signal tied_to_vcc_i             : std_logic;
  signal not_lock_i                : std_logic;

--**************************** Component Declarations ************************


  component FDE
    generic
      (
        INIT : bit := '0'
        );
    port
      (
        Q  : out std_ulogic;
        C  : in  std_ulogic;
        CE : in  std_ulogic;
        D  : in  std_ulogic
        );
  end component;


  component SRL16E
    generic
      (
        INIT : bit_vector := X"0000"
        );
    port
      (
        Q   : out std_ulogic;
        A0  : in  std_ulogic;
        A1  : in  std_ulogic;
        A2  : in  std_ulogic;
        A3  : in  std_ulogic;
        CE  : in  std_ulogic;
        CLK : in  std_ulogic;
        D   : in  std_ulogic
        );
  end component;


  component FDRE
    generic
      (
        INIT : bit := '0'
        );
    port
      (
        Q  : out std_ulogic;
        C  : in  std_ulogic;
        CE : in  std_ulogic;
        D  : in  std_ulogic;
        R  : in  std_ulogic
        );
  end component;
--**************************** Function Declaration ************************


  function ExtendString (string_in  : string;
                         string_len : integer) 
    return string is
    variable string_out : string(1 to string_len) := (others => ' ');

  begin
    if string_in'length > string_len then
      string_out := string_in(1 to string_len);
    else
      string_out(1 to string_in'length) := string_in;
    end if;
    return string_out;
  end ExtendString;

--*********************************Main Body of Code**************************

begin

  -- Static Assignments
  tied_to_ground_i <= '0';
  tied_to_vcc_i    <= '1';


  process (CLK, START_INIT)
  begin
    if (START_INIT = '1') then
      reset_r <= "11";
    elsif (rising_edge(CLK)) then
      reset_r <= '0' & reset_r(1);
    end if;
  end process;


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if (reset_r(0) = '1') then
        lock_r <= '0';
      else
        lock_r <= LOCK;
      end if;
    end if;
  end process;


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(reset_r(0) = '1') then
        pcs_error_r1 <= '0';
      else
        pcs_error_r1 <= PCS_ERROR;
      end if;
    end if;
  end process;

  -- Ready, PMA and PCS reset signals
  PMA_RESET <= '1' when (init_state_r = C_PMA_RESET) else '0';
  SYNC      <= '1' when (init_state_r = C_SYNC)      else '0';
  PCS_RESET <= '1' when (init_state_r = C_PCS_RESET) else '0';
  READY     <= '1' when (init_state_r = C_READY)     else '0';


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_PMA_RESET) then
        pma_reset_count_r <= C_DELAY_PMA_RESET;
      else
        pma_reset_count_r <= pma_reset_count_r - 1;
      end if;
    end if;
  end process;

  pma_reset_done_i <= '1' when (pma_reset_count_r = 1) else '0';

  for_simulation : if (C_SIMULATION /= 0) generate
  begin
    lockupdate_ready_i <= tied_to_vcc_i;
  end generate for_simulation;

  for_hardware : if (C_SIMULATION = 0) generate
  begin




    process(CLK)
    begin
      if(CLK'event and CLK = '1') then
        if (reset_r(0) = '1') then
          lock_r2 <= '0';
        else
          lock_r2 <= lock_r;
        end if;
      end if;
    end process;

    lock_pulse_i <= lock_r and not lock_r2;

    -- SRL16 Stage Zero - First stage of shifting
    shift_register_0_d_i <= lock_r and (lock_pulse_i or stage_1_enable_i);








    shift_register_0 : SRL16E
      port map
      (
        Q   => shift_register_0_q_i,
        A0  => tied_to_ground_i,
        A1  => tied_to_vcc_i,
        A2  => tied_to_vcc_i,
        A3  => tied_to_vcc_i,
        CE  => tied_to_vcc_i,
        CLK => CLK ,
        D   => shift_register_0_d_i
        );


    flop_stage_0 : FDE
      port map
      (
        Q  => stage_1_enable_i,
        C  => CLK ,
        CE => tied_to_vcc_i,
        D  => shift_register_0_q_i
        );

    shift_register_1_d_i <= lock_r and (lock_pulse_i or
                                        (stage_1_enable_i and stage_2_enable_i));
    shift_register_1_enable_i <= not lock_r2 or stage_1_enable_i;


    shift_register_1 : SRL16E
      port map
      (
        Q   => shift_register_1_q_i,
        A0  => tied_to_ground_i,
        A1  => tied_to_vcc_i,
        A2  => tied_to_vcc_i,
        A3  => tied_to_vcc_i,
        CE  => shift_register_1_enable_i,
        CLK => CLK ,
        D   => shift_register_1_d_i
        );


    flop_stage_1 : FDE
      port map
      (
        Q  => stage_2_enable_i,
        C  => CLK ,
        CE  => shift_register_1_enable_i,
        D  => shift_register_1_q_i
        );

    shift_register_2_d_i <= lock_r and (lock_pulse_i or
                                        (stage_1_enable_i and stage_2_enable_i and
                                         stage_3_enable_i));

    shift_register_2_enable_i <= not lock_r2 or
                                 (stage_1_enable_i and stage_2_enable_i);


    shift_register_2 : SRL16E
      port map
      (
        Q   => shift_register_2_q_i,
        A0  => tied_to_ground_i,
        A1  => tied_to_vcc_i,
        A2  => tied_to_vcc_i,
        A3  => tied_to_vcc_i,
        CE  => shift_register_2_enable_i,
        CLK => CLK ,
        D   => shift_register_2_d_i
        );


    flop_stage_2 : FDE
      port map
      (
        Q  => stage_3_enable_i,
        C  => CLK ,
        CE => shift_register_2_enable_i,
        D  => shift_register_2_q_i
        );

    shift_register_3_d_i <= lock_r and (lock_pulse_i or
                                        (stage_1_enable_i and stage_2_enable_i and
                                         stage_3_enable_i and lockupdate_ready_i));

    shift_register_3_enable_i <= not lock_r2 or
                                 (stage_1_enable_i and stage_2_enable_i and
                                  stage_3_enable_i and not lockupdate_ready_i);




    shift_register_3 : SRL16E
      port map
      (
        Q   => shift_register_3_q_i,
        A0  => tied_to_vcc_i,
        A1  => tied_to_vcc_i,
        A2  => tied_to_ground_i,
        A3  => tied_to_ground_i,
        CE  => shift_register_3_enable_i,
        CLK => CLK ,
        D   => shift_register_3_d_i
        );

    not_lock_i <= not lock_r;


    flop_stage_3 : FDRE
      port map
      (
        Q  => lockupdate_ready_i,
        C  => CLK ,
        CE => shift_register_3_enable_i,
        D  => shift_register_3_q_i,
        R  => not_lock_i
        );
  end generate for_hardware;


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_SYNC) then
        sync_count_r <= C_DELAY_SYNC;
      else
        sync_count_r <= sync_count_r - 1;
      end if;
    end if;
  end process;

  sync_done_i <= '1' when (sync_count_r = 1) else '0';


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_PCS_RESET) then
        pcs_reset_count_r <= C_DELAY_PCS_RESET;
      else
        pcs_reset_count_r <= pcs_reset_count_r - 1;
      end if;
    end if;
  end process;

  pcs_reset_done_i <= '1' when (pcs_reset_count_r = 1) else '0';


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r /= C_WAIT_PCS) then
        wait_pcs_count_r <= C_DELAY_WAIT_PCS;
      else
        wait_pcs_count_r <= wait_pcs_count_r - 1;
      end if;
    end if;
  end process;

  wait_pcs_done_i <= '1' when (wait_pcs_count_r = 1) else '0';


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if(init_state_r = C_PMA_RESET) then
        pcs_error_count_r <= C_PCS_ERROR_COUNT;
      elsif (((init_state_r = C_ALMOST_READY) or (init_state_r = C_READY)) and (pcs_error_r1 and lock_r) = '1') then
        pcs_error_count_r <= pcs_error_count_r - 1;
      end if;
    end if;
  end process;

  pcs_error_count_done_i <= '1' when (pcs_error_count_r = 1) else '0';


  process(CLK)
  begin
    if(CLK'event and CLK = '1') then
      if((init_state_r /= C_ALMOST_READY) or (pcs_error_r1 = '1')) then
        wait_ready_count_r <= C_DELAY_WAIT_READY;
      elsif(pcs_error_r1 = '0') then
        wait_ready_count_r <= wait_ready_count_r - 1;
      end if;
    end if;
  end process;

  wait_ready_done_i <= '1' when (wait_ready_count_r = 1) else '0';


  process (CLK)
  begin
    if (rising_edge(CLK)) then
      if (reset_r(0) = '1') then
        init_state_r <= C_RESET;
      else
        init_state_r <= init_next_state_r;
      end if;
    end if;
  end process;

  init_fsm_wait_lock_check <= lock_r and USRCLK_STABLE and lockupdate_ready_i;
































  process (reset_r(0), pma_reset_done_i, init_fsm_wait_lock_check, lock_r,
           sync_done_i, pcs_reset_done_i, wait_pcs_done_i, pcs_error_r1,
           pcs_error_count_done_i, wait_ready_done_i)
    variable init_fsm_name : string(1 to 25);
  begin
    case init_state_r is
      
      when C_RESET =>
        
        if (reset_r(0) = '1') then
          init_next_state_r <= C_RESET;
        else
          init_next_state_r <= C_PMA_RESET;
        end if;
        init_fsm_name := ExtendString("C_RESET", 25);

      when C_PMA_RESET =>

        if (pma_reset_done_i = '1') then
          init_next_state_r <= C_WAIT_LOCK;
        else
          init_next_state_r <= C_PMA_RESET;
        end if;
        init_fsm_name := ExtendString("C_PMA_RESET", 25);

      when C_WAIT_LOCK =>
        
        if(init_fsm_wait_lock_check = '1') then
          init_next_state_r <= C_SYNC;
        else
          init_next_state_r <= C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_WAIT_LOCK", 25);

      when C_SYNC =>
        if (lock_r = '1') then
          if (sync_done_i = '1') then
            init_next_state_r <= C_PCS_RESET;
          else
            init_next_state_r <= C_SYNC;
          end if;
        else
          init_next_state_r <= C_PMA_RESET;  --C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_SYNC", 25);

      when C_PCS_RESET =>
        if (lock_r = '1') then
          if (pcs_reset_done_i = '1') then
            init_next_state_r <= C_WAIT_PCS;
          else
            init_next_state_r <= C_PCS_RESET;
          end if;
        else
          init_next_state_r <= C_PMA_RESET;  --C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_PCS_RESET", 25);

      when C_WAIT_PCS =>
        if (lock_r = '1') then
          if (wait_pcs_done_i = '1') then
            init_next_state_r <= C_ALMOST_READY;
          else
            init_next_state_r <= C_WAIT_PCS;
          end if;
        else
          init_next_state_r <= C_PMA_RESET;  --C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_WAIT_PCS", 25);

      when C_ALMOST_READY =>
        if (lock_r = '0') then
          init_next_state_r <= C_PMA_RESET;  --C_WAIT_LOCK;
        elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '0')) then
          init_next_state_r <= C_SYNC;
        elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '1')) then
          init_next_state_r <= C_PMA_RESET;
        elsif (wait_ready_done_i = '1') then
          init_next_state_r <= C_READY;
        else
          init_next_state_r <= C_ALMOST_READY;
        end if;
        init_fsm_name := ExtendString("C_ALMOST_READY", 25);

      when C_READY =>
        if ((lock_r = '1') and (pcs_error_r1 = '0')) then
          init_next_state_r <= C_READY;
        elsif ((lock_r = '1') and (pcs_error_r1 = '1')) then
          init_next_state_r <= C_PCS_RESET;
        else
          init_next_state_r <= C_PMA_RESET;  --C_WAIT_LOCK;
        end if;
        init_fsm_name := ExtendString("C_READY", 25);

      when others =>
        init_next_state_r <= C_RESET;
        init_fsm_name     := ExtendString("C_RESET", 25);

    end case;
  end process;

end rtl;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012