period_check.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/period_check.vhd,v $
--*  $Revision: 2.0.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;




entity period_check is
  
  generic (
    PERIOD : integer range 0 to 255 := 8);
  port (
    CLK : in  std_logic;
    RES : in  std_logic;
    EN  : in  std_logic;
    A   : in  std_logic;
    Y   : out std_logic
    );

end period_check;






architecture period_check_arc of period_check is

  signal res_n     : std_logic                    := '1';
  signal ok        : std_logic                    := '0';
  signal per_cnt_0 : std_logic_vector(3 downto 0) := (others => '0');
  signal per_cnt_1 : std_logic_vector(3 downto 0) := (others => '0');

begin  -- period_check_arc

  res_n <= not RES;
  Y     <= ok when rising_edge(CLK);


  onescnt : process (CLK, res_n)
    variable cnt : integer range 0 to 255 := 0;
  begin  -- process onescnt
    if res_n = '0' then                 -- asynchronous reset (active low)
      cnt       := 0;
      per_cnt_1 <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if EN = '1' and ok = '0' then
        if A = '1' then
          cnt := cnt + 1;
        else
          if cnt = PERIOD/2 then
            per_cnt_1 <= per_cnt_1 + '1';
          elsif cnt /= 0 then
            per_cnt_1 <= (others => '0');
          else
            per_cnt_1 <= per_cnt_1;
          end if;
          cnt := 0;
        end if;
      else
        cnt       := cnt;
        per_cnt_1 <= per_cnt_1;
      end if;
    end if;
  end process onescnt;


  zeroscnt : process (CLK, res_n)
    variable cnt : integer range 0 to 255 := 0;
  begin  -- process onescnt
    if res_n = '0' then                 -- asynchronous reset (active low)
      cnt       := 0;
      per_cnt_0 <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if EN = '1' and ok = '0' then
        if A = '0' then
          cnt := cnt + 1;
        else
          if cnt = PERIOD/2 then
            per_cnt_0 <= per_cnt_0 + '1';
          elsif cnt /= 0 then
            per_cnt_0 <= (others => '0');
          else
            per_cnt_0 <= per_cnt_0;
          end if;
          cnt := 0;
        end if;
      else
        cnt       := cnt;
        per_cnt_0 <= per_cnt_0;
      end if;
    end if;
  end process zeroscnt;

  ok <= '0' when res_n = '0' else
        '1' when per_cnt_0 >= 3 and per_cnt_1 >= 3 else
        '0';

end period_check_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012