00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/delay.vhd,v $
00015 --* $Revision: 1.6.2.3 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:45 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023
00024 library ieee;
00025
00026 use ieee.std_logic_1164.all;
00027
00028 use ieee.std_logic_arith.all;
00029
00030 use ieee.std_logic_unsigned.all;
00031
00032
00033 entity delay is
00034 generic (i : range 0 to 99 := 00
00035 );
00036 port (A : in ;
00037 A_DEL : out ;
00038 CLK : in ;
00039 RES : in
00040 );
00041 end delay;
00042
00043
00044 architecture delay_arc of delay is
00045
00046 signal shift : (99 downto 0) := (others => '0');
00047
00048 begin
00049
00050
00051 delay_signal : process(CLK)
00052 begin
00053 if CLK'event and CLK = '1' then
00054 if RES = '1' then
00055 shift <= (others => '0');
00056 A_DEL <= '0';
00057 else
00058 shift <= shift(98 downto 0) & A;
00059 A_DEL <= shift(i);
00060 end if;
00061 end if;
00062 end process delay_signal;
00063
00064 end delay_arc;
00065