ORBIT_cnt.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/ORBIT_cnt.vhd,v $
--*  $Revision: 1.8.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;




entity ORBIT_cnt is
  port (
    RESET         : in  std_logic;
    CLK           : in  std_logic;
    ORBIT         : in  std_logic;
    ORBIT_LOAD_EN : in  std_logic;
    ORBIT_LOAD    : in  std_logic_vector(31 downto 0);
    START_RUN     : in  std_logic;
    CNT_ORBIT     : out std_logic_vector (31 downto 0));
end ORBIT_cnt;





architecture ORBIT_cnt_arc of ORBIT_cnt is

  signal cnt_i : std_logic_vector (31 downto 0) := (others => '0');
  signal orb   : std_logic                      := '0';
  component edge is
    port (CLK   : in  std_logic;
          A     : in  std_logic;
          PULSE : out std_logic);
  end component;

begin

  CNT_ORBIT <= cnt_i;


  orb_edge : edge
    port map (
      CLK   => CLK ,
      A     => ORBIT ,
      PULSE => orb 
      );


  cnt : process(CLK)
  begin
    if CLK'event and CLK = '1' then
      if (START_RUN or RESET) = '1' then
        cnt_i <= (others => '0');
      elsif ORBIT_LOAD_EN = '1' then
        cnt_i <= ORBIT_LOAD;
      elsif orb = '1' then
        cnt_i <= cnt_i + 1;
      else
        cnt_i <= cnt_i;
      end if;
    end if;
  end process;
  
end ORBIT_cnt_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012