comparator_v9_0.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/comparator_v9_0.vhd,v $
--*  $Revision: 1.3.2.4 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *


--*                                                            *
--**************************************************************
--------------------------------------------------------------------------------
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--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
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--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--------------------------------------------------------------------------------
-- You must compile the wrapper file comparator_v9_0.vhd when simulating
-- the core, comparator_v9_0. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

library ieee;
use ieee.std_logic_1164.all;
-- synopsys translate_off
library XilinxCoreLib;
-- synopsys translate_on

entity comparator_v9_0 is
  port (
    a       : in  std_logic_vector(5 downto 0);
    b       : in  std_logic_vector(5 downto 0);
    clk     : in  std_logic;
    ce      : in  std_logic;
    a_ge_b  : out std_logic;
    qa_ge_b : out std_logic
    );
end comparator_v9_0;


architecture comparator_v9_0_a of comparator_v9_0 is
-- synopsys translate_off

  component wrapped_comparator_v9_0
    port (
      a       : in  std_logic_vector(5 downto 0);
      b       : in  std_logic_vector(5 downto 0);
      clk     : in  std_logic;
      ce      : in  std_logic;
      a_ge_b  : out std_logic;
      qa_ge_b : out std_logic
      );
  end component;

-- Configuration specification 
  for all : wrapped_comparator_v9_0 use entity XilinxCoreLib.c_compare_v9_0(behavioral)
    generic map(
      c_has_qa_ge_b               => 1,
      c_has_aset                  => 0,
      c_has_qa_lt_b               => 0,
      c_has_qa_ne_b               => 0,
      c_has_a_gt_b                => 0,
      c_has_a_eq_b                => 0,
      c_data_type                 => 1,
      c_sync_priority             => 1,
      c_has_sclr                  => 0,
      c_has_qa_gt_b               => 0,
      c_width                     => 6,
      c_has_qa_eq_b               => 0,
      c_enable_rlocs              => 0,
      c_infered_rtl_const_compare => 0,
      c_carry_chain_eq_ne         => 0,
      c_has_a_le_b                => 0,
      c_ainit_val                 => "0",
      c_dense_lut_packing         => 0,
      c_has_ce                    => 1,
      c_pipe_stages               => 0,
      c_has_aclr                  => 0,
      c_sync_enable               => 0,
      c_has_sset                  => 0,
      c_has_qa_le_b               => 0,
      c_b_constant                => 0,
      c_has_a_ge_b                => 1,
      c_has_a_ne_b                => 0,
      c_has_a_lt_b                => 0,
      c_b_value                   => "0000000000000000"
      );
-- synopsys translate_on
begin
-- synopsys translate_off

  U0 : wrapped_comparator_v9_0
    port map (
      a       => a ,
      b       => b ,
      clk     => clk ,
      ce      => ce ,
      a_ge_b  => a_ge_b,
      qa_ge_b => qa_ge_b
      );
-- synopsys translate_on

end comparator_v9_0_a;

---

Author: M.Niegl

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