00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_data_path_iobs_0.vhd,v $ *
00015 --* $Revision: 1.3.2.3 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:43 $ *
00019 --* *
00020 --**************************************************************
00021 -------------------------------------------------------------------------------
00022 -- Copyright (c) 2005 Xilinx, Inc.
00023 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00024 -------------------------------------------------------------------------------
00025 -- ____ ____
00026 -- / /\/ /
00027 -- /___/ \ / Vendor: Xilinx
00028 -- \ \ \/ Version: 1.6
00029 -- \ \ Application : MIG
00030 -- / / Filename: mem_interface_top_data_path_iobs_0.vhd
00031 -- /___/ /\ Date Last Modified: Wed Jun 1 2005
00032 -- \ \ / \Date Created: Mon May 2 2005
00033 -- \___\/\___\
00034 -- Device: Virtex-4
00035 -- Design Name: DDR1_SDRAM
00036 -- Description: This module instantiates data, data strobe and the data mask iobs.
00037 -------------------------------------------------------------------------------
00038
00039
00040 library ieee;
00041
00042 use ieee.std_logic_1164.all;
00043
00044 library unisim;
00045
00046 use unisim.vcomponents.all;
00047 use work.mem_interface_top_parameters_0.all;
00048
00049 entity mem_interface_top_data_path_iobs_0 is
00050 port ( CLK : in ;
00051 CLK90 : in ;
00052 CAL_CLK : in ;
00053 RESET0 : in ;
00054 RESET90 : in ;
00055 dqs_idelay_inc : in ((ReadEnable - 1) downto 0);
00056 dqs_idelay_ce : in ((ReadEnable - 1) downto 0);
00057 dqs_idelay_rst : in ((ReadEnable - 1) downto 0);
00058 dqs_rst : in ;
00059 dqs_en : in ;
00060 dqs_delayed : out ((data_strobe_width -1) downto 0);
00061
00062 data_idelay_inc : in ((ReadEnable - 1) downto 0);
00063 data_idelay_ce : in ((ReadEnable - 1) downto 0);
00064 data_idelay_rst : in ((ReadEnable - 1) downto 0);
00065 wr_data_rise : in ((data_width -1) downto 0);
00066 wr_data_fall : in ((data_width -1) downto 0);
00067 wr_en : in ;
00068 rd_data_rise : out ((data_width -1) downto 0);
00069 rd_data_fall : out ((data_width -1) downto 0);
00070 mask_data_rise : in ((data_mask_width -1) downto 0);
00071 mask_data_fall : in ((data_mask_width -1) downto 0);
00072 DDR_DQ : inout ((data_width -1) downto 0);
00073 DDR_DQS : inout ((data_strobe_width -1) downto 0);
00074 DDR_DM : out ((data_mask_width -1) downto 0)
00075 );
00076 end mem_interface_top_data_path_iobs_0;
00077
00078 architecture arch of mem_interface_top_data_path_iobs_0 is
00079
00080 component mem_interface_top_v4_dqs_iob
00081 port(
00082 CLK : in ;
00083 CAL_CLK : in ;
00084 DLYINC : in ;
00085 DLYCE : in ;
00086 DLYRST : in ;
00087 CTRL_DQS_RST : in ;
00088 CTRL_DQS_EN : in ;
00089 DDR_DQS : inout ;
00090 DQS_RISE : out
00091 );
00092 end component;
00093
00094 component mem_interface_top_v4_dm_iob
00095 port(
00096 CLK90 : in ;
00097 MASK_DATA_RISE : in ;
00098 MASK_DATA_Fall : in ;
00099 DDR_DM : out
00100 );
00101 end component;
00102
00103 component mem_interface_top_v4_dq_iob
00104 port(
00105 CLK : in ;
00106 CLK90 : in ;
00107 CAL_CLK : in ;
00108 RESET : in ;
00109 DATA_DLYINC : in ;
00110 DATA_DLYCE : in ;
00111 DATA_DLYRST : in ;
00112 WRITE_DATA_RISE : in ;
00113 WRITE_DATA_Fall : in ;
00114 CTRL_WREN : in ;
00115 DDR_DQ : inout ;
00116 READ_DATA_RISE : out ;
00117 READ_DATA_Fall : out
00118 );
00119 end component;
00120
00121 component mem_interface_top_idelay_rd_en_io_0
00122 port( CLK : in ;
00123 CLK90 : in ;
00124 CAL_CLK : in ;
00125 DATA_DLYINC : in ;
00126 DATA_DLYCE : in ;
00127 DATA_DLYRST : in ;
00128 CTRL_RD_EN : in ;
00129 READ_EN_IN : in ;
00130 READ_EN_OUT : out ;
00131 rd_en_delayed_r1 : out ;
00132 rd_en_delayed_r2 : out
00133 );
00134 end component;
00135
00136 begin
00137
00138 --**************************************************************************************************************
00139 -- DQS instances
00140 --**************************************************************************************************************
00141
00142
00143 v4_dqs_iob0 : mem_interface_top_v4_dqs_iob port map
00144 (
00145 CLK => CLK,
00146 CAL_CLK => CAL_CLK,
00147 DLYINC => dqs_idelay_inc(0),
00148 DLYCE => dqs_idelay_ce(0),
00149 DLYRST => dqs_idelay_rst(0),
00150 CTRL_DQS_RST => dqs_rst,
00151 CTRL_DQS_EN => dqs_en,
00152 DDR_DQS => DDR_DQS(0),
00153 DQS_RISE => dqs_delayed(0)
00154 );
00155
00156
00157
00158 v4_dqs_iob1 : mem_interface_top_v4_dqs_iob port map
00159 (
00160 CLK => CLK,
00161 CAL_CLK => CAL_CLK,
00162 DLYINC => dqs_idelay_inc(0),
00163 DLYCE => dqs_idelay_ce(0),
00164 DLYRST => dqs_idelay_rst(0),
00165 CTRL_DQS_RST => dqs_rst,
00166 CTRL_DQS_EN => dqs_en,
00167 DDR_DQS => DDR_DQS(1),
00168 DQS_RISE => dqs_delayed(1)
00169 );
00170
00171
00172
00173 v4_dqs_iob2 : mem_interface_top_v4_dqs_iob port map
00174 (
00175 CLK => CLK,
00176 CAL_CLK => CAL_CLK,
00177 DLYINC => dqs_idelay_inc(0),
00178 DLYCE => dqs_idelay_ce(0),
00179 DLYRST => dqs_idelay_rst(0),
00180 CTRL_DQS_RST => dqs_rst,
00181 CTRL_DQS_EN => dqs_en,
00182 DDR_DQS => DDR_DQS(2),
00183 DQS_RISE => dqs_delayed(2)
00184 );
00185
00186
00187
00188 v4_dqs_iob3 : mem_interface_top_v4_dqs_iob port map
00189 (
00190 CLK => CLK,
00191 CAL_CLK => CAL_CLK,
00192 DLYINC => dqs_idelay_inc(0),
00193 DLYCE => dqs_idelay_ce(0),
00194 DLYRST => dqs_idelay_rst(0),
00195 CTRL_DQS_RST => dqs_rst,
00196 CTRL_DQS_EN => dqs_en,
00197 DDR_DQS => DDR_DQS(3),
00198 DQS_RISE => dqs_delayed(3)
00199 );
00200
00201
00202
00203 --*************************************************************************************************************
00204 -- DM instances
00205 --*************************************************************************************************************
00206
00207
00208 v4_dm_iob0 : mem_interface_top_v4_dm_iob port map
00209 (
00210 CLK90 => CLK90,
00211 MASK_DATA_RISE => mask_data_rise(0),
00212 MASK_DATA_Fall => mask_data_fall(0),
00213 DDR_DM => DDR_DM(0)
00214 );
00215
00216
00217
00218
00219 v4_dm_iob1 : mem_interface_top_v4_dm_iob port map
00220 (
00221 CLK90 => CLK90,
00222 MASK_DATA_RISE => mask_data_rise(1),
00223 MASK_DATA_Fall => mask_data_fall(1),
00224 DDR_DM => DDR_DM(1)
00225 );
00226
00227
00228
00229
00230 v4_dm_iob2 : mem_interface_top_v4_dm_iob port map
00231 (
00232 CLK90 => CLK90,
00233 MASK_DATA_RISE => mask_data_rise(2),
00234 MASK_DATA_Fall => mask_data_fall(2),
00235 DDR_DM => DDR_DM(2)
00236 );
00237
00238
00239
00240
00241 v4_dm_iob3 : mem_interface_top_v4_dm_iob port map
00242 (
00243 CLK90 => CLK90,
00244 MASK_DATA_RISE => mask_data_rise(3),
00245 MASK_DATA_Fall => mask_data_fall(3),
00246 DDR_DM => DDR_DM(3)
00247 );
00248
00249
00250
00251
00252 --*************************************************************************************************************
00253 -- DQ_IOB4 instances
00254 --*************************************************************************************************************
00255
00256
00257 v4_dq_iob_0 : mem_interface_top_v4_dq_iob port map
00258 (
00259 CLK => CLK,
00260 CLK90 => CLK90,
00261 CAL_CLK => CAL_CLK,
00262 RESET => RESET90,
00263 DATA_DLYINC => data_idelay_inc(0),
00264 DATA_DLYCE => data_idelay_ce(0),
00265 DATA_DLYRST => data_idelay_rst(0),
00266 WRITE_DATA_RISE => wr_data_rise(0),
00267 WRITE_DATA_Fall => wr_data_fall(0),
00268 CTRL_WREN => wr_en,
00269 DDR_DQ => DDR_DQ(0),
00270 READ_DATA_RISE => rd_data_rise(0),
00271 READ_DATA_Fall => rd_data_fall(0)
00272 );
00273
00274
00275
00276 v4_dq_iob_1 : mem_interface_top_v4_dq_iob port map
00277 (
00278 CLK => CLK,
00279 CLK90 => CLK90,
00280 CAL_CLK => CAL_CLK,
00281 RESET => RESET90,
00282 DATA_DLYINC => data_idelay_inc(0),
00283 DATA_DLYCE => data_idelay_ce(0),
00284 DATA_DLYRST => data_idelay_rst(0),
00285 WRITE_DATA_RISE => wr_data_rise(1),
00286 WRITE_DATA_Fall => wr_data_fall(1),
00287 CTRL_WREN => wr_en,
00288 DDR_DQ => DDR_DQ(1),
00289 READ_DATA_RISE => rd_data_rise(1),
00290 READ_DATA_Fall => rd_data_fall(1)
00291 );
00292
00293
00294
00295 v4_dq_iob_2 : mem_interface_top_v4_dq_iob port map
00296 (
00297 CLK => CLK,
00298 CLK90 => CLK90,
00299 CAL_CLK => CAL_CLK,
00300 RESET => RESET90,
00301 DATA_DLYINC => data_idelay_inc(0),
00302 DATA_DLYCE => data_idelay_ce(0),
00303 DATA_DLYRST => data_idelay_rst(0),
00304 WRITE_DATA_RISE => wr_data_rise(2),
00305 WRITE_DATA_Fall => wr_data_fall(2),
00306 CTRL_WREN => wr_en,
00307 DDR_DQ => DDR_DQ(2),
00308 READ_DATA_RISE => rd_data_rise(2),
00309 READ_DATA_Fall => rd_data_fall(2)
00310 );
00311
00312
00313
00314 v4_dq_iob_3 : mem_interface_top_v4_dq_iob port map
00315 (
00316 CLK => CLK,
00317 CLK90 => CLK90,
00318 CAL_CLK => CAL_CLK,
00319 RESET => RESET90,
00320 DATA_DLYINC => data_idelay_inc(0),
00321 DATA_DLYCE => data_idelay_ce(0),
00322 DATA_DLYRST => data_idelay_rst(0),
00323 WRITE_DATA_RISE => wr_data_rise(3),
00324 WRITE_DATA_Fall => wr_data_fall(3),
00325 CTRL_WREN => wr_en,
00326 DDR_DQ => DDR_DQ(3),
00327 READ_DATA_RISE => rd_data_rise(3),
00328 READ_DATA_Fall => rd_data_fall(3)
00329 );
00330
00331
00332
00333 v4_dq_iob_4 : mem_interface_top_v4_dq_iob port map
00334 (
00335 CLK => CLK,
00336 CLK90 => CLK90,
00337 CAL_CLK => CAL_CLK,
00338 RESET => RESET90,
00339 DATA_DLYINC => data_idelay_inc(0),
00340 DATA_DLYCE => data_idelay_ce(0),
00341 DATA_DLYRST => data_idelay_rst(0),
00342 WRITE_DATA_RISE => wr_data_rise(4),
00343 WRITE_DATA_Fall => wr_data_fall(4),
00344 CTRL_WREN => wr_en,
00345 DDR_DQ => DDR_DQ(4),
00346 READ_DATA_RISE => rd_data_rise(4),
00347 READ_DATA_Fall => rd_data_fall(4)
00348 );
00349
00350
00351
00352 v4_dq_iob_5 : mem_interface_top_v4_dq_iob port map
00353 (
00354 CLK => CLK,
00355 CLK90 => CLK90,
00356 CAL_CLK => CAL_CLK,
00357 RESET => RESET90,
00358 DATA_DLYINC => data_idelay_inc(0),
00359 DATA_DLYCE => data_idelay_ce(0),
00360 DATA_DLYRST => data_idelay_rst(0),
00361 WRITE_DATA_RISE => wr_data_rise(5),
00362 WRITE_DATA_Fall => wr_data_fall(5),
00363 CTRL_WREN => wr_en,
00364 DDR_DQ => DDR_DQ(5),
00365 READ_DATA_RISE => rd_data_rise(5),
00366 READ_DATA_Fall => rd_data_fall(5)
00367 );
00368
00369
00370
00371 v4_dq_iob_6 : mem_interface_top_v4_dq_iob port map
00372 (
00373 CLK => CLK,
00374 CLK90 => CLK90,
00375 CAL_CLK => CAL_CLK,
00376 RESET => RESET90,
00377 DATA_DLYINC => data_idelay_inc(0),
00378 DATA_DLYCE => data_idelay_ce(0),
00379 DATA_DLYRST => data_idelay_rst(0),
00380 WRITE_DATA_RISE => wr_data_rise(6),
00381 WRITE_DATA_Fall => wr_data_fall(6),
00382 CTRL_WREN => wr_en,
00383 DDR_DQ => DDR_DQ(6),
00384 READ_DATA_RISE => rd_data_rise(6),
00385 READ_DATA_Fall => rd_data_fall(6)
00386 );
00387
00388
00389
00390 v4_dq_iob_7 : mem_interface_top_v4_dq_iob port map
00391 (
00392 CLK => CLK,
00393 CLK90 => CLK90,
00394 CAL_CLK => CAL_CLK,
00395 RESET => RESET90,
00396 DATA_DLYINC => data_idelay_inc(0),
00397 DATA_DLYCE => data_idelay_ce(0),
00398 DATA_DLYRST => data_idelay_rst(0),
00399 WRITE_DATA_RISE => wr_data_rise(7),
00400 WRITE_DATA_Fall => wr_data_fall(7),
00401 CTRL_WREN => wr_en,
00402 DDR_DQ => DDR_DQ(7),
00403 READ_DATA_RISE => rd_data_rise(7),
00404 READ_DATA_Fall => rd_data_fall(7)
00405 );
00406
00407
00408
00409 v4_dq_iob_8 : mem_interface_top_v4_dq_iob port map
00410 (
00411 CLK => CLK,
00412 CLK90 => CLK90,
00413 CAL_CLK => CAL_CLK,
00414 RESET => RESET90,
00415 DATA_DLYINC => data_idelay_inc(0),
00416 DATA_DLYCE => data_idelay_ce(0),
00417 DATA_DLYRST => data_idelay_rst(0),
00418 WRITE_DATA_RISE => wr_data_rise(8),
00419 WRITE_DATA_Fall => wr_data_fall(8),
00420 CTRL_WREN => wr_en,
00421 DDR_DQ => DDR_DQ(8),
00422 READ_DATA_RISE => rd_data_rise(8),
00423 READ_DATA_Fall => rd_data_fall(8)
00424 );
00425
00426
00427
00428 v4_dq_iob_9 : mem_interface_top_v4_dq_iob port map
00429 (
00430 CLK => CLK,
00431 CLK90 => CLK90,
00432 CAL_CLK => CAL_CLK,
00433 RESET => RESET90,
00434 DATA_DLYINC => data_idelay_inc(0),
00435 DATA_DLYCE => data_idelay_ce(0),
00436 DATA_DLYRST => data_idelay_rst(0),
00437 WRITE_DATA_RISE => wr_data_rise(9),
00438 WRITE_DATA_Fall => wr_data_fall(9),
00439 CTRL_WREN => wr_en,
00440 DDR_DQ => DDR_DQ(9),
00441 READ_DATA_RISE => rd_data_rise(9),
00442 READ_DATA_Fall => rd_data_fall(9)
00443 );
00444
00445
00446
00447 v4_dq_iob_10 : mem_interface_top_v4_dq_iob port map
00448 (
00449 CLK => CLK,
00450 CLK90 => CLK90,
00451 CAL_CLK => CAL_CLK,
00452 RESET => RESET90,
00453 DATA_DLYINC => data_idelay_inc(0),
00454 DATA_DLYCE => data_idelay_ce(0),
00455 DATA_DLYRST => data_idelay_rst(0),
00456 WRITE_DATA_RISE => wr_data_rise(10),
00457 WRITE_DATA_Fall => wr_data_fall(10),
00458 CTRL_WREN => wr_en,
00459 DDR_DQ => DDR_DQ(10),
00460 READ_DATA_RISE => rd_data_rise(10),
00461 READ_DATA_Fall => rd_data_fall(10)
00462 );
00463
00464
00465
00466 v4_dq_iob_11 : mem_interface_top_v4_dq_iob port map
00467 (
00468 CLK => CLK,
00469 CLK90 => CLK90,
00470 CAL_CLK => CAL_CLK,
00471 RESET => RESET90,
00472 DATA_DLYINC => data_idelay_inc(0),
00473 DATA_DLYCE => data_idelay_ce(0),
00474 DATA_DLYRST => data_idelay_rst(0),
00475 WRITE_DATA_RISE => wr_data_rise(11),
00476 WRITE_DATA_Fall => wr_data_fall(11),
00477 CTRL_WREN => wr_en,
00478 DDR_DQ => DDR_DQ(11),
00479 READ_DATA_RISE => rd_data_rise(11),
00480 READ_DATA_Fall => rd_data_fall(11)
00481 );
00482
00483
00484
00485 v4_dq_iob_12 : mem_interface_top_v4_dq_iob port map
00486 (
00487 CLK => CLK,
00488 CLK90 => CLK90,
00489 CAL_CLK => CAL_CLK,
00490 RESET => RESET90,
00491 DATA_DLYINC => data_idelay_inc(0),
00492 DATA_DLYCE => data_idelay_ce(0),
00493 DATA_DLYRST => data_idelay_rst(0),
00494 WRITE_DATA_RISE => wr_data_rise(12),
00495 WRITE_DATA_Fall => wr_data_fall(12),
00496 CTRL_WREN => wr_en,
00497 DDR_DQ => DDR_DQ(12),
00498 READ_DATA_RISE => rd_data_rise(12),
00499 READ_DATA_Fall => rd_data_fall(12)
00500 );
00501
00502
00503
00504 v4_dq_iob_13 : mem_interface_top_v4_dq_iob port map
00505 (
00506 CLK => CLK,
00507 CLK90 => CLK90,
00508 CAL_CLK => CAL_CLK,
00509 RESET => RESET90,
00510 DATA_DLYINC => data_idelay_inc(0),
00511 DATA_DLYCE => data_idelay_ce(0),
00512 DATA_DLYRST => data_idelay_rst(0),
00513 WRITE_DATA_RISE => wr_data_rise(13),
00514 WRITE_DATA_Fall => wr_data_fall(13),
00515 CTRL_WREN => wr_en,
00516 DDR_DQ => DDR_DQ(13),
00517 READ_DATA_RISE => rd_data_rise(13),
00518 READ_DATA_Fall => rd_data_fall(13)
00519 );
00520
00521
00522
00523 v4_dq_iob_14 : mem_interface_top_v4_dq_iob port map
00524 (
00525 CLK => CLK,
00526 CLK90 => CLK90,
00527 CAL_CLK => CAL_CLK,
00528 RESET => RESET90,
00529 DATA_DLYINC => data_idelay_inc(0),
00530 DATA_DLYCE => data_idelay_ce(0),
00531 DATA_DLYRST => data_idelay_rst(0),
00532 WRITE_DATA_RISE => wr_data_rise(14),
00533 WRITE_DATA_Fall => wr_data_fall(14),
00534 CTRL_WREN => wr_en,
00535 DDR_DQ => DDR_DQ(14),
00536 READ_DATA_RISE => rd_data_rise(14),
00537 READ_DATA_Fall => rd_data_fall(14)
00538 );
00539
00540
00541
00542 v4_dq_iob_15 : mem_interface_top_v4_dq_iob port map
00543 (
00544 CLK => CLK,
00545 CLK90 => CLK90,
00546 CAL_CLK => CAL_CLK,
00547 RESET => RESET90,
00548 DATA_DLYINC => data_idelay_inc(0),
00549 DATA_DLYCE => data_idelay_ce(0),
00550 DATA_DLYRST => data_idelay_rst(0),
00551 WRITE_DATA_RISE => wr_data_rise(15),
00552 WRITE_DATA_Fall => wr_data_fall(15),
00553 CTRL_WREN => wr_en,
00554 DDR_DQ => DDR_DQ(15),
00555 READ_DATA_RISE => rd_data_rise(15),
00556 READ_DATA_Fall => rd_data_fall(15)
00557 );
00558
00559
00560
00561 v4_dq_iob_16 : mem_interface_top_v4_dq_iob port map
00562 (
00563 CLK => CLK,
00564 CLK90 => CLK90,
00565 CAL_CLK => CAL_CLK,
00566 RESET => RESET90,
00567 DATA_DLYINC => data_idelay_inc(0),
00568 DATA_DLYCE => data_idelay_ce(0),
00569 DATA_DLYRST => data_idelay_rst(0),
00570 WRITE_DATA_RISE => wr_data_rise(16),
00571 WRITE_DATA_Fall => wr_data_fall(16),
00572 CTRL_WREN => wr_en,
00573 DDR_DQ => DDR_DQ(16),
00574 READ_DATA_RISE => rd_data_rise(16),
00575 READ_DATA_Fall => rd_data_fall(16)
00576 );
00577
00578
00579
00580 v4_dq_iob_17 : mem_interface_top_v4_dq_iob port map
00581 (
00582 CLK => CLK,
00583 CLK90 => CLK90,
00584 CAL_CLK => CAL_CLK,
00585 RESET => RESET90,
00586 DATA_DLYINC => data_idelay_inc(0),
00587 DATA_DLYCE => data_idelay_ce(0),
00588 DATA_DLYRST => data_idelay_rst(0),
00589 WRITE_DATA_RISE => wr_data_rise(17),
00590 WRITE_DATA_Fall => wr_data_fall(17),
00591 CTRL_WREN => wr_en,
00592 DDR_DQ => DDR_DQ(17),
00593 READ_DATA_RISE => rd_data_rise(17),
00594 READ_DATA_Fall => rd_data_fall(17)
00595 );
00596
00597
00598
00599 v4_dq_iob_18 : mem_interface_top_v4_dq_iob port map
00600 (
00601 CLK => CLK,
00602 CLK90 => CLK90,
00603 CAL_CLK => CAL_CLK,
00604 RESET => RESET90,
00605 DATA_DLYINC => data_idelay_inc(0),
00606 DATA_DLYCE => data_idelay_ce(0),
00607 DATA_DLYRST => data_idelay_rst(0),
00608 WRITE_DATA_RISE => wr_data_rise(18),
00609 WRITE_DATA_Fall => wr_data_fall(18),
00610 CTRL_WREN => wr_en,
00611 DDR_DQ => DDR_DQ(18),
00612 READ_DATA_RISE => rd_data_rise(18),
00613 READ_DATA_Fall => rd_data_fall(18)
00614 );
00615
00616
00617
00618 v4_dq_iob_19 : mem_interface_top_v4_dq_iob port map
00619 (
00620 CLK => CLK,
00621 CLK90 => CLK90,
00622 CAL_CLK => CAL_CLK,
00623 RESET => RESET90,
00624 DATA_DLYINC => data_idelay_inc(0),
00625 DATA_DLYCE => data_idelay_ce(0),
00626 DATA_DLYRST => data_idelay_rst(0),
00627 WRITE_DATA_RISE => wr_data_rise(19),
00628 WRITE_DATA_Fall => wr_data_fall(19),
00629 CTRL_WREN => wr_en,
00630 DDR_DQ => DDR_DQ(19),
00631 READ_DATA_RISE => rd_data_rise(19),
00632 READ_DATA_Fall => rd_data_fall(19)
00633 );
00634
00635
00636
00637 v4_dq_iob_20 : mem_interface_top_v4_dq_iob port map
00638 (
00639 CLK => CLK,
00640 CLK90 => CLK90,
00641 CAL_CLK => CAL_CLK,
00642 RESET => RESET90,
00643 DATA_DLYINC => data_idelay_inc(0),
00644 DATA_DLYCE => data_idelay_ce(0),
00645 DATA_DLYRST => data_idelay_rst(0),
00646 WRITE_DATA_RISE => wr_data_rise(20),
00647 WRITE_DATA_Fall => wr_data_fall(20),
00648 CTRL_WREN => wr_en,
00649 DDR_DQ => DDR_DQ(20),
00650 READ_DATA_RISE => rd_data_rise(20),
00651 READ_DATA_Fall => rd_data_fall(20)
00652 );
00653
00654
00655
00656 v4_dq_iob_21 : mem_interface_top_v4_dq_iob port map
00657 (
00658 CLK => CLK,
00659 CLK90 => CLK90,
00660 CAL_CLK => CAL_CLK,
00661 RESET => RESET90,
00662 DATA_DLYINC => data_idelay_inc(0),
00663 DATA_DLYCE => data_idelay_ce(0),
00664 DATA_DLYRST => data_idelay_rst(0),
00665 WRITE_DATA_RISE => wr_data_rise(21),
00666 WRITE_DATA_Fall => wr_data_fall(21),
00667 CTRL_WREN => wr_en,
00668 DDR_DQ => DDR_DQ(21),
00669 READ_DATA_RISE => rd_data_rise(21),
00670 READ_DATA_Fall => rd_data_fall(21)
00671 );
00672
00673
00674
00675 v4_dq_iob_22 : mem_interface_top_v4_dq_iob port map
00676 (
00677 CLK => CLK,
00678 CLK90 => CLK90,
00679 CAL_CLK => CAL_CLK,
00680 RESET => RESET90,
00681 DATA_DLYINC => data_idelay_inc(0),
00682 DATA_DLYCE => data_idelay_ce(0),
00683 DATA_DLYRST => data_idelay_rst(0),
00684 WRITE_DATA_RISE => wr_data_rise(22),
00685 WRITE_DATA_Fall => wr_data_fall(22),
00686 CTRL_WREN => wr_en,
00687 DDR_DQ => DDR_DQ(22),
00688 READ_DATA_RISE => rd_data_rise(22),
00689 READ_DATA_Fall => rd_data_fall(22)
00690 );
00691
00692
00693
00694 v4_dq_iob_23 : mem_interface_top_v4_dq_iob port map
00695 (
00696 CLK => CLK,
00697 CLK90 => CLK90,
00698 CAL_CLK => CAL_CLK,
00699 RESET => RESET90,
00700 DATA_DLYINC => data_idelay_inc(0),
00701 DATA_DLYCE => data_idelay_ce(0),
00702 DATA_DLYRST => data_idelay_rst(0),
00703 WRITE_DATA_RISE => wr_data_rise(23),
00704 WRITE_DATA_Fall => wr_data_fall(23),
00705 CTRL_WREN => wr_en,
00706 DDR_DQ => DDR_DQ(23),
00707 READ_DATA_RISE => rd_data_rise(23),
00708 READ_DATA_Fall => rd_data_fall(23)
00709 );
00710
00711
00712
00713 v4_dq_iob_24 : mem_interface_top_v4_dq_iob port map
00714 (
00715 CLK => CLK,
00716 CLK90 => CLK90,
00717 CAL_CLK => CAL_CLK,
00718 RESET => RESET90,
00719 DATA_DLYINC => data_idelay_inc(0),
00720 DATA_DLYCE => data_idelay_ce(0),
00721 DATA_DLYRST => data_idelay_rst(0),
00722 WRITE_DATA_RISE => wr_data_rise(24),
00723 WRITE_DATA_Fall => wr_data_fall(24),
00724 CTRL_WREN => wr_en,
00725 DDR_DQ => DDR_DQ(24),
00726 READ_DATA_RISE => rd_data_rise(24),
00727 READ_DATA_Fall => rd_data_fall(24)
00728 );
00729
00730
00731
00732 v4_dq_iob_25 : mem_interface_top_v4_dq_iob port map
00733 (
00734 CLK => CLK,
00735 CLK90 => CLK90,
00736 CAL_CLK => CAL_CLK,
00737 RESET => RESET90,
00738 DATA_DLYINC => data_idelay_inc(0),
00739 DATA_DLYCE => data_idelay_ce(0),
00740 DATA_DLYRST => data_idelay_rst(0),
00741 WRITE_DATA_RISE => wr_data_rise(25),
00742 WRITE_DATA_Fall => wr_data_fall(25),
00743 CTRL_WREN => wr_en,
00744 DDR_DQ => DDR_DQ(25),
00745 READ_DATA_RISE => rd_data_rise(25),
00746 READ_DATA_Fall => rd_data_fall(25)
00747 );
00748
00749
00750
00751 v4_dq_iob_26 : mem_interface_top_v4_dq_iob port map
00752 (
00753 CLK => CLK,
00754 CLK90 => CLK90,
00755 CAL_CLK => CAL_CLK,
00756 RESET => RESET90,
00757 DATA_DLYINC => data_idelay_inc(0),
00758 DATA_DLYCE => data_idelay_ce(0),
00759 DATA_DLYRST => data_idelay_rst(0),
00760 WRITE_DATA_RISE => wr_data_rise(26),
00761 WRITE_DATA_Fall => wr_data_fall(26),
00762 CTRL_WREN => wr_en,
00763 DDR_DQ => DDR_DQ(26),
00764 READ_DATA_RISE => rd_data_rise(26),
00765 READ_DATA_Fall => rd_data_fall(26)
00766 );
00767
00768
00769
00770 v4_dq_iob_27 : mem_interface_top_v4_dq_iob port map
00771 (
00772 CLK => CLK,
00773 CLK90 => CLK90,
00774 CAL_CLK => CAL_CLK,
00775 RESET => RESET90,
00776 DATA_DLYINC => data_idelay_inc(0),
00777 DATA_DLYCE => data_idelay_ce(0),
00778 DATA_DLYRST => data_idelay_rst(0),
00779 WRITE_DATA_RISE => wr_data_rise(27),
00780 WRITE_DATA_Fall => wr_data_fall(27),
00781 CTRL_WREN => wr_en,
00782 DDR_DQ => DDR_DQ(27),
00783 READ_DATA_RISE => rd_data_rise(27),
00784 READ_DATA_Fall => rd_data_fall(27)
00785 );
00786
00787
00788
00789 v4_dq_iob_28 : mem_interface_top_v4_dq_iob port map
00790 (
00791 CLK => CLK,
00792 CLK90 => CLK90,
00793 CAL_CLK => CAL_CLK,
00794 RESET => RESET90,
00795 DATA_DLYINC => data_idelay_inc(0),
00796 DATA_DLYCE => data_idelay_ce(0),
00797 DATA_DLYRST => data_idelay_rst(0),
00798 WRITE_DATA_RISE => wr_data_rise(28),
00799 WRITE_DATA_Fall => wr_data_fall(28),
00800 CTRL_WREN => wr_en,
00801 DDR_DQ => DDR_DQ(28),
00802 READ_DATA_RISE => rd_data_rise(28),
00803 READ_DATA_Fall => rd_data_fall(28)
00804 );
00805
00806
00807
00808 v4_dq_iob_29 : mem_interface_top_v4_dq_iob port map
00809 (
00810 CLK => CLK,
00811 CLK90 => CLK90,
00812 CAL_CLK => CAL_CLK,
00813 RESET => RESET90,
00814 DATA_DLYINC => data_idelay_inc(0),
00815 DATA_DLYCE => data_idelay_ce(0),
00816 DATA_DLYRST => data_idelay_rst(0),
00817 WRITE_DATA_RISE => wr_data_rise(29),
00818 WRITE_DATA_Fall => wr_data_fall(29),
00819 CTRL_WREN => wr_en,
00820 DDR_DQ => DDR_DQ(29),
00821 READ_DATA_RISE => rd_data_rise(29),
00822 READ_DATA_Fall => rd_data_fall(29)
00823 );
00824
00825
00826
00827 v4_dq_iob_30 : mem_interface_top_v4_dq_iob port map
00828 (
00829 CLK => CLK,
00830 CLK90 => CLK90,
00831 CAL_CLK => CAL_CLK,
00832 RESET => RESET90,
00833 DATA_DLYINC => data_idelay_inc(0),
00834 DATA_DLYCE => data_idelay_ce(0),
00835 DATA_DLYRST => data_idelay_rst(0),
00836 WRITE_DATA_RISE => wr_data_rise(30),
00837 WRITE_DATA_Fall => wr_data_fall(30),
00838 CTRL_WREN => wr_en,
00839 DDR_DQ => DDR_DQ(30),
00840 READ_DATA_RISE => rd_data_rise(30),
00841 READ_DATA_Fall => rd_data_fall(30)
00842 );
00843
00844
00845
00846 v4_dq_iob_31 : mem_interface_top_v4_dq_iob port map
00847 (
00848 CLK => CLK,
00849 CLK90 => CLK90,
00850 CAL_CLK => CAL_CLK,
00851 RESET => RESET90,
00852 DATA_DLYINC => data_idelay_inc(0),
00853 DATA_DLYCE => data_idelay_ce(0),
00854 DATA_DLYRST => data_idelay_rst(0),
00855 WRITE_DATA_RISE => wr_data_rise(31),
00856 WRITE_DATA_Fall => wr_data_fall(31),
00857 CTRL_WREN => wr_en,
00858 DDR_DQ => DDR_DQ(31),
00859 READ_DATA_RISE => rd_data_rise(31),
00860 READ_DATA_Fall => rd_data_fall(31)
00861 );
00862
00863
00864
00865
00866 end arch;