BCM-AAA: daqrio_top.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/daqrio_top.vhd,v $
00015 --*  $Revision: 1.16.2.5 $                                         *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:47 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 
00025 library ieee;
00026 
00027 use ieee.std_logic_1164.all;
00028 
00029 use ieee.std_logic_arith.all;
00030 
00031 use ieee.std_logic_unsigned.all;
00032 library WORK;
00033 use work.daq_header.all;
00034 
00035 
00036 
00037 
00038 entity daqrio_top is
00039   generic
00040     (
00041       PATTERN : std_logic_vector(31 downto 0) := "11110000111100001111000011110000"
00042       );
00043   port
00044     (
00045       SET_SHIFT          : in  std_logic_vector(7 downto 0);
00046       CALIB              : in  std_logic;
00047       CAL1               : in  std_logic;
00048       CAL2               : in  std_logic;
00049       CHECK_1            : out std_logic;
00050       CHECK_2            : out std_logic;
00051       RES                : in  std_logic;
00052       REF                : in  std_logic;
00053       PAR                : in  std_logic;
00054       BC                 : in  std_logic;
00055       EN                 : in  std_logic;
00056       COARSE_TIME_1      : in  std_logic_vector(7 downto 0);
00057       COARSE_TIME_2      : in  std_logic_vector(7 downto 0);
00058       ADJUST_TIME_1      : in  integer range 0 to 32 := 0;
00059       ADJUST_TIME_2      : in  integer range 0 to 32 := 0;
00060       ADJUST_TIME_12     : in  integer range 0 to 32 := 0;
00061       ADJUST_TIME_22     : in  integer range 0 to 32 := 0;
00062       TX_SYSTEM_RESET_IN : in  std_logic;
00063       RX_SYSTEM_RESET_IN : in  std_logic;
00064       MGT0_RXLOCK_OUT    : out std_logic;
00065       MGT0_TXLOCK_OUT    : out std_logic;
00066       MGT1_RXLOCK_OUT    : out std_logic;
00067       MGT1_TXLOCK_OUT    : out std_logic;
00068       RX1N_IN            : in  std_logic_vector(1 downto 0);
00069       RX1P_IN            : in  std_logic_vector(1 downto 0);
00070       TX1N_OUT           : out std_logic_vector(1 downto 0);
00071       TX1P_OUT           : out std_logic_vector(1 downto 0);
00072       RX_READY_FLAG      : out std_logic;
00073       TX_READY_FLAG      : out std_logic;
00074       PULSE_OUT_P        : out std_logic;
00075       SUM_RIS_1          : out std_logic_vector (7 downto 0);
00076       SUM_FAL_1          : out std_logic_vector (7 downto 0);
00077       T1_1               : out std_logic_vector (7 downto 0);
00078       T2_1               : out std_logic_vector (7 downto 0);
00079       T3_1               : out std_logic_vector (7 downto 0);
00080       W1_1               : out std_logic_vector (7 downto 0);
00081       W2_1               : out std_logic_vector (7 downto 0);
00082       W3_1               : out std_logic_vector (7 downto 0);
00083       STATUS_T1_1        : out std_logic;
00084       STATUS_T2_1        : out std_logic;
00085       STATUS_T3_1        : out std_logic;
00086       STATUS_W1_1        : out std_logic;
00087       STATUS_W2_1        : out std_logic;
00088       STATUS_W3_1        : out std_logic;
00089       OVERFLOW_1         : out std_logic;
00090       SUM_RIS_2          : out std_logic_vector (7 downto 0);
00091       SUM_FAL_2          : out std_logic_vector (7 downto 0);
00092       T1_2               : out std_logic_vector (7 downto 0);
00093       T2_2               : out std_logic_vector (7 downto 0);
00094       T3_2               : out std_logic_vector (7 downto 0);
00095       W1_2               : out std_logic_vector (7 downto 0);
00096       W2_2               : out std_logic_vector (7 downto 0);
00097       W3_2               : out std_logic_vector (7 downto 0);
00098       STATUS_T1_2        : out std_logic;
00099       STATUS_T2_2        : out std_logic;
00100       STATUS_T3_2        : out std_logic;
00101       STATUS_W1_2        : out std_logic;
00102       STATUS_W2_2        : out std_logic;
00103       STATUS_W3_2        : out std_logic;
00104       OVERFLOW_2         : out std_logic;
00105       MASK_1             : out std_logic;
00106       MASK_2             : out std_logic;
00107       CALIB_DONE         : out std_logic;
00108       RAW_DATA1          : out std_logic_vector(31 downto 0);
00109       RAW_DATA2          : out std_logic_vector(31 downto 0)
00110       );
00111 
00112 end daqrio_top;
00113 
00114 
00115 architecture daqrio_top_arc of daqrio_top is
00116 
00117 -------------------------------- signals -----------------------------------
00118   signal ref_i          : std_logic                     := '0';
00119   signal par_i          : std_logic                     := '0';
00120   signal bclk2x_i       : std_logic                     := '0';
00121   signal bc_i           : std_logic                     := '0';
00122   signal STATUS_P1_i    : std_logic                     := '0';
00123   signal STATUS_P2_i    : std_logic                     := '0';
00124   signal STATUS_P3_i    : std_logic                     := '0';
00125   signal STATUS_N1_i    : std_logic                     := '0';
00126   signal STATUS_N2_i    : std_logic                     := '0';
00127   signal STATUS_N3_i    : std_logic                     := '0';
00128   signal S_P1_i         : std_logic                     := '0';
00129   signal S_P2_i         : std_logic                     := '0';
00130   signal S_P3_i         : std_logic                     := '0';
00131   signal S_N1_i         : std_logic                     := '0';
00132   signal S_N2_i         : std_logic                     := '0';
00133   signal S_N3_i         : std_logic                     := '0';
00134   signal STATUS_P1_e    : std_logic                     := '0';
00135   signal STATUS_P2_e    : std_logic                     := '0';
00136   signal STATUS_P3_e    : std_logic                     := '0';
00137   signal STATUS_N1_e    : std_logic                     := '0';
00138   signal STATUS_N2_e    : std_logic                     := '0';
00139   signal STATUS_N3_e    : std_logic                     := '0';
00140   signal S_P1_e         : std_logic                     := '0';
00141   signal S_P2_e         : std_logic                     := '0';
00142   signal S_P3_e         : std_logic                     := '0';
00143   signal S_N1_e         : std_logic                     := '0';
00144   signal S_N2_e         : std_logic                     := '0';
00145   signal S_N3_e         : std_logic                     := '0';
00146   signal tg             : std_logic_vector(1 downto 0)  := "00";
00147   signal data_irena     : std_logic_vector(31 downto 0) := (others => '0');
00148   signal data_irena_i   : std_logic_vector(31 downto 0) := (others => '0');
00149   signal data_irena_ii  : std_logic_vector(31 downto 0) := (others => '0');
00150   signal data_irena_id  : std_logic_vector(31 downto 0) := (others => '0');
00151   signal data_irena_idd : std_logic_vector(31 downto 0) := (others => '0');
00152   signal SUM_RIS_i      : std_logic_vector(5 downto 0)  := (others => '0');
00153   signal SUM_FAL_i      : std_logic_vector(5 downto 0)  := (others => '0');
00154   signal SUM_R_i        : std_logic_vector(7 downto 0)  := (others => '0');
00155   signal SUM_F_i        : std_logic_vector(7 downto 0)  := (others => '0');
00156   signal EDGE_RIS1_i    : std_logic_vector(4 downto 0)  := (others => '0');
00157   signal EDGE_RIS2_i    : std_logic_vector(4 downto 0)  := (others => '0');
00158   signal EDGE_RIS3_i    : std_logic_vector(4 downto 0)  := (others => '0');
00159   signal EDGE_FAL1_i    : std_logic_vector(4 downto 0)  := (others => '0');
00160   signal EDGE_FAL2_i    : std_logic_vector(4 downto 0)  := (others => '0');
00161   signal EDGE_FAL3_i    : std_logic_vector(4 downto 0)  := (others => '0');
00162   signal RIS1_i         : std_logic_vector(5 downto 0)  := (others => '0');
00163   signal RIS2_i         : std_logic_vector(5 downto 0)  := (others => '0');
00164   signal RIS3_i         : std_logic_vector(5 downto 0)  := (others => '0');
00165   signal FAL1_i         : std_logic_vector(5 downto 0)  := (others => '0');
00166   signal FAL2_i         : std_logic_vector(5 downto 0)  := (others => '0');
00167   signal FAL3_i         : std_logic_vector(5 downto 0)  := (others => '0');
00168   signal data_ewa       : std_logic_vector(31 downto 0) := (others => '0');
00169   signal data_ewa_i     : std_logic_vector(31 downto 0) := (others => '0');
00170   signal data_ewa_ii    : std_logic_vector(31 downto 0) := (others => '0');
00171   signal data_ewa_id    : std_logic_vector(31 downto 0) := (others => '0');
00172   signal data_ewa_idd   : std_logic_vector(31 downto 0) := (others => '0');
00173   signal SUM_RIS_e      : std_logic_vector(5 downto 0)  := (others => '0');
00174   signal SUM_FAL_e      : std_logic_vector(5 downto 0)  := (others => '0');
00175   signal SUM_R_e        : std_logic_vector(7 downto 0)  := (others => '0');
00176   signal SUM_F_e        : std_logic_vector(7 downto 0)  := (others => '0');
00177   signal EDGE_RIS1_e    : std_logic_vector(4 downto 0)  := (others => '0');
00178   signal EDGE_RIS2_e    : std_logic_vector(4 downto 0)  := (others => '0');
00179   signal EDGE_RIS3_e    : std_logic_vector(4 downto 0)  := (others => '0');
00180   signal EDGE_FAL1_e    : std_logic_vector(4 downto 0)  := (others => '0');
00181   signal EDGE_FAL2_e    : std_logic_vector(4 downto 0)  := (others => '0');
00182   signal EDGE_FAL3_e    : std_logic_vector(4 downto 0)  := (others => '0');
00183   signal RIS1_e         : std_logic_vector(5 downto 0)  := (others => '0');
00184   signal RIS2_e         : std_logic_vector(5 downto 0)  := (others => '0');
00185   signal RIS3_e         : std_logic_vector(5 downto 0)  := (others => '0');
00186   signal FAL1_e         : std_logic_vector(5 downto 0)  := (others => '0');
00187   signal FAL2_e         : std_logic_vector(5 downto 0)  := (others => '0');
00188   signal FAL3_e         : std_logic_vector(5 downto 0)  := (others => '0');
00189 
00190 ------------------------------ components ----------------------------------
00191 
00192 
00193   component rio_rxtx
00194     generic
00195       (
00196         USE_CHIPSCOPE : integer;
00197         BOARD         : string;
00198         SIMULATION_P  : integer;
00199         XOR_PATTERN   : std_logic_vector(31 downto 0)
00200         );
00201     port
00202       (
00203         SET_SHIFT          : in  std_logic_vector(7 downto 0);
00204         CALIB              : in  std_logic;
00205         CAL1               : in  std_logic;
00206         CAL2               : in  std_logic;
00207         CHECK_OUT_1        : out std_logic;
00208         CHECK_OUT_2        : out std_logic;
00209         REFCLK             : in  std_logic;
00210         PARCLK             : in  std_logic;
00211         TX_SYSTEM_RESET_IN : in  std_logic;
00212         RX_SYSTEM_RESET_IN : in  std_logic;
00213         MGT0_RXLOCK_OUT    : out std_logic;
00214         MGT0_TXLOCK_OUT    : out std_logic;
00215         MGT1_RXLOCK_OUT    : out std_logic;
00216         MGT1_TXLOCK_OUT    : out std_logic;
00217         RX1N_IN_1          : in  std_logic;
00218         RX1P_IN_1          : in  std_logic;
00219         RX1N_IN_2          : in  std_logic;
00220         RX1P_IN_2          : in  std_logic;
00221         TX1N_OUT_1         : out std_logic;
00222         TX1P_OUT_1         : out std_logic;
00223         TX1N_OUT_2         : out std_logic;
00224         TX1P_OUT_2         : out std_logic;
00225         RXRECCLK1_OUT      : out std_logic;
00226         RX_READY_FLAG      : out std_logic;
00227         TX_READY_FLAG      : out std_logic;
00228         BC_2X              : out std_logic;
00229         RX_DATA_OUT_1      : out std_logic_vector(31 downto 0);
00230         RX_DATA_OUT_2      : out std_logic_vector(31 downto 0);
00231         MASK1              : out std_logic;
00232         MASK2              : out std_logic;
00233         VALID              : out std_logic
00234         );
00235   end component;
00236 
00237 
00238   component edge_det
00239     port
00240       (
00241         DATA_IN   : in  std_logic_vector (31 downto 0);
00242         CLK       : in  std_logic;
00243         SUM_RIS   : out std_logic_vector (5 downto 0);
00244         SUM_FAL   : out std_logic_vector (5 downto 0);
00245         EDGE_RIS1 : out std_logic_vector (4 downto 0);
00246         EDGE_RIS2 : out std_logic_vector (4 downto 0);
00247         EDGE_RIS3 : out std_logic_vector (4 downto 0);
00248         EDGE_FAL1 : out std_logic_vector (4 downto 0);
00249         EDGE_FAL2 : out std_logic_vector (4 downto 0);
00250         EDGE_FAL3 : out std_logic_vector (4 downto 0);
00251         STATUS_P1 : out std_logic;
00252         STATUS_P2 : out std_logic;
00253         STATUS_P3 : out std_logic;
00254         STATUS_N1 : out std_logic;
00255         STATUS_N2 : out std_logic;
00256         STATUS_N3 : out std_logic
00257         );
00258   end component;
00259 
00260 
00261   component delay_adj
00262     port
00263       (
00264         CLK        : in  std_logic;
00265         A          : in  std_logic_vector(31 downto 0);
00266         B          : in  std_logic_vector(31 downto 0);
00267         X          : out std_logic_vector(31 downto 0);
00268         Y          : out std_logic_vector(31 downto 0);
00269         ADJ_TIME_1 : in  integer range 0 to 32 := 0;
00270         ADJ_TIME_2 : in  integer range 0 to 32 := 0
00271         );
00272   end component;
00273 
00274 
00275   component bcm_signal_delay_vec
00276     port
00277       (
00278         CLK           : in  std_logic;
00279         SCLR          : in  std_logic;
00280         delay_setting : in  std_logic_vector(7 downto 0);
00281         data_input    : in  std_logic_vector(31 downto 0);
00282         data_output   : out std_logic_vector(31 downto 0)
00283         );
00284   end component;
00285 
00286 
00287   component bunchcycle
00288     port
00289       (
00290         CLK2X      : in  std_logic;
00291         CLK        : in  std_logic;
00292         RESET      : in  std_logic;
00293         EN         : in  std_logic;
00294         R1         : in  std_logic_vector(4 downto 0);
00295         R2         : in  std_logic_vector(4 downto 0);
00296         R3         : in  std_logic_vector(4 downto 0);
00297         F1         : in  std_logic_vector(4 downto 0);
00298         F2         : in  std_logic_vector(4 downto 0);
00299         F3         : in  std_logic_vector(4 downto 0);
00300         SR1        : in  std_logic;
00301         SR2        : in  std_logic;
00302         SR3        : in  std_logic;
00303         SF1        : in  std_logic;
00304         SF2        : in  std_logic;
00305         SF3        : in  std_logic;
00306         SUM_R_IN   : in  std_logic_vector(5 downto 0);
00307         SUM_F_IN   : in  std_logic_vector(5 downto 0);
00308         EDGE_RIS1  : out std_logic_vector(5 downto 0);
00309         EDGE_RIS2  : out std_logic_vector(5 downto 0);
00310         EDGE_RIS3  : out std_logic_vector(5 downto 0);
00311         EDGE_FAL1  : out std_logic_vector(5 downto 0);
00312         EDGE_FAL2  : out std_logic_vector(5 downto 0);
00313         EDGE_FAL3  : out std_logic_vector(5 downto 0);
00314         STATUS_ER1 : out std_logic;
00315         STATUS_ER2 : out std_logic;
00316         STATUS_ER3 : out std_logic;
00317         STATUS_EF1 : out std_logic;
00318         STATUS_EF2 : out std_logic;
00319         STATUS_EF3 : out std_logic;
00320         SUM_R_OUT  : out std_logic_vector(7 downto 0);
00321         SUM_F_OUT  : out std_logic_vector(7 downto 0)
00322         );
00323   end component;
00324 
00325 
00326   component cal
00327     generic
00328       (
00329         ADJUST : integer := 0
00330         );
00331     port
00332       (
00333         CLK      : in  std_logic;
00334         STAT_R1  : in  std_logic;
00335         STAT_R2  : in  std_logic;
00336         STAT_R3  : in  std_logic;
00337         STAT_F1  : in  std_logic;
00338         STAT_F2  : in  std_logic;
00339         STAT_F3  : in  std_logic;
00340         RIS1     : in  std_logic_vector(5 downto 0);
00341         RIS2     : in  std_logic_vector(5 downto 0);
00342         RIS3     : in  std_logic_vector(5 downto 0);
00343         FAL1     : in  std_logic_vector(5 downto 0);
00344         FAL2     : in  std_logic_vector(5 downto 0);
00345         FAL3     : in  std_logic_vector(5 downto 0);
00346         S_T1     : out std_logic;
00347         S_T2     : out std_logic;
00348         S_T3     : out std_logic;
00349         S_W1     : out std_logic;
00350         S_W2     : out std_logic;
00351         S_W3     : out std_logic;
00352         TIME1    : out std_logic_vector(7 downto 0);
00353         TIME2    : out std_logic_vector(7 downto 0);
00354         TIME3    : out std_logic_vector(7 downto 0);
00355         WIDTH1   : out std_logic_vector(7 downto 0);
00356         WIDTH2   : out std_logic_vector(7 downto 0);
00357         WIDTH3   : out std_logic_vector(7 downto 0);
00358         SUM_RIN  : in  std_logic_vector (7 downto 0);
00359         SUM_FIN  : in  std_logic_vector (7 downto 0);
00360         SUM_ROUT : out std_logic_vector (7 downto 0);
00361         SUM_FOUT : out std_logic_vector (7 downto 0);
00362         OVER     : out std_logic
00363         );
00364   end component;
00365 
00366 --*************************************************************************
00367 --                                main code
00368 --*************************************************************************
00369 
00370 begin
00371 
00372   PULSE_OUT_P <= '0';
00373   RAW_DATA1   <= data_irena_id;
00374   RAW_DATA2   <= data_ewa_id;
00375   ref_i       <= REF;
00376   par_i       <= PAR;
00377   bc_i        <= BC;
00378 
00379 
00380   rios2 : rio_rxtx
00381     generic map
00382     (
00383       USE_CHIPSCOPE => 0,       -- Set to 1 to use Chipscope to drive resets
00384       SIMULATION_P  => 0,       -- Set to 1 when using module in simulation
00385       BOARD         => "BIG",
00386       XOR_PATTERN   => PATTERN           -- tx big endian
00387       )
00388     port map
00389     (
00390       SET_SHIFT          => SET_SHIFT,
00391       CALIB              => CALIB,
00392       CAL1               => CAL1,
00393       CAL2               => CAL2,
00394       CHECK_OUT_1        => CHECK_1,
00395       CHECK_OUT_2        => CHECK_2,
00396       REFCLK             => REF_i,
00397       PARCLK             => PAR_i,
00398       TX_SYSTEM_RESET_IN => RES,
00399       RX_SYSTEM_RESET_IN => RES,
00400       MGT0_RXLOCK_OUT    => MGT0_RXLOCK_OUT,
00401       MGT0_TXLOCK_OUT    => MGT0_TXLOCK_OUT,
00402       MGT1_RXLOCK_OUT    => MGT1_RXLOCK_OUT,
00403       MGT1_TXLOCK_OUT    => MGT1_TXLOCK_OUT,
00404       RX1N_IN_1          => RX1N_IN(0),
00405       RX1P_IN_1          => RX1P_IN(0),
00406       RX1N_IN_2          => RX1N_IN(1),
00407       RX1P_IN_2          => RX1P_IN(1),
00408       TX1N_OUT_1         => TX1N_OUT(0),
00409       TX1P_OUT_1         => TX1P_OUT(0),
00410       TX1N_OUT_2         => TX1N_OUT(1),
00411       TX1P_OUT_2         => TX1P_OUT(1),
00412       RXRECCLK1_OUT      => open,
00413       RX_READY_FLAG      => RX_READY_FLAG,
00414       TX_READY_FLAG      => TX_READY_FLAG,
00415       BC_2X              => bclk2x_i,
00416       RX_DATA_OUT_1      => data_irena,
00417       RX_DATA_OUT_2      => data_ewa,
00418       MASK1              => MASK_1,
00419       MASK2              => MASK_2,
00420       VALID              => CALIB_DONE
00421       );
00422 
00423 
00424   cable_compensation1 : delay_adj
00425     port map
00426     (
00427       CLK         => bclk2x_i,
00428       A           => data_irena,
00429       B           => data_ewa,
00430       X           => data_irena_ii,
00431       Y           => data_ewa_ii,
00432       ADJ_TIME_1 => ADJUST_TIME_1,
00433       ADJ_TIME_2 => ADJUST_TIME_2
00434       );
00435 
00436 
00437   cable_compensation2 : delay_adj
00438     port map
00439     (
00440       CLK         => bclk2x_i,
00441       A           => data_irena_ii,
00442       B           => data_ewa_ii,
00443       X          => data_irena_i,
00444       Y          => data_ewa_i,
00445       ADJ_TIME_1 => ADJUST_TIME_12 ,
00446       ADJ_TIME_2 => ADJUST_TIME_22
00447       );
00448 
00449 
00450   coarse_delay_ch11 : bcm_signal_delay_vec
00451     port map
00452     (
00453       CLK           => bclk2x_i,
00454       SCLR          => RES,
00455       delay_setting => COARSE_TIME_1,
00456       data_input    => data_irena_i,
00457       data_output   => data_irena_idd
00458       );
00459 
00460 
00461   coarse_delay_ch21 : bcm_signal_delay_vec
00462     port map
00463     (
00464       CLK           => bclk2x_i,
00465       SCLR          => RES,
00466       delay_setting => COARSE_TIME_2,
00467       data_input    => data_ewa_i,
00468       data_output   => data_ewa_idd
00469       );
00470 
00471 
00472   coarse_delay_ch12 : bcm_signal_delay_vec
00473     port map
00474     (
00475       CLK           => bclk2x_i,
00476       SCLR          => RES,
00477       delay_setting => COARSE_TIME_1,
00478       data_input    => data_irena_idd,
00479       data_output   => data_irena_id
00480       );
00481 
00482 
00483   coarse_delay_ch22 : bcm_signal_delay_vec
00484     port map
00485     (
00486       CLK           => bclk2x_i,
00487       SCLR          => RES,
00488       delay_setting => COARSE_TIME_2,
00489       data_input    => data_ewa_idd,
00490       data_output   => data_ewa_id
00491       );
00492 
00493 
00494   edge_i : edge_det
00495     port map
00496     (
00497       DATA_IN   => data_irena_id,
00498       CLK       => bclk2x_i,
00499       SUM_RIS   => SUM_RIS_i,
00500       SUM_FAL   => SUM_FAL_i,
00501       EDGE_RIS1 => EDGE_RIS1_i,
00502       EDGE_RIS2 => EDGE_RIS2_i,
00503       EDGE_RIS3 => EDGE_RIS3_i,
00504       EDGE_FAL1 => EDGE_FAL1_i,
00505       EDGE_FAL2 => EDGE_FAL2_i,
00506       EDGE_FAL3 => EDGE_FAL3_i,
00507       STATUS_P1 => STATUS_P1_i,
00508       STATUS_P2 => STATUS_P2_i,
00509       STATUS_P3 => STATUS_P3_i,
00510       STATUS_N1 => STATUS_N1_i,
00511       STATUS_N2 => STATUS_N2_i,
00512       STATUS_N3 => STATUS_N3_i
00513       );
00514 
00515 
00516   edge_e : edge_det
00517     port map
00518     (
00519       DATA_IN   => data_ewa_id,
00520       CLK       => bclk2x_i,
00521       SUM_RIS   => SUM_RIS_e,
00522       SUM_FAL   => SUM_FAL_e,
00523       EDGE_RIS1 => EDGE_RIS1_e,
00524       EDGE_RIS2 => EDGE_RIS2_e,
00525       EDGE_RIS3 => EDGE_RIS3_e,
00526       EDGE_FAL1 => EDGE_FAL1_e,
00527       EDGE_FAL2 => EDGE_FAL2_e,
00528       EDGE_FAL3 => EDGE_FAL3_e,
00529       STATUS_P1 => STATUS_P1_e,
00530       STATUS_P2 => STATUS_P2_e,
00531       STATUS_P3 => STATUS_P3_e,
00532       STATUS_N1 => STATUS_N1_e,
00533       STATUS_N2 => STATUS_N2_e,
00534       STATUS_N3 => STATUS_N3_e
00535       );
00536 
00537 
00538   bunchcycle_i : bunchcycle
00539     port map
00540     (
00541       CLK2X      => bclk2x_i,
00542       CLK         => BC_i,
00543       RESET      => RES,
00544       EN         => EN,
00545       R1          => EDGE_RIS1_i,
00546       R2         => EDGE_RIS2_i,
00547       R3         => EDGE_RIS3_i,
00548       F1         => EDGE_FAL1_i,
00549       F2         => EDGE_FAL2_i,
00550       F3         => EDGE_FAL3_i,
00551       SR1         => STATUS_P1_i,
00552       SR2         => STATUS_P2_i,
00553       SR3        => STATUS_P3_i,
00554       SF1        => STATUS_N1_i,
00555       SF2        => STATUS_N2_i,
00556       SF3         => STATUS_N3_i,
00557       EDGE_RIS1  => RIS1_i,
00558       EDGE_RIS2  => RIS2_i,
00559       EDGE_RIS3  => RIS3_i,
00560       EDGE_FAL1  => FAL1_i,
00561       EDGE_FAL2  => FAL2_i ,
00562       EDGE_FAL3  => FAL3_i,
00563       STATUS_ER1 => S_P1_i,
00564       STATUS_ER2 => S_P2_i,
00565       STATUS_ER3 => S_P3_i ,
00566       STATUS_EF1 => S_N1_i,
00567       STATUS_EF2 => S_N2_i,
00568       STATUS_EF3 => S_N3_i,
00569       SUM_R_IN   => SUM_RIS_i,
00570       SUM_F_IN   => SUM_FAL_i,
00571       SUM_R_OUT  => SUM_R_i,
00572       SUM_F_OUT  => SUM_F_i
00573       );
00574 
00575 
00576   bunchcycle_e : bunchcycle
00577     port map
00578     (
00579       CLK2X      => bclk2x_i,
00580       CLK         => BC_i,
00581       RESET      => RES,
00582       EN         => EN,
00583       R1          => EDGE_RIS1_e,
00584       R2          => EDGE_RIS2_e,
00585       R3         => EDGE_RIS3_e,
00586       F1         => EDGE_FAL1_e ,
00587       F2         => EDGE_FAL2_e ,
00588       F3         => EDGE_FAL3_e,
00589       SR1        => STATUS_P1_e,
00590       SR2        => STATUS_P2_e,
00591       SR3         => STATUS_P3_e,
00592       SF1         => STATUS_N1_e,
00593       SF2        => STATUS_N2_e,
00594       SF3        => STATUS_N3_e,
00595       EDGE_RIS1  => RIS1_e,
00596       EDGE_RIS2  => RIS2_e,
00597       EDGE_RIS3  => RIS3_e,
00598       EDGE_FAL1  => FAL1_e,
00599       EDGE_FAL2  => FAL2_e,
00600       EDGE_FAL3  => FAL3_e,
00601       STATUS_ER1 => S_P1_e,
00602       STATUS_ER2 => S_P2_e,
00603       STATUS_ER3 => S_P3_e,
00604       STATUS_EF1 => S_N1_e,
00605       STATUS_EF2 => S_N2_e,
00606       STATUS_EF3 => S_N3_e,
00607       SUM_R_IN   => SUM_RIS_e,
00608       SUM_F_IN   => SUM_FAL_e,
00609       SUM_R_OUT  => SUM_R_e,
00610       SUM_F_OUT  => SUM_F_e
00611       );
00612 
00613 
00614   cal_i : cal
00615     port map
00616     (
00617       CLK      => BC_i,
00618       STAT_R1  => S_P1_i,
00619       STAT_R2  => S_P2_i,
00620       STAT_R3  => S_P3_i,
00621       STAT_F1  => S_N1_i,
00622       STAT_F2  => S_N2_i,
00623       STAT_F3  => S_N3_i,
00624       RIS1     => RIS1_i,
00625       RIS2     => RIS2_i,
00626       RIS3     => RIS3_i,
00627       FAL1     => FAL1_i,
00628       FAL2     => FAL2_i,
00629       FAL3     => FAL3_i,
00630       S_T1     => STATUS_T1_1 ,
00631       S_T2     => STATUS_T2_1 ,
00632       S_T3     => STATUS_T3_1 ,
00633       S_W1     => STATUS_W1_1 ,
00634       S_W2     => STATUS_W2_1 ,
00635       S_W3     => STATUS_W3_1 ,
00636       TIME1    => T1_1,
00637       TIME2    => T2_1,
00638       TIME3    => T3_1,
00639       WIDTH1   => W1_1,
00640       WIDTH2   => W2_1,
00641       WIDTH3   => W3_1,
00642       SUM_RIN  => SUM_R_i,
00643       SUM_FIN  => SUM_F_i,
00644       SUM_ROUT => SUM_RIS_1,
00645       SUM_FOUT => SUM_FAL_1,
00646       OVER     => OVERFLOW_1 
00647       );
00648 
00649 
00650   cal_e : cal
00651     port map
00652     (
00653       CLK      => BC_i,
00654       STAT_R1  => S_P1_e,
00655       STAT_R2  => S_P2_e,
00656       STAT_R3  => S_P3_e,
00657       STAT_F1  => S_N1_e,
00658       STAT_F2  => S_N2_e,
00659       STAT_F3  => S_N3_e,
00660       RIS1     => RIS1_e,
00661       RIS2     => RIS2_e,
00662       RIS3     => RIS3_e,
00663       FAL1     => FAL1_e,
00664       FAL2     => FAL2_e,
00665       FAL3     => FAL3_e,
00666       S_T1     => STATUS_T1_2 ,
00667       S_T2     => STATUS_T2_2 ,
00668       S_T3     => STATUS_T3_2 ,
00669       S_W1     => STATUS_W1_2 ,
00670       S_W2     => STATUS_W2_2 ,
00671       S_W3     => STATUS_W3_2 ,
00672       TIME1    => T1_2,
00673       TIME2    => T2_2,
00674       TIME3    => T3_2,
00675       WIDTH1   => W1_2,
00676       WIDTH2   => W2_2,
00677       WIDTH3   => W3_2,
00678       SUM_RIN  => SUM_R_e,
00679       SUM_FIN  => SUM_F_e,
00680       SUM_ROUT => SUM_RIS_2,
00681       SUM_FOUT => SUM_FAL_2,
00682       OVER     => OVERFLOW_2 
00683       );
00684 
00685 end daqrio_top_arc;