comparator4.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/comparator4.vhd,v $
--*  $Revision: 1.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;





entity comparator4 is
  port (
    CLK : in  std_logic;
    SA  : in  std_logic;
    SB  : in  std_logic;
    SC  : in  std_logic;
    SD  : in  std_logic;
    A   : in  std_logic_vector (5 downto 0);
    B   : in  std_logic_vector (5 downto 0);
    C   : in  std_logic_vector (5 downto 0);
    D   : in  std_logic_vector (5 downto 0);
    SY  : out std_logic;
    Y   : out std_logic_vector (5 downto 0)
    );
end comparator4;




architecture comparator4_arc of comparator4 is

-------------------------- signals -----------------------------
  signal a_i     : std_logic_vector (5 downto 0) := (others => '0');
  signal b_i     : std_logic_vector (5 downto 0) := (others => '0');
  signal c_i     : std_logic_vector (5 downto 0) := (others => '0');
  signal d_i     : std_logic_vector (5 downto 0) := (others => '0');
  signal ab      : std_logic_vector (5 downto 0) := (others => '0');
  signal cd      : std_logic_vector (5 downto 0) := (others => '0');
  signal ab_i    : std_logic_vector (5 downto 0) := (others => '0');
  signal cd_i    : std_logic_vector (5 downto 0) := (others => '0');
  signal final   : std_logic_vector (5 downto 0) := (others => '0');
  signal res_ab  : std_logic                     := '0';
  signal res_cd  : std_logic                     := '0';
  signal res_end : std_logic                     := '0';
  signal or_stat : std_logic                     := '0';


  component comparator_v9_0
    port (
      a       : in  std_logic_vector(5 downto 0);
      b       : in  std_logic_vector(5 downto 0);
      clk     : in  std_logic;
      ce      : in  std_logic;
      a_ge_b  : out std_logic;
      qa_ge_b : out std_logic);
  end component;

begin

  a_i <= A when SA = '1' else (others => '0');
  b_i <= B when SB = '1' else (others => '0');
  c_i <= C when SC = '1' else (others => '0');
  d_i <= D when SD = '1' else (others => '0');

  comp_1 : comparator_v9_0
    port map (
      a       => a_i ,
      b       => b_i ,
      clk     => CLK ,
      ce      => '1' ,
      a_ge_b  => res_ab,
      qa_ge_b => open);

  comp_2 : comparator_v9_0
    port map (
      a       => c_i ,
      b       => d_i ,
      clk     => CLK ,
      ce      => '1' ,
      a_ge_b  => res_cd,
      qa_ge_b => open);

  ab_i    <= a                    when res_ab = '1' else b;
  cd_i    <= c                    when res_cd = '1' else d;
  or_stat <= SA or SB or SC or SD when rising_edge(CLK);
  ab      <= ab_i                 when rising_edge(CLK);
  cd      <= cd_i                 when rising_edge(CLK);

  comp_3 : comparator_v9_0
    port map (
      a       => ab ,
      b       => cd ,
      clk     => CLK ,
      ce      => '1' ,
      a_ge_b  => res_end,
      qa_ge_b => open);

  final <= ab      when res_end = '1' else cd;
  SY    <= or_stat when rising_edge(CLK);
  Y     <= final   when rising_edge(CLK);

end comparator4_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:03 2008 for BCM-AAA by  1.5.7.1-20081012