clocks.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/main/clocks.vhd,v $
--*  $Revision: 1.27.2.5 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 18:48:14 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;






entity clocks is
  port (RESET                    : in  std_logic;
        SYSCLK                   : in  std_logic;
        REFCLK                   : in  std_logic;
        BCLK4X                   : in  std_logic;
        UPPER_MGTCLK_PAD_P_IN_EX : in  std_logic_vector(1 downto 0);
        UPPER_MGTCLK_PAD_N_IN_EX : in  std_logic_vector(1 downto 0);
        SYSCLK_INT               : out std_logic;
        DDRCLK                   : out std_logic;
        REFCLK_P                 : out std_logic;
        REFCLK_N                 : out std_logic;
        BCLK                     : out std_logic;
        BCLK2X_P                 : out std_logic;
        BCLK2X_N                 : out std_logic;
        BCLK4X_P                 : out std_logic;
        BCLK4X_N                 : out std_logic;
        RIOCLK_1                 : out std_logic;
        RIOCLK_2                 : out std_logic;
        SATA_CLK                 : out std_logic;
        SATA_LOGIC_CLK           : out std_logic;
        CLK_50MHz_OUT            : out std_logic;
        EMAC_CLK                 : out std_logic;
        INTTRIG_CLK              : out std_logic;
        CLK_HZ                   : out std_logic;
        XTAL_SEL                 : out std_logic;
        CLK_DET                  : in  std_logic;
        LOCK                     : out std_logic
        );
end clocks;






architecture coldplay of clocks is

  signal rioclk_1_i       : std_logic := '0';
  signal rioclk_1_ii      : std_logic := '0';
  signal sysclk_buf       : std_logic := '0';
  signal refclk_p_i       : std_logic := '0';
  signal refclk_n_i       : std_logic := '0';
  signal bclk_i           : std_logic := '0';
  signal bclk2x_p_i       : std_logic := '0';
  signal sataclk_i        : std_logic := '0';
  signal sataclk_ii       : std_logic := '0';
  signal fb1_i            : std_logic := '0';
  signal fb1_o            : std_logic := '0';
  signal fb2_i            : std_logic := '0';
  signal fb2_o            : std_logic := '0';
  signal dcmlock1         : std_logic := '0';
  signal dcmlock2         : std_logic := '0';
  signal clk1, clk2, clk3 : std_logic := '0';

  attribute syn_keep                 : boolean;
  attribute syn_keep of "rioclk_1_i" : signal is true;
  attribute syn_keep of "sataclk_i"  : signal is true;


  component MGT_CLOCK_MODULE
    port
      (
        ------------------- Input Differential Clocks from Pads -------------------
        UPPER_MGTCLK_PAD_N_IN : in  std_logic;
        UPPER_MGTCLK_PAD_P_IN : in  std_logic;
        ------------------------- Output Reference Clocks -------------------------
        REFCLK1_OUT           : out std_logic

        );
  end component;


  component clock_divider is
    generic(
      DIVISION_FACTOR : integer range 0 to 127 := 2;  --only even numbers
      INITIAL_VALUE   : integer range 0 to 127 := 2   --only even numbers
      );
    port(
      CLK_IN  : in  std_logic;
      CLK_OUT : out std_logic
      );
  end component;


  component prescaler is
    generic (divider : integer range 0 to 127 := 10);
    port (CLK : in  std_logic;          --! Clock Input
          CE  : in  std_logic;          --! Clock Enable
          R   : in  std_logic;          --! Reset
          TC  : out std_logic           --! Clock Output
          );
  end component;

begin


  LOCK     <= dcmlock1 and dcmlock2;
  XTAL_SEL <= not CLK_DET;


  SYSCLK_BUFFER : IBUFG
    port map
    (
      O => sysclk_buf,
      I => SYSCLK
      );

  SYSCLK_INT <= sysclk_buf;


  mgt_clock_module_110 : MGT_CLOCK_MODULE
    port map
    (
      ------------------- Input Differential Clocks from Pads ---------------
      UPPER_MGTCLK_PAD_N_IN => UPPER_MGTCLK_PAD_N_IN_EX(1),
      UPPER_MGTCLK_PAD_P_IN => UPPER_MGTCLK_PAD_P_IN_EX(1),
      ------------------------- Output Reference Clocks ---------------------
      REFCLK1_OUT           => rioclk_1_i
      );


  mgt_clock_module_102 : MGT_CLOCK_MODULE
    port map
    (
      ------------------- Input Differential Clocks from Pads ---------------
      UPPER_MGTCLK_PAD_N_IN => UPPER_MGTCLK_PAD_N_IN_EX(0),
      UPPER_MGTCLK_PAD_P_IN => UPPER_MGTCLK_PAD_P_IN_EX(0),
      ------------------------- Output Reference Clocks ---------------------
      REFCLK1_OUT           => sataclk_i
      );


  rioclkbuf  : BUFG port map(O => rioclk_1_ii, I => rioclk_1_i);

  sataclkbuf : BUFG port map(O => sataclk_ii, I => sataclk_i);  --, CE => '1', CLR => '0');

  DDRCLK   <= rioclk_1_ii;
  RIOCLK_1 <= rioclk_1_i;
  RIOCLK_2 <= rioclk_1_i;
  SATA_CLK <= sataclk_i;


  sata_clk_i : clock_divider
    generic map(
      DIVISION_FACTOR => 2,             --only even numbers
      INITIAL_VALUE   => 2              --only even numbers
      )
    port map(
      CLK_IN  => sataclk_ii ,
      CLK_OUT => SATA_LOGIC_CLK
      );



  dcm_1 : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 16.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 2,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 4,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 10.0,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,  -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS" ,  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => fb1_o,                -- 0 degree DCM CLK ouptput
      CLK180   => open,                 -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => refclk_p_i ,           -- 2X DCM CLK output
      CLK2X180 => refclk_n_i,           -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => open,                 -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => open,  --refclk_p_i,--bclk4x_p_i,       -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,                 -- 180 degree CLK synthesis out
      LOCKED   => dcmlock1,             -- DCM LOCK status output
      CLKFB    => fb1_i,                -- DCM clock feedback
      CLKIN    => sysclk_buf ,      -- Clock input (from IBUFG, BUFG or DCM)
      RST      => '0'                   -- DCM asynchronous reset input
      );

  EMAC_CLK <= sysclk_buf;
  FB1_BUF     : BUFG port map (O => fb1_i, I => fb1_o);

  REFCLKP_BUF : BUFG port map (O => REFCLK_P, I => refclk_p_i);
  REFCLK_N <= refclk_n_i;



  dcm_2 : DCM_BASE
    generic map (
      CLKDV_DIVIDE          => 4.0,  -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
      --   7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
      CLKFX_DIVIDE          => 4,       -- Can be any interger from 1 to 32
      CLKFX_MULTIPLY        => 2,       -- Can be any integer from 2 to 32
      CLKIN_DIVIDE_BY_2     => false,  -- TRUE/FALSE to enable CLKIN divide by two feature
      CLKIN_PERIOD          => 6.4,  -- Specify period of input clock in ns from 1.25 to 1000.00
      CLKOUT_PHASE_SHIFT    => "NONE",  -- Specify phase shift mode of NONE or FIXED
      CLK_FEEDBACK          => "1X",    -- Specify clock feedback of NONE or 1X
      DCM_AUTOCALIBRATION   => true,   -- DCM calibrartion circuitry TRUE/FALSE
      DCM_PERFORMANCE_MODE  => "MAX_SPEED",  -- Can be MAX_SPEED or MAX_RANGE
      DESKEW_ADJUST         => "SYSTEM_SYNCHRONOUS" ,  -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
                                        --   an integer from 0 to 15
      DFS_FREQUENCY_MODE    => "LOW",  -- LOW or HIGH frequency mode for frequency synthesis
      DLL_FREQUENCY_MODE    => "LOW",  -- LOW, HIGH, or HIGH_SER frequency mode for DLL
      DUTY_CYCLE_CORRECTION => true,    -- Duty cycle correction, TRUE or FALSE
      FACTORY_JF            => X"F0F0",  -- FACTORY JF Values Suggested to be set to X"F0F0
      PHASE_SHIFT           => 0,  -- Amount of fixed phase shift from -255 to 1023
      STARTUP_WAIT          => false)  -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
    port map (
      CLK0     => fb2_o,                -- 0 degree DCM CLK ouptput
      CLK180   => open,  --bclk4x_n_i,     -- 180 degree DCM CLK output
      CLK270   => open,                 -- 270 degree DCM CLK output
      CLK2X    => open,                 -- 2X DCM CLK output
      CLK2X180 => open,                 -- 2X, 180 degree DCM CLK out
      CLK90    => open,                 -- 90 degree DCM CLK output
      CLKDV    => bclk_i,               -- Divided DCM CLK out (CLKDV_DIVIDE)
      CLKFX    => bclk2x_p_i ,           -- DCM CLK synthesis out (M/D)
      CLKFX180 => open,  --bclk2x_n_i, -- 180 degree CLK synthesis out
      LOCKED   => dcmlock2,             -- DCM LOCK status output
      CLKFB    => fb2_i,                -- DCM clock feedback
      CLKIN    => rioclk_1_ii ,  --bclk4x_p_i,       -- Clock input (from IBUFG, BUFG or DCM)
      RST      => '0'                    -- DCM asynchronous reset input
      );

  BCLK4X_P <= fb2_i;
  FB2_BUF      : BUFG port map (O => fb2_i, I => fb2_o);

  BCLK_BUF     : BUFG port map (O => BCLK, I => bclk_i);

  BCLK2X_P_BUF : BUFG port map (O => BCLK2X_P, I => bclk2x_p_i);
  BCLK2X_N <= '0';
  BCLK4X_N <= '0';


  gen_50MHz : clock_divider
    generic map(
      DIVISION_FACTOR => 2,             --only even numbers
      INITIAL_VALUE   => 2              --only even numbers
      )
    port map(
      CLK_IN  => sysclk_buf ,
      CLK_OUT => CLK_50MHz_OUT
      );


  div1 : prescaler
    generic map (divider => 100)
    port map(
      CLK => sysclk_buf,
      CE  => '1' ,
      R   => RESET ,
      TC  => clk1
      );


  div2 : prescaler
    generic map (divider => 100)
    port map(
      CLK => clk1,
      CE  => '1' ,
      R   => RESET ,
      TC  => clk2
      );


  div3 : prescaler
    generic map (divider => 100)
    port map(
      CLK => clk2,
      CE  => '1' ,
      R   => RESET ,
      TC  => clk3
      );

  INTTRIG_CLK <= clk3;


  div4 : prescaler
    generic map (divider => 100)
    port map(
      CLK => clk3,
      CE  => '1' ,
      R   => RESET ,
      TC  => CLK_HZ 
      );

end coldplay;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:03 2008 for BCM-AAA by  1.5.7.1-20081012