mem_interface_top_idelay_ctrl.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_idelay_ctrl.vhd,v $
--*  $Revision: 1.3.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:43 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_idelay_ctrl.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;





entity mem_interface_top_idelay_ctrl is
  port(CLK200      : in  std_logic;
        RESET      : in  std_logic;
        RDY_STATUS : out std_logic
        );
end mem_interface_top_idelay_ctrl;





architecture arch of mem_interface_top_idelay_ctrl is


  component IDELAYCTRL
    port(RDY     : out std_logic;
          REFCLK : in  std_logic;
          RST    : in  std_logic
          );
  end component;

begin

  idelayctrl0 : IDELAYCTRL port map
    (RDY     => RDY_STATUS,
      REFCLK  => CLK200,
      RST    => RESET
      );

end arch;

---

Author: M.Niegl

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