ddr_data_buffer.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/ddr_data_buffer.vhd,v $
--*  $Revision: 1.6.2.4 $                                          *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:43 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;
library work;
use work.main_components.all;


entity ddr_data_buffer is
  port (
    CLK_A    : in  std_logic;
    CLK_B    : in  std_logic;
    WEN      : in  std_logic;
    RESET    : in  std_logic;
    REN      : in  std_logic;
    EMPTY    : out std_logic;
    DATA_IN  : in  std_logic_vector(191 downto 0);
    DATA_OUT : out std_logic_vector (63 downto 0)
    );
end ddr_data_buffer;


architecture ddr_data_buffer_arc of ddr_data_buffer is
----------------------------- signals -----------------------------
  signal   empty_flag : std_logic                      := '0';
  signal   over_b     : std_logic                      := '0';
  signal   en_a       : std_logic                      := '0';
  signal   addr_a     : std_logic_vector(8 downto 0)   := (others => '0');
  signal   addr_b     : std_logic_vector(6 downto 0)   := (others => '0');
  signal   data       : std_logic_vector(63 downto 0)  := (others => '0');
  signal   write_data : std_logic_vector(255 downto 0) := (others => '0');
  signal   jmp_cnt    : std_logic_vector(1 downto 0)   := (others => '0');

  constant noread     : std_logic_vector(63 downto 0)  := x"11111111_11111111";

---------------------------- components -----------------------------

  component proc_data_buf
    port (
      addra : in  std_logic_vector(8 downto 0);
      addrb : in  std_logic_vector(6 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dinb  : in  std_logic_vector(255 downto 0);
      douta : out std_logic_vector(63 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      web   : in  std_logic);
  end component;

---------------------------- main code ----------------------------
begin

  DATA_OUT   <= data;
  EMPTY      <= empty_flag;
  write_data <= noread & DATA_IN;


  bram_buf : proc_data_buf
    port map
    (
      addra => addr_a,
      addrb => addr_b,
      clka  => clk_a,
      clkb  => clk_b,
      dinb  => write_data,
      douta => data,
      ena   => en_a,
      enb   => '1' ,
      web   => WEN 
      );


  wr_addr_gen : process(clk_b)
  begin
    if clk_b'event and clk_b = '1' then
      if RESET = '1' then
        addr_b <= (others => '0');
        over_b <= '0';
      else
        if WEN = '1' then
          addr_b <= addr_b + 1;
          if addr_b = "1111110" then
            over_b <= '1';
          end if;
        else
          addr_b <= addr_b;
        end if;
      end if;
    end if;
  end process wr_addr_gen;

  empty_flag <= '0' when addr_b >= "0000110" or over_b = '1' else '1';
  en_a       <= REN;


  read_addr : process(clk_a)
  begin
    if clk_a'event and clk_a = '1' then
      if RESET = '1' then
        addr_a  <= (others => '0');
        jmp_cnt <= (others => '0');
      else
        if REN = '1' then
          if jmp_cnt = 2 then
            addr_a  <= addr_a + 2;
            jmp_cnt <= (others => '0');
          else
            jmp_cnt <= jmp_cnt + 1;
            addr_a  <= addr_a + 1;
          end if;
        else
          addr_a <= addr_a;
        end if;
      end if;
    end if;
  end process read_addr;

end ddr_data_buffer_arc;

---

Author: M.Niegl

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