ncm_temac.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/ncm_temac.vhd,v $                                                  *
--*  $Revision: 2.4.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;
library work;
use work.ncm_package.all;



entity ncm_temac is
  port (sys_clk     : in    std_logic;
        TXVLD_N     : out   std_logic;
        DATA_IN     : in    std_logic_vector(7 downto 0);
        SOF         : in    std_logic;
        EOF         : in    std_logic;
        EN          : in    std_logic;
        rst_n       : in    std_logic;
        pause       : out   std_logic;
        EMPTY       : out   std_logic;
        gmii_rx_clk : in    std_logic;
        gmii_rx_dv  : in    std_logic;
        gmii_rx_er  : in    std_logic;
        gmii_rxd    : in    std_logic_vector (0 to 7);
        mii_tx_clk  : in    std_logic;
        gmii_tx_en  : out   std_logic;
        gmii_tx_er  : out   std_logic;
        gmii_txd    : out   std_logic_vector(0 to 3);
        MDC_0       : out   std_logic;
        mdio        : inout std_logic;
        phy_rst_n   : out   std_logic;
        DATA_OUT    : out   std_logic_vector(7 downto 0);
        DATAVLD     : out   std_logic;
        PACKET      : out   std_logic_vector(19 downto 0);
        DATA_TYPE   : out   std_logic_vector(11 downto 0);
        ARP_vld     : out   std_logic;
        SHA         : out   std_logic_vector(47 downto 0);
        SPA         : out   std_logic_vector(31 downto 0);
        led1        : out   std_logic;
        led2        : out   std_logic
        );
end ncm_temac;



architecture ncm_temac_arc of ncm_temac is

  signal clk            : std_logic;
  signal sys_rst        : std_logic;
  signal dcm1_locked    : std_logic;
  signal dcm2_locked    : std_logic;
  signal dcm_locked     : std_logic;
  signal tx_fifo_data   : std_logic_vector(31 downto 0);
  signal tx_fifo_en     : std_logic;
  signal tx_fifo_full   : std_logic;
  signal n_tx_fifo_full : std_logic;
  signal tx_fifo_lock_n : std_logic;
  signal rx_fifo_rst    : std_logic := '0';
  signal rx_fifo_data   : std_logic_vector(31 downto 0);
  signal rx_fifo_en     : std_logic := '1';
  signal running        : std_logic := '0';
  signal good_packet    : std_logic;
  signal gmii_tx_clk_i  : std_logic;
  signal gmii_tx_en_i   : std_logic;
  signal gmii_tx_er_i   : std_logic;
  signal gmii_txd_i     : std_logic_vector(0 to 7);
  signal gmii_rxd_i     : std_logic_vector(0 to 7);
  signal gmii_col       : std_logic := '0';
  signal gmii_crs       : std_logic := '1';

begin

  led1 <= running;
  led2 <= dcm_locked;

  tx_fifo_lock_n <= '1';

  gmii_tx_en <= gmii_tx_en_i;
  gmii_tx_er <= gmii_tx_er_i;
  gmii_txd   <= gmii_txd_i(0 to 3);
  gmii_rxd_i <= gmii_rxd;

  gmii_col <= '0';
  gmii_crs <= '1';

  clk <= sys_clk;

  dcm2_locked <= '1';                   -- for later use

  dcm_locked <= dcm1_locked and dcm2_locked;
  sys_rst    <= not rst_n;              -- and dcm_locked);

  phy_rst_n <= rst_n;


  emac0 : temac_controller port map (
    TXVLD_N        => TXVLD_N,
    gmii_col       => gmii_col,
    gmii_crs       => gmii_crs,
    gmii_rx_clk    => gmii_rx_clk,
    gmii_rx_dv     => gmii_rx_dv,
    gmii_rx_er     => gmii_rx_er,
    gmii_rxd       => gmii_rxd_i,
    mii_tx_clk      => mii_tx_clk,
    gmii_tx_clk    => gmii_tx_clk_i,
    gmii_tx_en     => gmii_tx_en_i,
    gmii_tx_er     => gmii_tx_er_i,
    gmii_txd       => gmii_txd_i,
    MDC_0          => MDC_0,
    mdio           => mdio,
    phy_mii_int    => open,             -- interrupt not used now
    dcm1_locked    => dcm1_locked,
    sys_rst        => sys_rst,
    sys_clk        => clk,
    -- tx fifo interface
    tx_fifo_data   => tx_fifo_data,
    tx_fifo_wren   => tx_fifo_en,
    tx_fifo_full   => tx_fifo_full,
    tx_fifo_lock_n => tx_fifo_lock_n,   -- default: keep sending
    EMPTY          => EMPTY,
    -- rx fifo interface
    rx_fifo_rst    => rx_fifo_rst,
    rx_fifo_data   => rx_fifo_data,
    rx_fifo_rden   => rx_fifo_en,
    clk_100mhz     => clk
    );

  PAUSE          <= tx_fifo_full;       --not tx_fifo_en;
  n_tx_fifo_full <= not tx_fifo_full;

  ---------------------------------------------------------------------------------


  pack : process(clk)
    variable last_good : std_logic               := '0';
    variable cnt       : integer range 0 to 1000 := 0;
  begin
    if (rising_edge(clk)) then
      
      if (cnt = 0) then
        if (last_good = '0' and rx_fifo_data(22) = '1') then
          cnt         := 999;
          good_packet <= '1';
        else
          last_good   := rx_fifo_data(22);
          good_packet <= '0';
        end if;
        
      else
        last_good := rx_fifo_data(22);
        cnt       := cnt - 1;
      end if;
      
    end if;
  end process;


  RX : auto_receiver
    port map
    (
      clk             => sys_clk,
      en              => '1',
      busy            => open,
      rx_fifo_rst     => rx_fifo_rst,
      rx_fifo_data    => rx_fifo_data(7 downto 0),
      rx_fifo_en      => rx_fifo_en,
      rx_good_packet  => rx_fifo_data(22),
      rx_bad_packet   => rx_fifo_data(21),
      rx_valid        => rx_fifo_data(20),
      rx_rderr        => rx_fifo_data(23),
      ncm_sync        => open,
      ncm_rcv_channel => open,
      ncm_rcv_en      => DATAVLD,
      ncm_rcv_data    => DATA_OUT ,
      ncm_rcv_reset   => open,
      ARP_vld         => ARP_vld,
      SHA             => SHA,
      SPA             => SPA,
      PACKET          => PACKET,
      DATA_TYPE       => DATA_TYPE,
      lastpacketlen   => open,
      goodcnt         => open,
      nobroadcst      => open,
      badcnt          => open
      );

  tx_fifo_en <= running when rising_edge(clk);

  fillit : process(clk, sys_rst)
  begin
    if (sys_rst = '1') then
      running      <= '0';
      tx_fifo_data <= x"ffffffff";
    elsif rising_edge(clk) then
      if EN = '1' then
        if EOF = '0' and running = '1' then
          running      <= '0';
          tx_fifo_data <= x"000000" & DATA_IN;
        elsif running = '1' then
          tx_fifo_data <= x"000001" & DATA_IN;
        elsif SOF = '0' then
          running      <= '1';
          tx_fifo_data <= x"000001ff";
        else
          running      <= '0';
          tx_fifo_data <= x"ffffffff";
        end if;
      else
        running      <= '0';
        tx_fifo_data <= x"ffffffff";
      end if;
    end if;
  end process;
  
end ncm_temac_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012