LCD.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/lcd/LCD.vhd,v $                                                  *
--*  $Revision: 1.7.2.4 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:46 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
library work;
use work.main_components.all;
use work.lcd_characters.all;



entity LCD is
  port (
    LCDCLK        : in    std_logic;
    LCD_DIRECTION : out   std_logic;
    LCD_RS        : out   std_logic;
    LCD_RW        : out   std_logic;
    LCD_E         : out   std_logic;
    LCD_DB        : inout std_logic_vector(7 downto 0);
    TAKE          : in    std_logic;
    GIVE          : in    std_logic;
    RES           : in    std_logic
    );
end LCD;


architecture LCD_arc of LCD is

  signal lcd_clk   : std_logic := '0';
  signal init_lcd  : std_logic := '0';
  signal paint_lcd : std_logic := '0';
  signal busy_lcd  : std_logic := '0';
  signal line1_lcd : lcd_line;
  signal line2_lcd : lcd_line;
  signal lcd_cs    : lcd_states;

begin


  gen_lcdclk : prescaler                --* gen slow clk for lcd
    generic map (divider => 52)
    port map(
      CLK => LCDCLK,
      CE  => '1' ,
      R   => RES ,
      TC  => lcd_clk 
      );

  LCD_FSM : process(lcd_clk)
    variable cnt : integer range 0 to 7;
  begin
    if lcd_clk'event and lcd_clk = '1' then
      if RES = '1' then
        init_lcd <= '1';
        lcd_cs   <= lcdinit;
      else
        case lcd_cs is
          when lcdinit =>
            cnt := cnt + 1;
            if cnt = 1 then
              init_lcd <= '1';
              cnt      := 0;
              lcd_cs   <= lcdwrite;
            else
              lcd_cs <= lcd_cs;
            end if;
            
          when lcdwrite =>
            if busy_lcd = '0' then
              paint_lcd <= '1';
              if (TAKE and GIVE) = '1' then
                line1_lcd <= (ch_f_c, ch_u_c, ch_c_c, ch_k_c, ch_space, ch_e_c, ch_r, ch_r, ch_o, ch_r, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space);
                line2_lcd <= (ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space);
              elsif TAKE = '1' then
                line1_lcd <= (ch_space, ch_space, ch_t_c, ch_a, ch_k, ch_i, ch_n, ch_g, ch_space, ch_space, ch_d_c, ch_a, ch_t, ch_a, ch_space, ch_space);
                line2_lcd <= (ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star, ch_star);
              elsif GIVE = '1' then
                line1_lcd <= (ch_space, ch_space, ch_r_c, ch_e, ch_a, ch_d, ch_i, ch_n, ch_g, ch_space, ch_space, ch_o_c, ch_u, ch_t, ch_space, ch_space);
                line2_lcd <= (ch_i_c, ch_r, ch_e, ch_n, ch_a, ch_space, ch_w, ch_a, ch_i, ch_t, ch_i, ch_n, ch_g, ch_dot, ch_dot, ch_dot);
              else
                line1_lcd <= (ch_f_c, ch_u_c, ch_c_c, ch_k_c, ch_space, ch_e_c, ch_r, ch_r, ch_o, ch_r, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space);
                line2_lcd <= (ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space, ch_space);
              end if;
            else
              null;
            end if;
            lcd_cs <= lcd_cs;
            
          when others =>
            lcd_cs <= lcdinit;
            
        end case;
      end if;
    end if;
  end process LCD_FSM;


  lcd_contr : lcd_controller
    port map
    (
      CLOCK_LCD       => lcd_clk ,
      CLOCK_ANI_I     => lcd_clk,
      CLOCK_ANI_II     => lcd_clk,
      LINE_I          => line1_lcd,
      LINE_II         => line2_lcd,
      LINE_I_PAINT    => paint_lcd,
      LINE_II_PAINT   => paint_lcd,
      LINE_I_MODE     => "00",
      LINE_II_MODE    => "00",
      AUTO_REFRESH_I  => '1',
      AUTO_REFRESH_II => '1',
      BUSY            => busy_lcd,
      DIRECTION       => LCD_DIRECTION,
      RS              => LCD_RS,
      RW              => LCD_RW,
      DB              => LCD_DB,
      E               => LCD_E
      );


end LCD_arc;

---

Author: M.Niegl

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