bcm_rod_formatter.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod_formatter.vhd,v $
--*  $Revision: 1.21.2.6 $                                         *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;









entity bcm_rod_formatter is
  generic (
    -- some data constants:
    INPUT_DATA_WIDTH             : positive                      := 32;
    MAX_FRAGMENT_SIZE            : std_logic_vector(11 downto 0) := X"17f";
    -- some constants for the header:
    SLINK_BEGIN_OF_FRAGMENT      : std_logic_vector(31 downto 0) := X"b0f00000";
    SLINK_END_OF_FRAGMENT        : std_logic_vector(31 downto 0) := X"e0f00000";
    ROD_HEADER                   : std_logic_vector(31 downto 0) := X"ee1234ee";
    ROD_HEADER_WORDS             : std_logic_vector(31 downto 0) := X"00000009";
    ROD_STATUS_BLOCK_WORD1       : std_logic_vector(31 downto 0) := X"12345678";
    ROD_STATUS_BLOCK_WORD2       : std_logic_vector(31 downto 0) := X"87654321";
    ROD_STATUS_BLOCK_WORDS       : std_logic_vector(31 downto 0) := X"00000002";
    ROD_STATUS_BLOCK_BEFORE_DATA : std_logic_vector(31 downto 0) := X"00000000";
    ROD_STATUS_BLOCK_AFTER_DATA  : std_logic_vector(31 downto 0) := X"00000001";
    ROD_EMPTY                    : std_logic_vector(31 downto 0) := X"00000000"
    );
  port (
    -- clock and synchronus reset 
    CLK                     : in  std_logic;
    SCLR                    : in  std_logic;
    -- input data
    rod_data_vld            : in  std_logic;
    rod_data_available      : in  std_logic                     := '0';
    rod_fragment_end        : in  std_logic                     := '0';
    rod_input_data          : in  std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
    rod_data_next           : out std_logic                     := '0';
    rod_format_version      : in  std_logic_vector(31 downto 0) := X"03010001";
    rod_source_ID           : in  std_logic_vector(31 downto 0) := X"00810000";
    rod_run_number          : in  std_logic_vector(31 downto 0) := X"7fffffff";
    rod_CTP_trigger_type    : in  std_logic_vector(31 downto 0) := X"00000011";
    rod_detector_event_type : in  std_logic_vector(31 downto 0) := X"000000dd";
    -- SLINK interface:
    hola_LFF                : in  std_logic;
    hola_LDOWN              : in  std_logic;
    hola_LRL                : in  std_logic_vector(3 downto 0);
    hola_CLK                : out std_logic;
    hola_UD                 : out std_logic_vector(31 downto 0);
    hola_URESET             : out std_logic;
    hola_UTEST              : out std_logic;
    hola_UCTRL              : out std_logic;
    hola_UWEN               : out std_logic;
    hola_UDW                : out std_logic_vector(1 downto 0)  := "00"
    );
end bcm_rod_formatter;


architecture bcm_rod_formatter_arc of bcm_rod_formatter is


  component bcm_rod_slink
    port (
      CLK                           : in  std_logic;
      SCLR                          : in  std_logic;
      formatter_control_word_flag   : in  std_logic;
      formatter_data_in             : in  std_logic_vector(31 downto 0);
      formatter_data_valid          : in  std_logic;
      formatter_reset_link          : in  std_logic;
      formatter_ignore_slink_status : in  std_logic;
      formatter_stop_transfer       : out std_logic;
      -- SLINK interface    
      slink_full_flag               : in  std_logic;
      slink_down                    : in  std_logic;
      slink_link_return_lines       : in  std_logic_vector(3 downto 0);
      slink_clock                   : out std_logic;
      slink_data_out                : out std_logic_vector(31 downto 0);
      slink_reset                   : out std_logic;
      slink_test                    : out std_logic;
      slink_control_word_flag       : out std_logic;
      slink_write_enable            : out std_logic;
      slink_data_width              : out std_logic_vector(1 downto 0) := "00"
      );
  end component;


  type bcm_rod_formatter_fsm_state_typedef is (
    formatter_idle,
    formatter_begin_of_fragment,
    formatter_header,
    formatter_header_size,
    formatter_format_version,
    formatter_source_ID,
    formatter_run_number,
    formatter_Level1_ID,
    formatter_BC_ID,
    formatter_trigger_type,
    formatter_detector_event_type,
    formatter_data,
    formatter_last_data,
    formatter_status_word_1,
    formatter_status_word_2,
    formatter_status_block_words,
    formatter_data_block_words,
    formatter_status_block_position,
    formatter_end_of_fragment
    );

  signal fsm_state                   : bcm_rod_formatter_fsm_state_typedef;
  signal formatter_data_valid        : std_logic;
  signal formatter_data_in           : std_logic_vector(31 downto 0)  := (others => '0');
  signal lvlid_i                     : std_logic_vector(31 downto 0)  := (others => '0');
  signal formatter_control_word_flag : std_logic;
  signal formatter_stop_transfer     : std_logic;
  signal intern_slink_data_out       : std_logic;
  signal reset_n                     : std_logic;
  signal data_counter                : std_logic_vector(11 downto 0)  := (others => '0');
  signal buffer_data                 : std_logic_vector(223 downto 0) := (others => '0');
  signal buffer_counter              : std_logic_vector(7 downto 0)   := (others => '0');
  signal buffer_eof                  : std_logic_vector(6 downto 0)   := (others => '0');
  signal last_data_next              : std_logic;
  signal buffer_data_next            : std_logic;
  signal last_data_available         : std_logic;
  signal last_data_available_i       : std_logic;
  signal LinkBusy                    : std_logic;
  signal FSMBusy                     : std_logic;
  
begin

  reset_n                 <= not SCLR;
  formatter_stop_transfer <= LinkBusy;


  output_interface : bcm_rod_slink
    port map (
      CLK                           => CLK,
      SCLR                          => SCLR,
      -- ROD formatter interface
      formatter_control_word_flag   => formatter_control_word_flag,  --ControlWord,                
      formatter_data_in             => formatter_data_in,     --OutputBus,
      formatter_data_valid          => formatter_data_valid,  --LinkWrite,
      formatter_reset_link          => reset_n,
      formatter_ignore_slink_status => '0',  --FIXME: ignoreSlinkStatus,
      formatter_stop_transfer       => LinkBusy,
      -- SLINK interface    
      slink_full_flag               => hola_LFF,
      slink_down                    => hola_LDOWN,
      slink_link_return_lines       => hola_LRL,
      slink_clock                   => hola_CLK,
      slink_data_out                => hola_UD,
      slink_reset                   => hola_URESET ,
      slink_test                    => hola_UTEST,
      slink_control_word_flag       => hola_UCTRL,
      slink_write_enable            => hola_UWEN,
      slink_data_width              => hola_UDW
      );






  RAM_reader : process (CLK, SCLR)
  begin
    if SCLR = '1' then
      rod_data_next         <= '0';
      buffer_data_next      <= '0';
      last_data_available   <= '0';
      last_data_available_i <= '0';
      last_data_next        <= '0';
      buffer_counter        <= (others => '0');
      buffer_eof            <= (others => '0');
      buffer_data           <= (others => '0');
    elsif (CLK'event and CLK = '1') then
      if rod_data_available = '1' then
        rod_data_next    <= '1';
        buffer_data_next <= '1';
      else
        rod_data_next    <= '0';
        buffer_data_next <= '0';
      end if;
      -- shift data out
      if (formatter_stop_transfer = '0') and (fsm_state = formatter_detector_event_type or
                                              fsm_state = formatter_data or
                                              fsm_state = formatter_source_ID) then
        if fsm_state = formatter_source_ID then
          rod_data_next <= '0';
        end if;
        if (rod_data_vld and (last_data_available or last_data_available_i)) = '1' then  -- fill and shift out
          case buffer_counter is
            when "00000001" =>
              buffer_data <= X"000000000000000000000000000000000000000000000000" & rod_input_data;
              buffer_eof  <= "000000" & rod_fragment_end;
            when "00000010" =>
              buffer_data <= X"0000000000000000000000000000000000000000" & rod_input_data & buffer_data(63 downto 32);
              buffer_eof  <= "00000" & rod_fragment_end & buffer_eof(1);
            when "00000011" =>
              buffer_data <= X"00000000000000000000000000000000" & rod_input_data & buffer_data(95 downto 32);
              buffer_eof  <= "0000" & rod_fragment_end & buffer_eof(2 downto 1);
            when "00000100" =>
              buffer_data <= X"000000000000000000000000" & rod_input_data & buffer_data(127 downto 32);
              buffer_eof  <= "000" & rod_fragment_end & buffer_eof(3 downto 1);
            when "00000101" =>
              buffer_data <= X"0000000000000000" & rod_input_data & buffer_data(159 downto 32);
              buffer_eof  <= "00" & rod_fragment_end & buffer_eof(4 downto 1);
            when "00000110" =>
              buffer_data <= X"00000000" & rod_input_data & buffer_data(191 downto 32);
              buffer_eof  <= '0' & rod_fragment_end & buffer_eof(5 downto 1);
            when "00000111" =>
              buffer_data <= rod_input_data & buffer_data(223 downto 32);
              buffer_eof  <= rod_fragment_end & buffer_eof(6 downto 1);
            when others =>
              buffer_data <= rod_input_data & buffer_data(223 downto 32);
              buffer_eof  <= rod_fragment_end & buffer_eof(6 downto 1);
          end case;
          buffer_counter <= buffer_counter;
        elsif buffer_counter /= "00000000" then  -- just shift out
          buffer_data    <= rod_input_data & buffer_data(223 downto 32);
          buffer_eof     <= rod_fragment_end & buffer_eof(6 downto 1);
          buffer_counter <= buffer_counter - "01";  
        end if;
      else                              -- nothing to shift
        if (rod_data_vld and (last_data_available or last_data_available_i)) = '1' then  -- fill
          case buffer_counter is
            when "00000000" =>
              buffer_data <= X"000000000000000000000000000000000000000000000000" & rod_input_data;
              buffer_eof  <= "000000" & rod_fragment_end;
            when "00000001" =>
              buffer_data <= X"0000000000000000000000000000000000000000" & rod_input_data & buffer_data(31 downto 0);
              buffer_eof  <= "00000" & rod_fragment_end & buffer_eof(0);
            when "00000010" =>
              buffer_data <= X"00000000000000000000000000000000" & rod_input_data & buffer_data(63 downto 0);
              buffer_eof  <= "0000" & rod_fragment_end & buffer_eof(1 downto 0);
            when "00000011" =>
              buffer_data <= X"000000000000000000000000" & rod_input_data & buffer_data(95 downto 0);
              buffer_eof  <= "000" & rod_fragment_end & buffer_eof(2 downto 0);
            when "00000100" =>
              buffer_data <= X"0000000000000000" & rod_input_data & buffer_data(127 downto 0);
              buffer_eof  <= "00" & rod_fragment_end & buffer_eof(3 downto 0);
            when "00000101" =>
              buffer_data   <= X"00000000" & rod_input_data & buffer_data(159 downto 0);
              buffer_eof    <= '0' & rod_fragment_end & buffer_eof(4 downto 0);
              rod_data_next <= '0';
            when "00000110" =>
              buffer_data   <= rod_input_data & buffer_data(191 downto 0);
              buffer_eof    <= rod_fragment_end & buffer_eof(5 downto 0);
              rod_data_next <= '0';
            when "00000111" =>
              buffer_data   <= buffer_data;
              buffer_eof    <= buffer_eof;
              rod_data_next <= '0';
            when others =>
              buffer_data <= rod_input_data & buffer_data(223 downto 32);
              buffer_eof  <= rod_fragment_end & buffer_eof(6 downto 1);
          end case;
          buffer_counter <= buffer_counter + "01";
        elsif buffer_counter /= "00000000" then
          rod_data_next <= '0';
        end if;
      end if;
      last_data_next        <= buffer_data_next;
      last_data_available   <= rod_data_available;
      last_data_available_i <= last_data_available;
    end if;
  end process;



  formatter_fsm : process (CLK, SCLR)
  begin
    if (SCLR = '1') then
      fsm_state                   <= formatter_idle;
      formatter_data_valid        <= '0';
      formatter_control_word_flag <= '1';
      formatter_data_in           <= ROD_EMPTY;
      data_counter                <= X"000";
      lvlid_i                     <= (others => '0');
    elsif (CLK'event and CLK = '1') then
      if (formatter_stop_transfer = '1') then
        fsm_state                   <= fsm_state;
        formatter_data_valid        <= formatter_data_valid;
        formatter_control_word_flag <= formatter_control_word_flag;
        formatter_data_in           <= formatter_data_in;
        data_counter                <= data_counter;
      else
        if ((fsm_state = formatter_end_of_fragment or fsm_state = formatter_idle) and (buffer_counter = "000")) then
          formatter_data_valid <= '0';
        else
          formatter_data_valid <= '1';
        end if;
        if ((fsm_state = formatter_status_block_position) or
            (fsm_state = formatter_end_of_fragment and (not (buffer_counter = "000"))) or
            (fsm_state = formatter_idle and (not (buffer_counter = "000")))) then
          formatter_control_word_flag <= '0';
        else
          formatter_control_word_flag <= '1';
        end if;
        data_counter <= data_counter;
        case fsm_state is
          when formatter_idle =>
            if (not (buffer_counter = "0000")) then
              fsm_state         <= formatter_begin_of_fragment;
              formatter_data_in <= SLINK_BEGIN_OF_FRAGMENT;
            else
              fsm_state         <= formatter_idle;
              formatter_data_in <= ROD_EMPTY;
            end if;
          when formatter_begin_of_fragment =>
            fsm_state         <= formatter_header;
            formatter_data_in <= ROD_HEADER;
          when formatter_header =>
            fsm_state         <= formatter_header_size;
            formatter_data_in <= ROD_HEADER_WORDS;
          when formatter_header_size =>
            fsm_state         <= formatter_format_version;
            formatter_data_in <= rod_format_version;
          when formatter_format_version =>
            fsm_state         <= formatter_source_ID;
            formatter_data_in <= rod_source_ID;
          when formatter_source_ID =>
            fsm_state         <= formatter_run_number;
            formatter_data_in <= rod_run_number;
            lvlid_i           <= buffer_data(31 downto 0);
          when formatter_run_number =>
            fsm_state         <= formatter_Level1_ID;
            formatter_data_in <= lvlid_i;
          when formatter_Level1_ID =>
            fsm_state         <= formatter_BC_ID;
            formatter_data_in <= x"00000" & buffer_data(31 downto 20);
          when formatter_BC_ID =>
            fsm_state         <= formatter_trigger_type;
            formatter_data_in <= rod_CTP_trigger_type;
          when formatter_trigger_type =>
            fsm_state         <= formatter_detector_event_type;
            formatter_data_in <= rod_detector_event_type;
          when formatter_detector_event_type =>
            fsm_state         <= formatter_data;
            formatter_data_in <= buffer_data(31 downto 0);
            data_counter      <= (data_counter + "01");
          when formatter_data =>
            data_counter      <= (data_counter + "01");
            formatter_data_in <= buffer_data(31 downto 0);
            if (data_counter = MAX_FRAGMENT_SIZE or buffer_eof(0) = '1') then
              fsm_state <= formatter_last_data;
            else
              fsm_state <= formatter_data;
            end if;
          when formatter_last_data =>
            fsm_state         <= formatter_status_word_1;
            formatter_data_in <= ROD_STATUS_BLOCK_WORD1;
          when formatter_status_word_1 =>
            fsm_state         <= formatter_status_word_2;
            formatter_data_in <= ROD_STATUS_BLOCK_WORD2;
          when formatter_status_word_2 =>
            fsm_state         <= formatter_status_block_words;
            formatter_data_in <= ROD_STATUS_BLOCK_WORDS;
          when formatter_status_block_words =>
            fsm_state         <= formatter_data_block_words;
            formatter_data_in <= X"00000" & data_counter;
          when formatter_data_block_words =>
            fsm_state         <= formatter_status_block_position;
            formatter_data_in <= ROD_STATUS_BLOCK_AFTER_DATA;
            data_counter      <= X"000";
          when formatter_status_block_position =>
            fsm_state         <= formatter_end_of_fragment;
            formatter_data_in <= SLINK_END_OF_FRAGMENT;
          when formatter_end_of_fragment =>
            if buffer_counter /= 0 then
              fsm_state         <= formatter_begin_of_fragment;
              formatter_data_in <= SLINK_BEGIN_OF_FRAGMENT;
            else
              fsm_state         <= formatter_idle;
              formatter_data_in <= ROD_EMPTY;
            end if;
          when others => null;
        end case;
      end if;
    end if;
  end process;
  
end bcm_rod_formatter_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012