ddr2_mem.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem.vhd,v $
--*  $Revision: 1.6.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 21:55:52 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: ddr2_mem.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- 
-- Device: Virtex-4
-- Design Name: DDR2_V4
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
-- pragma translate_off

library unisim;

use unisim.vcomponents.all;
-- pragma translate_on




entity ddr2_mem is
  port (
    cntrl0_DDR2_DQ            : inout std_logic_vector(63 downto 0);
    cntrl0_DDR2_A             : out   std_logic_vector(13 downto 0);
    cntrl0_DDR2_BA            : out   std_logic_vector(1 downto 0);
    cntrl0_DDR2_RAS_N         : out   std_logic;
    cntrl0_DDR2_CAS_N         : out   std_logic;
    cntrl0_DDR2_WE_N          : out   std_logic;
    cntrl0_DDR2_RESET_N       : out   std_logic;
    cntrl0_DDR2_CS_N          : out   std_logic;
    cntrl0_DDR2_ODT           : out   std_logic;
    cntrl0_DDR2_CKE           : out   std_logic;
    cntrl0_DDR2_DM            : out   std_logic_vector(7 downto 0);
    SYS_CLK_P                 : in    std_logic;
    SYS_CLK_N                 : in    std_logic;
    CLK200_P                  : in    std_logic;
    CLK200_N                  : in    std_logic;
    SYS_RESET_IN              : in    std_logic;
    cntrl0_CLK_TB             : out   std_logic;
    cntrl0_RESET_TB           : out   std_logic;
    cntrl0_WDF_ALMOST_FULL    : out   std_logic;
    cntrl0_AF_ALMOST_FULL     : out   std_logic;
    cntrl0_READ_DATA_VALID    : out   std_logic;
    cntrl0_APP_WDF_WREN       : in    std_logic;
    cntrl0_APP_AF_WREN        : in    std_logic;
    cntrl0_BURST_LENGTH       : out   std_logic_vector(2 downto 0);
    cntrl0_APP_AF_ADDR        : in    std_logic_vector(35 downto 0);
    cntrl0_READ_DATA_FIFO_OUT : out   std_logic_vector(127 downto 0);
    cntrl0_APP_WDF_DATA       : in    std_logic_vector(127 downto 0);
    cntrl0_APP_MASK_DATA      : in    std_logic_vector(15 downto 0);
    cntrl0_DDR2_DQS           : inout std_logic_vector(7 downto 0);
    cntrl0_DDR2_DQS_N         : inout std_logic_vector(7 downto 0);
    cntrl0_DDR2_CK            : out   std_logic;
    cntrl0_DDR2_CK_N          : out   std_logic;
    LOCK_IN                   : in    std_logic
    );
end entity;




architecture arc_ddr2_mem of ddr2_mem is


  component ddr2_mem_top_0
    port (
      DDR2_DQ            : inout std_logic_vector(63 downto 0);
      DDR2_A             : out   std_logic_vector(13 downto 0);
      DDR2_BA            : out   std_logic_vector(1 downto 0);
      DDR2_RAS_N         : out   std_logic;
      DDR2_CAS_N         : out   std_logic;
      DDR2_WE_N          : out   std_logic;
      DDR2_RESET_N       : out   std_logic;
      DDR2_CS_N          : out   std_logic;
      DDR2_ODT           : out   std_logic;
      DDR2_CKE           : out   std_logic;
      DDR2_DM            : out   std_logic_vector(7 downto 0);
      CLK_TB             : out   std_logic;
      RESET_TB           : out   std_logic;
      WDF_ALMOST_FULL    : out   std_logic;
      AF_ALMOST_FULL     : out   std_logic;
      READ_DATA_VALID    : out   std_logic;
      APP_WDF_WREN       : in    std_logic;
      APP_AF_WREN        : in    std_logic;
      BURST_LENGTH       : out   std_logic_vector(2 downto 0);
      APP_AF_ADDR        : in    std_logic_vector(35 downto 0);
      READ_DATA_FIFO_OUT : out   std_logic_vector(127 downto 0);
      APP_WDF_DATA       : in    std_logic_vector(127 downto 0);
      APP_MASK_DATA      : in    std_logic_vector(15 downto 0);
      DDR2_DQS           : inout std_logic_vector(7 downto 0);
      DDR2_DQS_N         : inout std_logic_vector(7 downto 0);
      DDR2_CK            : out   std_logic;
      DDR2_CK_N          : out   std_logic;
      clk_0              : in    std_logic;
      clk_90             : in    std_logic;
      clk_50             : in    std_logic;
      ref_clk            : in    std_logic;
      sys_rst            : in    std_logic;
      sys_rst90          : in    std_logic;
      sys_rst_ref_clk_1  : in    std_logic;
      idelay_ctrl_rdy    : in    std_logic
      );
  end component;


  component ddr2_mem_infrastructure
    port (
      SYS_CLK_P         : in  std_logic;
      SYS_CLK_N         : in  std_logic;
      CLK200_P          : in  std_logic;
      CLK200_N          : in  std_logic;
      SYS_RESET_IN      : in  std_logic;
      LOCK              : in  std_logic;
      CLK               : out std_logic;
      CLK90             : out std_logic;
      CLK50             : out std_logic;
      CLK200            : out std_logic;
      REFRESH_CLK       : out std_logic;
      sys_rst           : out std_logic;
      sys_rst90         : out std_logic;
      sys_rst_ref_clk_1 : out std_logic
      );
  end component;


  component ddr2_mem_idelay_ctrl
    port (
      CLK200     : in  std_logic;
      RESET      : in  std_logic;
      RDY_STATUS : out std_logic
      );
  end component;

  signal idelay_ctrl_rdy   : std_logic;
  signal sys_rst           : std_logic;
  signal sys_rst90         : std_logic;
  signal sys_rst_ref_clk_1 : std_logic;
  signal clk_0             : std_logic;
  signal clk_90            : std_logic;
  signal clk_50            : std_logic;
  signal ref_clk           : std_logic;

begin


  top_00 : ddr2_mem_top_0 port map
    (
      DDR2_DQ            => cntrl0_DDR2_DQ,
      DDR2_A             => cntrl0_DDR2_A ,
      DDR2_BA            => cntrl0_DDR2_BA,
      DDR2_RAS_N         => cntrl0_DDR2_RAS_N ,
      DDR2_CAS_N         => cntrl0_DDR2_CAS_N ,
      DDR2_WE_N          => cntrl0_DDR2_WE_N ,
      DDR2_RESET_N       => cntrl0_DDR2_RESET_N ,
      DDR2_CS_N          => cntrl0_DDR2_CS_N ,
      DDR2_ODT           => cntrl0_DDR2_ODT ,
      DDR2_CKE           => cntrl0_DDR2_CKE ,
      DDR2_DM            => cntrl0_DDR2_DM,
      CLK_TB             => cntrl0_CLK_TB,
      RESET_TB           => cntrl0_RESET_TB ,
      WDF_ALMOST_FULL    => cntrl0_WDF_ALMOST_FULL ,
      AF_ALMOST_FULL     => cntrl0_AF_ALMOST_FULL ,
      READ_DATA_VALID    => cntrl0_READ_DATA_VALID ,
      APP_WDF_WREN       => cntrl0_APP_WDF_WREN ,
      APP_AF_WREN        => cntrl0_APP_AF_WREN ,
      BURST_LENGTH       => cntrl0_BURST_LENGTH ,
      APP_AF_ADDR        => cntrl0_APP_AF_ADDR ,
      READ_DATA_FIFO_OUT => cntrl0_READ_DATA_FIFO_OUT,
      APP_WDF_DATA       => cntrl0_APP_WDF_DATA ,
      APP_MASK_DATA      => cntrl0_APP_MASK_DATA ,
      DDR2_DQS           => cntrl0_DDR2_DQS ,
      DDR2_DQS_N         => cntrl0_DDR2_DQS_N ,
      DDR2_CK            => cntrl0_DDR2_CK,
      DDR2_CK_N          => cntrl0_DDR2_CK_N ,
      --infrastructure signals
      clk_0              => clk_0,
      clk_90             => clk_90,
      idelay_ctrl_rdy    => idelay_ctrl_rdy,
      clk_50             => clk_50,
      ref_clk            => ref_clk,
      sys_rst            => sys_rst,
      sys_rst90          => sys_rst90,
      sys_rst_ref_clk_1  => sys_rst_ref_clk_1
      );


  infrastructure0 : ddr2_mem_infrastructure
    port map (
      SYS_CLK_P         => SYS_CLK_P,
      SYS_CLK_N         => '0',
      CLK200_P          => '0',         --CLK200_P,
      CLK200_N          => '0',
      SYS_RESET_IN      => SYS_RESET_IN,
      LOCK              => LOCK_IN,     --lock_shift,
      CLK               => clk_0,
      CLK90             => clk_90,
      CLK50             => clk_50,
      CLK200            => open,
      REFRESH_CLK       => ref_clk,
      sys_rst           => sys_rst,
      sys_rst90         => sys_rst90,
      sys_rst_ref_clk_1 => sys_rst_ref_clk_1
      );


  idelay_ctrl0 : ddr2_mem_idelay_ctrl
    port map (
      CLK200     => SYS_CLK_P,
      RESET      => sys_rst,
      RDY_STATUS => idelay_ctrl_rdy
      );

end arc_ddr2_mem;

---

Author: M.Niegl

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