bcm_rod_slink.vhd

Go to the documentation of this file.

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod_slink.vhd,v $*
--*  $Revision: 1.12.2.5 $                                     *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


library unisim;

use unisim.vcomponents.all;





entity bcm_rod_slink is
  generic (
    DATA_WIDTH : std_logic_vector(1 downto 0) := "00";
    TEST       : std_logic                    := '1'
    );
  port (
    CLK                           : in  std_logic;
    SCLR                          : in  std_logic;
    -- ROD formatter interface     
    formatter_control_word_flag   : in  std_logic;
    formatter_data_in             : in  std_logic_vector(31 downto 0);
    formatter_data_valid          : in  std_logic;
    formatter_reset_link          : in  std_logic;
    formatter_ignore_slink_status : in  std_logic;
    formatter_stop_transfer       : out std_logic;
    -- SLINK interface    
    slink_full_flag               : in  std_logic;
    slink_down                    : in  std_logic;
    slink_link_return_lines       : in  std_logic_vector(3 downto 0);
    slink_clock                   : out std_logic;
    slink_data_out                : out std_logic_vector(31 downto 0);
    slink_reset                   : out std_logic;
    slink_test                    : out std_logic;
    slink_control_word_flag       : out std_logic;
    slink_write_enable            : out std_logic;
    slink_data_width              : out std_logic_vector(1 downto 0) := "00"
    );
end bcm_rod_slink;


architecture bcm_rod_slink_arc of bcm_rod_slink is


  type bcm_slink_fsm_state_typedef is (
    link_idle,
    link_down,
    link_write,
    link_notransfer,
    link_full,
    link_wait1,
    link_wait2,
    link_wait3
    );

  signal fsm_state              : bcm_slink_fsm_state_typedef;  -- SLINK FSM states
  signal enable                 : std_logic;
  signal fsm_stop               : std_logic;
  signal intern_slink_full_flag : std_logic;
  signal intern_slink_down      : std_logic;
  signal intern_enable          : std_logic;
  signal intern_data_pending    : std_logic;
  
begin
  
  slink_data_width        <= DATA_WIDTH;
  slink_test              <= TEST;
  slink_clock             <= CLK;
  slink_reset             <= not (SCLR);
  enable                  <= (formatter_ignore_slink_status or (intern_slink_full_flag and intern_slink_down)) and not fsm_stop;
  formatter_stop_transfer <= not formatter_ignore_slink_status and (not (intern_slink_full_flag and intern_slink_down) or fsm_stop);


  slink_full_FDRSE : FDRSE
    generic map (
      INIT => '0' )  -- Initial value of register ('0' or '1')  
    port map (
      Q  => intern_slink_full_flag,     -- Data output
      C   => CLK ,                        -- Clock input
      CE => '1' ,                        -- Clock enable input
      D   => slink_full_flag,            -- Data input
      R  => '0' ,                        -- Synchronous reset input
      S  => '0'                         -- Synchronous set input
      );


  slink_down_FDRSE : FDRSE
    generic map (
      INIT => '0' )              -- Initial value of register ('0' or '1')  
    port map (
      Q   => intern_slink_down,          -- Data output
      C  => CLK ,                        -- Clock input
      CE => '1' ,                        -- Clock enable input
      D  => slink_down,                 -- Data input
      R  => '0' ,                        -- Synchronous reset input
      S  => '0'                         -- Synchronous set input
      );


  enable_FDRSE : FDRSE
    generic map (
      INIT => '0' )          -- Initial value of register ('0' or '1')  
    port map (
      Q  => intern_enable,              -- Data output
      C  => CLK ,                        -- Clock input
      CE => '1' ,                        -- Clock enable input
      D  => enable ,                     -- Data input
      R  => SCLR,                       -- Synchronous reset input
      S  => '0'                         -- Synchronous set input            
      );


  control_word_FDRSE : FDRSE
    generic map (
      INIT => '0' )  -- Initial value of register ('0' or '1')  
    port map (
      Q  => slink_control_word_flag,    -- Data output
      C   => CLK ,                        -- Clock input
      CE => intern_enable,              -- Clock enable input
      R  => '0' ,                        -- synchronous clear input
      D  => formatter_control_word_flag,  -- Data input
      S  => SCLR                        -- synchronous set input
      );


  data_vld : FDRSE
    generic map (
      INIT => '0' )                 -- Initial value of register ('0' or '1')  
    port map (
      Q   => intern_data_pending,        -- Data output
      C  => CLK ,                        -- Clock input
      CE => intern_enable,              -- Clock enable input
      D  => formatter_data_valid,       -- Data input
      R   => SCLR,                       -- Synchronous reset input
      S  => '0'                         -- Synchronous set input            
      );

  DFF_arr : for I in 31 downto 0 generate


    data_register : FDRSE
      generic map (
        INIT  => '0' )  -- Initial value of register ('0' or '1')  
      port map (
        Q  => slink_data_out(I),        -- Data output
        C   => CLK ,                      -- Clock input
        CE => intern_enable,            -- Clock enable input
        D  => formatter_data_in(I),     -- Data input
        R  => SCLR ,                     -- Synchronous reset input
        S  => '0'                       -- Synchronous set input          
        );

  end generate DFF_arr;


  slink_fsm : process (CLK, SCLR)
  begin
    if (SCLR = '1') then
      fsm_state          <= link_idle;
      fsm_stop           <= '1';
      slink_write_enable <= '1';
    elsif (CLK'event and CLK = '1') then
      if (intern_slink_down = '0' and formatter_ignore_slink_status = '0') then
        fsm_state          <= link_down;
        fsm_stop           <= '1';
        slink_write_enable <= '1';
      else
        case fsm_state is
          when link_idle =>
            fsm_stop <= '0';
            if (formatter_data_valid = '1') then
              fsm_state          <= link_write;
              slink_write_enable <= '0';
            else
              fsm_state <= link_notransfer;
            end if;
          when link_write =>
            if ((intern_slink_full_flag = '1' or formatter_ignore_slink_status = '1') and formatter_data_valid = '0') then
              fsm_state          <= link_notransfer;
              slink_write_enable <= '1';
            elsif (intern_slink_full_flag = '0' and formatter_ignore_slink_status = '0') then
              fsm_state          <= link_full;
              slink_write_enable <= '1';
            else
              fsm_state <= link_write;
            end if;
          when link_notransfer =>
            if ((intern_slink_full_flag = '1' or formatter_ignore_slink_status = '1') and formatter_data_valid = '1') then
              fsm_state          <= link_write;
              slink_write_enable <= '0';
            elsif (intern_slink_full_flag = '0' and formatter_ignore_slink_status = '0') then
              fsm_state <= link_full;
            else
              fsm_state <= link_notransfer;
            end if;
          when link_full =>
            if (formatter_ignore_slink_status = '1') then
              -- After a reset the ignore SlinkStatus might be set to '0'.
              -- if there is active ('0') lff line the STM ends up in the
              -- LinkFull_state. In order to ignore the lff there must be
              -- a way to escape the state if the ignoreSlinkStatus line
              -- is set to '1' later. Therfore this condition here.
              fsm_state <= link_idle;
            elsif (intern_slink_full_flag = '1' and intern_data_pending = '1') then
              fsm_state          <= link_write;
              slink_write_enable <= '0';
            elsif (intern_slink_full_flag = '1' and intern_data_pending = '0') then
              fsm_state <= link_notransfer;
            else
              fsm_state <= link_full;
            end if;
          when link_down =>
            fsm_state <= link_wait1;
          when link_wait1 =>
            fsm_state <= link_wait2;
          when link_wait2 =>
            fsm_state <= link_wait3;
          when link_wait3 =>
            fsm_state <= link_idle;
            fsm_stop  <= '0';
        end case;
      end if;
    end if;
  end process slink_fsm;

end bcm_rod_slink_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012