00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/ctp_comm.vhd,v $
00015 --* $Revision: 1.2.2.3 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:45 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023
00024
00025 library ieee;
00026
00027 use ieee.std_logic_1164.all;
00028
00029
00030
00031
00032
00033
00034 entity ctp_comm is
00035
00036 port (
00037 CLK : in ;
00038 RESET : in ;
00039 SET_EN : in ;
00040 SET_VAL : in (9 downto 1);
00041 CTP_OUT : out (9 downto 1)
00042 );
00043
00044 end ctp_comm;
00045
00046
00047
00048
00049
00050
00051 architecture ctp_comm_arc of ctp_comm is
00052
00053 begin -- ctp_comm_arc
00054
00055
00056 ctp_set : process (CLK, RESET)
00057 begin -- process ctp_set
00058 if RESET = '1' then -- asynchronous reset (active high)
00059 CTP_OUT <= (others => '0');
00060 elsif CLK'event and CLK = '1' then -- rising clock edge
00061 if SET_EN = '1' then
00062 CTP_OUT <= SET_VAL;
00063 end if;
00064 end if;
00065 end process ctp_set;
00066
00067 end ctp_comm_arc;