bcm_signal_delay.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_signal_delay.vhd,v $
--*  $Revision: 1.3.2.4 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


entity bcm_signal_delay is
  port (
    CLK           : in  std_logic;
    SCLR          : in  std_logic;
    delay_setting : in  std_logic_vector(7 downto 0);
    data_input    : in  std_logic;
    data_output   : out std_logic
    );

  attribute shreg_extract                     : string;
  attribute shreg_extract of bcm_signal_delay : entity is "yes";
  
end bcm_signal_delay;


architecture bcm_signal_delay_arc of bcm_signal_delay is
  
  signal shift_register_0 : std_logic                      := '0';
  signal shift_register_1 : std_logic_vector(1 downto 0)   := (others => '0');
  signal shift_register_2 : std_logic_vector(3 downto 0)   := (others => '0');
  signal shift_register_3 : std_logic_vector(7 downto 0)   := (others => '0');
  signal shift_register_4 : std_logic_vector(15 downto 0)  := (others => '0');
  signal shift_register_5 : std_logic_vector(31 downto 0)  := (others => '0');
  signal shift_register_6 : std_logic_vector(63 downto 0)  := (others => '0');
  signal shift_register_7 : std_logic_vector(127 downto 0) := (others => '0');
  signal connection_0     : std_logic                      := '0';
  signal connection_1     : std_logic                      := '0';
  signal connection_2     : std_logic                      := '0';
  signal connection_3     : std_logic                      := '0';
  signal connection_4     : std_logic                      := '0';
  signal connection_5     : std_logic                      := '0';
  signal connection_6     : std_logic                      := '0';
  
begin



  signal_delay : process (CLK, SCLR)
  begin
    if (SCLR = '1') then
      data_output      <= '0';
      shift_register_0 <= '0';
      connection_0     <= '0';
      connection_1     <= '0';
      connection_2     <= '0';
      connection_3     <= '0';
      connection_4     <= '0';
      connection_5     <= '0';
      connection_6     <= '0';
    elsif (CLK'event and CLK = '1') then
      if (delay_setting(0) = '1') then
        shift_register_0 <= data_input;
        connection_0     <= shift_register_0;
      else
        connection_0 <= data_input;
      end if;
      if (delay_setting(1) = '1') then
        shift_register_1 <= connection_0 & shift_register_1(1);
        connection_1     <= shift_register_1(0);
      else
        connection_1 <= connection_0;
      end if;
      if (delay_setting(2) = '1') then
        shift_register_2 <= connection_1 & shift_register_2(3 downto 1);
        connection_2     <= shift_register_2(0);
      else
        connection_2 <= connection_1;
      end if;
      if (delay_setting(3) = '1') then
        shift_register_3 <= connection_2 & shift_register_3(7 downto 1);
        connection_3     <= shift_register_3(0);
      else
        connection_3 <= connection_2;
      end if;
      if (delay_setting(4) = '1') then
        shift_register_4 <= connection_3 & shift_register_4(15 downto 1);
        connection_4     <= shift_register_4(0);
      else
        connection_4 <= connection_3;
      end if;
      if (delay_setting(5) = '1') then
        shift_register_5 <= connection_4 & shift_register_5(31 downto 1);
        connection_5     <= shift_register_5(0);
      else
        connection_5 <= connection_4;
      end if;
      if (delay_setting(6) = '1') then
        shift_register_6 <= connection_5 & shift_register_6(63 downto 1);
        connection_6     <= shift_register_6(0);
      else
        connection_6 <= connection_5;
      end if;
      if (delay_setting(7) = '1') then
        shift_register_7 <= connection_6 & shift_register_7(127 downto 1);
        data_output      <= shift_register_7(0);
      else
        data_output <= connection_6;
      end if;
    end if;
  end process;

end bcm_signal_delay_arc;

---

Author: M.Niegl

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