ddr2_mem_wr_data_fifo_16.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_wr_data_fifo_16.vhd,v $
--*  $Revision: 1.3.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 22:24:28 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: ddr2_mem_wr_data_fifo_16.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- 
-- Device: Virtex-4
-- Design Name: DDR2_V4
-- Description  :
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

library unisim;

use unisim.vcomponents.all;






entity ddr2_mem_wr_data_fifo_16 is
  port(
    clk0              : in  std_logic;
    clk90             : in  std_logic;
    rst               : in  std_logic;
    app_Wdf_data      : in  std_logic_vector(31 downto 0);
    app_mask_data     : in  std_logic_vector(3 downto 0);
    app_Wdf_WrEn      : in  std_logic;
    ctrl_Wdf_RdEn     : in  std_logic;
    Wdf_data          : out std_logic_vector(31 downto 0);
    mask_data         : out std_logic_vector(3 downto 0);
    wr_df_almost_full : out std_logic
    );
end entity;






architecture arc_wr_data_fifo_16 of ddr2_mem_wr_data_fifo_16 is


  component FIFO16
    generic (
      ALMOST_FULL_OFFSET      : bit_vector;
      ALMOST_EMPTY_OFFSET     : bit_vector;
      DATA_WIDTH              : integer;
      FIRST_WORD_FALL_THROUGH : boolean
      );
    port(
      ALMOSTEMPTY : out std_logic;
      ALMOSTFULL  : out std_logic;
      DO          : out std_logic_vector (31 downto 0);
      DOP         : out std_logic_vector (3 downto 0);
      EMPTY       : out std_logic;
      FULL        : out std_logic;
      RDCOUNT     : out std_logic_vector (11 downto 0);
      RDERR       : out std_logic;
      WRCOUNT     : out std_logic_vector (11 downto 0);
      WRERR       : out std_logic;
      DI          : in  std_logic_vector (31 downto 0);
      DIP         : in  std_logic_vector (3 downto 0);
      RDCLK       : in  std_logic;
      RDEN        : in  std_logic;
      RST         : in  std_logic;
      WRCLK       : in  std_logic;
      WREN        : in  std_logic
      );
  end component;

  signal ctrl_Wdf_RdEn_270 : std_logic;
  signal ctrl_Wdf_RdEn_90  : std_logic;

begin


  process(clk90)
  begin
    if clk90'event and clk90 = '0' then
      ctrl_Wdf_RdEn_270 <= ctrl_Wdf_RdEn;
    end if;
  end process;


  process(clk90)
  begin
    if clk90'event and clk90 = '1' then
      ctrl_Wdf_RdEn_90 <= ctrl_Wdf_RdEn_270;
    end if;
  end process;


  Wdf_1 : FIFO16
    generic map(
      ALMOST_FULL_OFFSET      => X"00F",
      ALMOST_EMPTY_OFFSET     => X"007",
      DATA_WIDTH              => 36,
      FIRST_WORD_Fall_THROUGH => false
      )
    port map (
      ALMOSTEMPTY => open,
      ALMOSTFULL  => wr_df_almost_full,
      DO          => Wdf_data (31 downto 0),
      DOP         => mask_data(3 downto 0),
      EMPTY       => open,
      FULL        => open,
      RDCOUNT     => open,
      RDERR       => open,
      WRCOUNT     => open,
      WRERR       => open,
      DI          => app_Wdf_data(31 downto 0),
      DIP         => app_mask_data(3 downto 0),
      RDCLK       => clk90,
      RDEN        => ctrl_Wdf_RdEn_90,
      RST         => rst,
      WRCLK       => clk0,
      WREN        => app_Wdf_WrEn
      );

end arc_wr_data_fifo_16;

---

Author: M.Niegl

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