mem_interface_top_controller_iobs_0.vhd

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top_controller_iobs_0.vhd,v $                                                  *
--*  $Revision: 1.3.2.3 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:43 $                                                    *
--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: mem_interface_top_controller_iobs_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- Device: Virtex-4
-- Design Name: DDR1_SDRAM
-- Description: Puts the memory control signals like address, bank address, row 
--              address strobe, column address strobe, write enable and clock enable in the IOBs.
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

library unisim;

use unisim.vcomponents.all;
use work.mem_interface_top_parameters_0.all;

entity mem_interface_top_controller_iobs_0 is
        port ( ctrl_ddr_address : in std_logic_vector((row_address - 1) downto 0);
               ctrl_ddr_ba      : in std_logic_vector((bank_address - 1) downto 0);
               ctrl_ddr_ras_L   : in std_logic;
               ctrl_ddr_cas_L   : in std_logic;
               ctrl_ddr_we_L    : in std_logic;    
               ctrl_ddr_cs_L    : in std_logic;
               ctrl_ddr_cke     : in std_logic;
               DDR_ADDRESS      : out std_logic_vector((row_address - 1) downto 0);
               DDR_BA           : out std_logic_vector((bank_address - 1) downto 0);
               DDR_RAS_L        : out std_logic;
               DDR_CAS_L        : out std_logic; 
               DDR_WE_L         : out std_logic;
               DDR_CKE          : out std_logic;  
               ddr_cs_L         : out std_logic
            );
end mem_interface_top_controller_iobs_0;

architecture arch of mem_interface_top_controller_iobs_0 is

component OBUF
        port ( I : in std_logic;
               O : out std_logic
             );
end component;

begin

r0: OBUF port map( I => ctrl_ddr_ras_L,
                   O => DDR_RAS_L
                 );

r1: OBUF port map( I => ctrl_ddr_cas_L,
                   O => DDR_CAS_L
                 );

r2: OBUF port map( I => ctrl_ddr_we_L,
                   O => DDR_WE_L
                 );


OBUF_cs0: OBUF port map( I => ctrl_ddr_cs_L,
                        O => ddr_cs_L
                       );


OBUF_cke0: OBUF port map( I => ctrl_ddr_cke,
                         O => DDR_CKE
                       );



OBUF_r0: OBUF port map( I => ctrl_ddr_address(0),
                         O => DDR_ADDRESS(0)
                       );


OBUF_r1: OBUF port map( I => ctrl_ddr_address(1),
                         O => DDR_ADDRESS(1)
                       );


OBUF_r2: OBUF port map( I => ctrl_ddr_address(2),
                         O => DDR_ADDRESS(2)
                       );


OBUF_r3: OBUF port map( I => ctrl_ddr_address(3),
                         O => DDR_ADDRESS(3)
                       );


OBUF_r4: OBUF port map( I => ctrl_ddr_address(4),
                         O => DDR_ADDRESS(4)
                       );


OBUF_r5: OBUF port map( I => ctrl_ddr_address(5),
                         O => DDR_ADDRESS(5)
                       );


OBUF_r6: OBUF port map( I => ctrl_ddr_address(6),
                         O => DDR_ADDRESS(6)
                       );


OBUF_r7: OBUF port map( I => ctrl_ddr_address(7),
                         O => DDR_ADDRESS(7)
                       );


OBUF_r8: OBUF port map( I => ctrl_ddr_address(8),
                         O => DDR_ADDRESS(8)
                       );


OBUF_r9: OBUF port map( I => ctrl_ddr_address(9),
                         O => DDR_ADDRESS(9)
                       );


OBUF_r10: OBUF port map( I => ctrl_ddr_address(10),
                         O => DDR_ADDRESS(10)
                       );


OBUF_r11: OBUF port map( I => ctrl_ddr_address(11),
                         O => DDR_ADDRESS(11)
                       );


OBUF_r12: OBUF port map( I => ctrl_ddr_address(12),
                         O => DDR_ADDRESS(12)
                       );




OBUF_b0: OBUF port map( I => ctrl_ddr_ba(0),
                         O => DDR_BA(0)
                       );


OBUF_b1: OBUF port map( I => ctrl_ddr_ba(1),
                         O => DDR_BA(1)
                       );



end arch;

---

Author: M.Niegl

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