rio_rxtx.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/rio_rxtx.vhd,v $                                                  *
--*  $Revision: 1.12.2.7 $                                                *
--*  $Name: dev $                                                    *
--*  $Author: mniegl $                                                  *
--*  $Date: 2008/11/03 17:57:48 $                                                    *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

use ieee.numeric_std.all;
library WORK;
use work.daq_header.all;

library unisim;

use unisim.vcomponents.all;





entity rio_rxtx is
  generic
    (
      USE_CHIPSCOPE : integer                       := 0;
      BOARD         : string                        := "SMall";
      SIMULATION_P  : integer                       := 0;  -- Set to 1 when using module in simulation
      XOR_PATTERN   : std_logic_vector(31 downto 0) := "11110000111100001111000011110000"
      );
  port
    (
      SET_SHIFT          : in  std_logic_vector(7 downto 0);
      CALIB              : in  std_logic;
      CAL1               : in  std_logic;
      CAL2               : in  std_logic;
      CHECK_OUT_1        : out std_logic;
      CHECK_OUT_2        : out std_logic;
      REFCLK             : in  std_logic;
      PARCLK             : in  std_logic;
      TX_SYSTEM_RESET_IN : in  std_logic;
      RX_SYSTEM_RESET_IN : in  std_logic;
      MGT0_RXLOCK_OUT    : out std_logic;
      MGT0_TXLOCK_OUT    : out std_logic;
      MGT1_RXLOCK_OUT    : out std_logic;
      MGT1_TXLOCK_OUT    : out std_logic;
      RX1N_IN_1          : in  std_logic;
      RX1P_IN_1          : in  std_logic;
      RX1N_IN_2          : in  std_logic;
      RX1P_IN_2          : in  std_logic;
      TX1N_OUT_1         : out std_logic;
      TX1P_OUT_1         : out std_logic;
      TX1N_OUT_2         : out std_logic;
      TX1P_OUT_2         : out std_logic;
      RXRECCLK1_OUT      : out std_logic;
      RX_READY_FLAG      : out std_logic;
      TX_READY_FLAG      : out std_logic;
      BC_2X              : out std_logic;
      RX_DATA_OUT_1      : out std_logic_vector(31 downto 0);
      RX_DATA_OUT_2      : out std_logic_vector(31 downto 0);
      MASK1              : out std_logic;
      MASK2              : out std_logic;
      VALID              : out std_logic
      );
end rio_rxtx;












architecture rio_rxtx_arc of rio_rxtx is

--*************************** Signal Declarations *****************************

  signal SHIFT1                     : integer range 0 to 7          := 0;
  signal SHIFT2                     : integer range 0 to 7          := 0;
  signal valid1                     : std_logic                     := '0';
  signal valid2                     : std_logic                     := '0';
  signal data_out_1                 : std_logic_vector(31 downto 0) := (others => '0');
  signal data_out_2                 : std_logic_vector(31 downto 0) := (others => '0');
  ----------------------- Clock Signals ---------------------------
  signal refclk1_i                  : std_logic;
  signal pulse_clk_p                : std_logic;
  signal usr_clk2_i                 : std_logic;
  signal mgt0_usr_clk2_i            : std_logic;
  signal mgt1_usr_clk2_i            : std_logic;
  signal drp_clk_in_i               : std_logic;
  ------------------------- MGT Wrapper Signals -----------------------------
  -------------------------- Calibration Block Ports -------------------------
  signal mgt0_active_i              : std_logic;
  signal mgt1_active_i              : std_logic;
  ---------------------------------- PLL Lock --------------------------------
  signal mgt0_rxlock_i              : std_logic;
  signal mgt0_txlock_i              : std_logic;
  signal mgt1_rxlock_i              : std_logic;
  signal mgt1_txlock_i              : std_logic;
--    -------------------- Receive Data Path and Control Ports -------------------
  signal mgt0_rxdata_i              : std_logic_vector(31 downto 0);
  signal mgt1_rxdata_i              : std_logic_vector(31 downto 0);
--  signal mgt0_rxdata_irec           : std_logic_vector(31 downto 0);
--  signal mgt1_rxdata_irec           : std_logic_vector(31 downto 0);
  signal mgt0_rxdata_iout           : std_logic_vector(31 downto 0);
  signal mgt1_rxdata_iout           : std_logic_vector(31 downto 0);
--  signal mgt0_rxdata_p              : std_logic_vector(31 downto 0);
--  signal mgt1_rxdata_p              : std_logic_vector(31 downto 0);
--  signal mgt0_rxdata_n              : std_logic_vector(31 downto 0);
--  signal mgt1_rxdata_n              : std_logic_vector(31 downto 0);
--  signal mgt0_rxdata_mux            : std_logic_vector(31 downto 0);
--  signal mgt1_rxdata_mux            : std_logic_vector(31 downto 0);
--    -------------------------------- Serial Ports ------------------------------
  signal mgt0_rx1n_i                : std_logic;
  signal mgt0_rx1p_i                : std_logic;
  signal mgt0_tx1n_i                : std_logic;
  signal mgt0_tx1p_i                : std_logic;
  signal mgt1_rx1n_i                : std_logic;
  signal mgt1_rx1p_i                : std_logic;
  signal mgt1_tx1n_i                : std_logic;
  signal mgt1_tx1p_i                : std_logic;
  ----------------------------------- Status ---------------------------------
  signal mgt0_rxstatus_i            : std_logic_vector(5 downto 0);
  signal mgt1_rxstatus_i            : std_logic_vector(5 downto 0);
  -------------------- Transmit Data Path and Control Ports ------------------
  signal mgt0_txdata_i              : std_logic_vector(31 downto 0);
  signal mgt1_txdata_i              : std_logic_vector(31 downto 0);
  signal xor_tx_rx                  : std_logic_vector(31 downto 0);
  signal xor_tx_rx1                 : std_logic_vector(31 downto 0);
  signal xor_tx_rx2                 : std_logic_vector(31 downto 0);
  -------------------------------- User Clocks -------------------------------
  signal mgt0_rxrecclk1_i           : std_logic;
  signal mgt0_rxrecclk2_i           : std_logic;
  signal mgt0_txoutclk1_i           : std_logic;
  signal mgt0_txoutclk2_i           : std_logic;
  signal mgt1_rxrecclk1_i           : std_logic;
  signal mgt1_rxrecclk2_i           : std_logic;
  signal mgt1_txoutclk1_i           : std_logic;
  signal mgt1_txoutclk2_i           : std_logic;
  signal mgt1_txusrclk2_i           : std_logic;
  ------------------------------- Global Signals -----------------------------
  signal debounce_tx_system_reset_r : std_logic_vector(0 to 3);
  signal debounce_rx_system_reset_r : std_logic_vector(0 to 3);
  signal rxbuferr_i                 : std_logic;
  signal rxlock_i                   : std_logic;
  signal rx_pmareset_c              : std_logic;
  signal rx_system_ready_i          : std_logic;
  signal rx_sync_i                  : std_logic;
  signal rxreset_c                  : std_logic;
  signal rx_system_reset_c          : std_logic;
  signal rx_system_reset_in_i       : std_logic;
  signal rx_usrclks_stable_i        : std_logic;
  signal rx_user_logic_reset_c      : std_logic;
  signal txbuferr_i                 : std_logic;
  signal tx_pmareset_c              : std_logic;
  signal tx_post_sync_reset_i       : std_logic;
  signal txreset_c                  : std_logic;
  signal tx_system_reset_c          : std_logic;
  signal tx_system_reset_in_i       : std_logic;
  signal tx_system_ready_i          : std_logic;
  signal tied_to_ground_i           : std_logic;
  signal tied_to_ground_vec_i       : std_logic_vector(63 downto 0);
  signal tied_to_vcc_i              : std_logic;
  signal txlock_i                   : std_logic;
  signal tx_sync_i                  : std_logic;
  signal tx_usrclks_stable_i        : std_logic;
  signal drp_reset_i                : std_logic;
  signal ch1                        : std_logic;
  signal ch2                        : std_logic;
  signal tgff1                      : std_logic;
  signal tgff2                      : std_logic;
  signal recclklatch0               : std_logic;
  signal recclklatch1               : std_logic;
  -------------------------------- Combus signals ----------------------------
  signal tile0_combusout_a_i        : std_logic_vector(15 downto 0);
  signal tile0_combusout_b_i        : std_logic_vector(15 downto 0);


--************************** Component Declarations ***************************


  component rio
    generic
      (
        SIMULATION_P     : integer                       := 0;
        TX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00000011101";
        TX_FD_EN_P       : std_logic                     := '1';
        RX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00000011101";
        RX_FD_EN_P       : std_logic                     := '1';
        TX_FD_WIDTH_P    : integer                       := 11;
        RX_FD_WIDTH_P    : integer                       := 11;
        MGT0_GT11_MODE_P : string                        := "B";
        MGT0_MGT_ID_P    : integer                       := 1
        );
    port
      (
        --__________________________________________________________________________
        --__________________________________________________________________________
        --MGT0  (X1Y0)
        -------------------------- Calibration Block Ports -------------------------
        MGT0_ACTIVE_OUT          : out std_logic;
        MGT0_DISABLE_IN          : in  std_logic;
        MGT0_DRP_RESET_IN        : in  std_logic;
        MGT0_RX_SIGNAL_DETECT_IN : in  std_logic;
        MGT0_TX_SIGNAL_DETECT_IN : in  std_logic;
        --------------------- Dynamic Reconfiguration Port (DRP) -------------------
        MGT0_DCLK_IN             : in  std_logic;
        -------------------------------- Global Ports ------------------------------
        MGT0_POWERDOWN_IN        : in  std_logic;
        MGT0_TXINHIBIT_IN        : in  std_logic;
        ---------------------------------- PLL Lock --------------------------------
        MGT0_RXLOCK_OUT          : out std_logic;
        MGT0_TXLOCK_OUT          : out std_logic;
        --------------------------- Polarity Control Ports -------------------------
        MGT0_RXPOLARITY_IN       : in  std_logic;
        MGT0_TXPOLARITY_IN       : in  std_logic;
        ---------------------------- Ports for Simulation --------------------------
        MGT0_COMBUSIN_IN         : in  std_logic_vector(15 downto 0);
        MGT0_COMBUSOUT_OUT       : out std_logic_vector(15 downto 0);
        -------------------- Receive Data Path and Control Ports -------------------
        MGT0_RXDATA_OUT          : out std_logic_vector(31 downto 0);
        ------------------------------ Reference Clocks ----------------------------
        MGT0_REFCLK1_IN          : in  std_logic;
        ----------------------------------- Resets ---------------------------------
        MGT0_RXPMARESET_IN       : in  std_logic;
        MGT0_RXRESET_IN          : in  std_logic;
        MGT0_TXPMARESET_IN       : in  std_logic;
        MGT0_TXRESET_IN          : in  std_logic;
        -------------------------------- Serial Ports ------------------------------
        MGT0_RX1N_IN             : in  std_logic;
        MGT0_RX1P_IN             : in  std_logic;
        MGT0_TX1N_OUT            : out std_logic;
        MGT0_TX1P_OUT            : out std_logic;
        ----------------------------------- Status ---------------------------------
        MGT0_RXSTATUS_OUT        : out std_logic_vector(5 downto 0);
        ------------------------------ Synchronization -----------------------------
        MGT0_RXSYNC_IN           : in  std_logic;
        MGT0_TXSYNC_IN           : in  std_logic;
        -------------------- Transmit Data Path and Control Ports ------------------
        MGT0_TXDATA_IN           : in  std_logic_vector(31 downto 0);
        -------------------------------- User Clocks -------------------------------
        MGT0_RXRECCLK1_OUT       : out std_logic;
        MGT0_RXRECCLK2_OUT       : out std_logic;
        MGT0_RXUSRCLK2_IN        : in  std_logic;
        MGT0_TXOUTCLK1_OUT       : out std_logic;
        MGT0_TXOUTCLK2_OUT       : out std_logic;
        MGT0_TXUSRCLK2_IN        : in  std_logic
        );
  end component;


  component GT11_INIT_TX
    generic
      (
        C_SIMULATION : integer := 0
        );
    port
      (
        CLK           : in  std_logic;
        START_INIT    : in  std_logic;
        LOCK          : in  std_logic;
        USRCLK_STABLE : in  std_logic;
        PCS_ERROR     : in  std_logic;
        PMA_RESET     : out std_logic;
        SYNC          : out std_logic;
        PCS_RESET     : out std_logic;
        READY         : out std_logic

        );
  end component;


  component GT11_INIT_RX
    generic
      (
        C_SIMULATION : integer := 0
        );
    port
      (
        CLK           : in  std_logic;
        START_INIT    : in  std_logic;
        LOCK          : in  std_logic;
        USRCLK_STABLE : in  std_logic;
        PCS_ERROR     : in  std_logic;
        PMA_RESET     : out std_logic;
        SYNC          : out std_logic;
        PCS_RESET     : out std_logic;
        READY         : out std_logic
        );
  end component;


--*************************************************************************
--                                main code
--*************************************************************************

begin

  --  Static signal Assignments    
  tied_to_ground_i     <= '0';
  tied_to_ground_vec_i <= (others => '0');
  tied_to_vcc_i        <= '1';
  --  Output Assignments    
  MGT0_TXLOCK_OUT      <= mgt0_txlock_i;
  MGT0_RXLOCK_OUT      <= mgt0_rxlock_i;
  MGT1_TXLOCK_OUT      <= mgt1_txlock_i;
  MGT1_RXLOCK_OUT      <= mgt1_rxlock_i;
  TX_READY_FLAG        <= tx_system_ready_i;
  RX_READY_FLAG        <= rx_system_ready_i;
  RXRECCLK1_OUT        <= mgt0_rxrecclk1_i;
  TX1N_OUT_1           <= mgt0_tx1n_i;
  TX1P_OUT_1           <= mgt0_tx1p_i;
  TX1N_OUT_2           <= mgt1_tx1n_i;
  TX1P_OUT_2           <= mgt1_tx1p_i;
  BC_2X                <= usr_clk2_i;
  RX_DATA_OUT_1        <= data_out_1;
  RX_DATA_OUT_2        <= data_out_2;
  CHECK_OUT_1          <= or_check(data_out_1);
  CHECK_OUT_2          <= or_check(data_out_2);
  --  Input Assignments
  refclk1_i            <= REFCLK;
  usr_clk2_i           <= PARCLK;
  rx_system_reset_in_i <= RX_SYSTEM_RESET_IN;
  tx_system_reset_in_i <= TX_SYSTEM_RESET_IN;
  mgt0_rx1n_i          <= RX1N_IN_1;
  mgt0_rx1p_i          <= RX1P_IN_1;
  mgt1_rx1n_i          <= RX1N_IN_2;
  mgt1_rx1p_i          <= RX1P_IN_2;
  mgt0_txdata_i        <= XOR_PATTERN;
  mgt1_txdata_i        <= XOR_PATTERN;

--      man_pattern_adj_small : if BOARD = "SMall" generate
--
--               --  internal XOR to remove transitions
--      man_shift_set : process(usr_clk2_i,SET_SHIFT)
--               begin
--                      if usr_clk2_i'event and usr_clk2_i = '1' then
--                              for i in 0 to 7 loop
--                                      if SET_SHIFT(i) = '1' then
--                                              SHIFT <= i;
--                                      end if;
--                              end loop;
--                      end if;
--              end process man_shift_set;
--      
--               xor_tx_rx                                                      <=               xrol(mgt0_txdata_i,SHIFT);
--               data_out_1                                                     <=               mgt0_rxdata_i xor xor_tx_rx when rising_edge(usr_clk2_i);
--               data_out_2                                                     <=               mgt1_rxdata_i xor xor_tx_rx when rising_edge(usr_clk2_i);
--               
--               MASK1 <= '1';
--               MASK2 <= '1';
--               VALID <= '1';
--
--      end generate man_pattern_adj_small;

--      auto_pattern_adj_big : if BOARD = "BIG" generate


  auto_shift_set1 : process(mgt0_usr_clk2_i)
  begin
    if mgt0_usr_clk2_i'event and mgt0_usr_clk2_i = '1' then
      if (TX_SYSTEM_RESET_IN or RX_SYSTEM_RESET_IN) = '1' then
        valid1     <= '0';
        SHIFT1     <= 0;
        tgff1      <= '0';
        MASK1      <= '0';
        xor_tx_rx1 <= mgt0_txdata_i;
      else
        if (CALIB or CAL1) = '1' then
          if valid1 = '0' then
            if ch1 = '1' then
              if tgff1 = '0' then
                tgff1      <= '1';
                xor_tx_rx1 <= xor_tx_rx1(30 downto 0) & xor_tx_rx1(31);
                --SHIFT1 <= SHIFT1 + 1;
              else
                tgff1 <= '0';
              end if;
            else
              --SHIFT1 <= SHIFT1;
              valid1 <= '1';
              MASK1  <= '1';
            end if;
          end if;
        end if;
      end if;
    end if;
  end process auto_shift_set1;


  auto_shift_set2 : process(mgt1_usr_clk2_i)
  begin
    if mgt1_usr_clk2_i'event and mgt1_usr_clk2_i = '1' then
      if (TX_SYSTEM_RESET_IN or RX_SYSTEM_RESET_IN) = '1' then
        valid2     <= '0';
        SHIFT2     <= 0;
        tgff2      <= '0';
        MASK2      <= '0';
        xor_tx_rx2 <= mgt1_txdata_i;
      else
        if (CALIB or CAL2) = '1' then
          if valid2 = '0' then
            if ch2 = '1' then
              if tgff2 = '0' then
                tgff2      <= '1';
                xor_tx_rx2 <= xor_tx_rx2(30 downto 0) & xor_tx_rx2(31);
                --SHIFT2 <= SHIFT2 + 1;
              else
                tgff2 <= '0';
              end if;
            else
              --SHIFT2 <= SHIFT2;
              valid2 <= '1';
              MASK2  <= '1';
            end if;
          end if;
        end if;
      end if;
    end if;
  end process auto_shift_set2;

  VALID <= valid1 and valid2;

--               mgt0_txdata_i_bit <= to_bitvector(mgt0_txdata_i);
--               mgt1_txdata_i_bit <= to_bitvector(mgt1_txdata_i);

--               xor_tx_rx1                                                     <=               to_stdlogicvector(mgt0_txdata_i_bit rol SHIFT1) when rising_edge(usr_clk2_i);--xrol(mgt0_txdata_i,SHIFT1);
--               xor_tx_rx2                                                     <=               to_stdlogicvector(mgt1_txdata_i_bit rol SHIFT2) when rising_edge(usr_clk2_i);--xrol(mgt1_txdata_i,SHIFT2);
--               valid1 <= '1' when or_check(data_out_1) = '1' else '0';
--               valid2 <= '1' when or_check(data_out_2) = '1' else '0';
  ch1        <= or_check(data_out_1) when rising_edge(mgt0_usr_clk2_i);
  ch2        <= or_check(data_out_2) when rising_edge(mgt1_usr_clk2_i);
  data_out_1 <= mgt0_rxdata_iout xor xor_tx_rx1;
  data_out_2 <= mgt1_rxdata_iout xor xor_tx_rx2;

--      end generate auto_pattern_adj_big;

  mgt0_rxdata_iout <= mgt0_rxdata_i when rising_edge(mgt0_rxrecclk1_i);  -- in flop
  mgt1_rxdata_iout <= mgt1_rxdata_i when rising_edge(mgt1_rxrecclk1_i);  -- in flop
--  mgt0_rxdata_irec <= mgt0_rxdata_i when rising_edge(mgt0_rxrecclk1_i);  -- in flop
--  mgt1_rxdata_irec <= mgt1_rxdata_i when rising_edge(mgt1_rxrecclk1_i);  -- in flop

--  recclklatch0 <= mgt0_rxrecclk1_i when rising_edge(mgt0_usr_clk2_i);  -- latch rx clk
--  recclklatch1 <= mgt1_rxrecclk1_i when rising_edge(mgt1_usr_clk2_i);

--  mgt0_rxdata_p <= mgt0_rxdata_irec when rising_edge(mgt0_usr_clk2_i);  -- latch data on ris edge
--  mgt1_rxdata_p <= mgt1_rxdata_irec when rising_edge(mgt1_usr_clk2_i);

--  mgt0_rxdata_n <= mgt0_rxdata_irec when falling_edge(mgt0_usr_clk2_i);  -- latch data on fal edge
--  mgt1_rxdata_n <= mgt1_rxdata_irec when falling_edge(mgt1_usr_clk2_i);

--  mgt0_rxdata_mux <= mgt0_rxdata_p when recclklatch0 = '0' else mgt0_rxdata_n;  -- mux ris & fal edge
--  mgt1_rxdata_mux <= mgt1_rxdata_p when recclklatch1 = '0' else mgt1_rxdata_n;

--  mgt0_rxdata_iout <= mgt0_rxdata_mux when rising_edge(mgt0_usr_clk2_i);  --out flop
--  mgt1_rxdata_iout <= mgt1_rxdata_mux when rising_edge(mgt1_usr_clk2_i);


  MGT0_USRCLK2_BUF : BUFR
    port map (
      CLR => '0' ,
      CE  => '1' ,
      O   => mgt0_usr_clk2_i,
      I   => mgt0_txoutclk1_i
      );        


  MGT1_USRCLK2_BUF : BUFR
    port map (
      CLR => '0' ,
      CE  => '1' ,
      O   => mgt1_usr_clk2_i,
      I   => mgt1_txoutclk1_i
      );

  drp_clk_in_i <= usr_clk2_i;

--  -- Buffer the DRP Clock
--  drp_clk_in_bufg_i : BUFG
--    port map
--    (
--      I => usr_clk2_i,
--      O => drp_clk_in_i
--      );


  tx_res : process(drp_clk_in_i)
  begin
    if(drp_clk_in_i'event and drp_clk_in_i = '1') then
      debounce_tx_system_reset_r <= tx_system_reset_in_i & debounce_tx_system_reset_r(0 to 2);
    end if;
  end process tx_res;

  tx_system_reset_c <= debounce_tx_system_reset_r(0) and
                       debounce_tx_system_reset_r(1) and
                       debounce_tx_system_reset_r(2) and
                       debounce_tx_system_reset_r(3);


  rx_res : process(drp_clk_in_i)
  begin
    if(drp_clk_in_i'event and drp_clk_in_i = '1') then
      debounce_rx_system_reset_r <= rx_system_reset_in_i & debounce_rx_system_reset_r(0 to 2);
    end if;
  end process rx_res;

  rx_system_reset_c <= debounce_rx_system_reset_r(0) and
                       debounce_rx_system_reset_r(1) and
                       debounce_rx_system_reset_r(2) and
                       debounce_rx_system_reset_r(3);

  -- AND all the txlock signals together as an input to the GT11_INIT module
  txlock_i   <= mgt0_txlock_i;          -- and mgt1_txlock_i;
  txbuferr_i <= tied_to_ground_i;


  -- AND all the rxlock signals together as an input to the GT11_INIT module
  rxlock_i   <= mgt0_rxlock_i;          -- and mgt1_rxlock_i;
  rxbuferr_i <= tied_to_ground_i;

  -- tx_user_logic_reset_c signal for resetting the tx user logic
  --tx_user_logic_reset_c   <=  not tx_system_ready_i;
  tx_usrclks_stable_i <= tied_to_vcc_i;


  -- rx_user_logic_reset_c signal for resetting the tx user logic
  --rx_user_logic_reset_c   <=  not rx_system_ready_i;
  rx_usrclks_stable_i <= tied_to_vcc_i;

  ----------------------- Instantiate an GT11_INIT module -------------------


  gt11_init_tx_i : GT11_INIT_TX
    generic map
    (
      C_SIMULATION => SIMULATION_P
      )
    port map
    (
      CLK           => drp_clk_in_i,
      START_INIT    => tx_system_reset_c ,
      USRCLK_STABLE => tx_usrclks_stable_i,
      LOCK          => txlock_i,
      PCS_ERROR     => txbuferr_i,
      PMA_RESET     => tx_pmareset_c,
      PCS_RESET     => txreset_c,
      SYNC          => tx_sync_i,
      READY         => tx_system_ready_i 
      );



  gt11_init_rx_i : GT11_INIT_RX
    generic map
    (
      C_SIMULATION => 0
      )
    port map
    (
      CLK           => drp_clk_in_i,
      START_INIT    => rx_system_reset_c ,
      USRCLK_STABLE => rx_usrclks_stable_i,
      LOCK          => rxlock_i,
      PCS_ERROR     => rxbuferr_i,
      PMA_RESET     => rx_pmareset_c,
      PCS_RESET     => rxreset_c,
      SYNC          => rx_sync_i,
      READY         => rx_system_ready_i 
      );

  drp_reset_i <= tx_system_reset_in_i or rx_system_reset_in_i;

--*************************** Active MGT Instantiation ************************


  rio1 : rio
    generic map
    (
      SIMULATION_P     => SIMULATION_P,
      MGT0_GT11_MODE_P => "A",
      MGT0_MGT_ID_P    => 0
      )
    port map
    (
      --_____________________________________________________________________
      --_____________________________________________________________________
      --MGT0   (X1Y0)
      -------------------------- Calibration Block Ports -------------------------
      MGT0_ACTIVE_OUT          => mgt0_active_i,
      MGT0_DISABLE_IN          => tied_to_ground_i,
      MGT0_DRP_RESET_IN        => drp_reset_i,
      MGT0_RX_SIGNAL_DETECT_IN => tied_to_vcc_i,
      MGT0_TX_SIGNAL_DETECT_IN => tied_to_vcc_i,
      --------------------- Dynamic Reconfiguration Port (DRP) -------------------
      MGT0_DCLK_IN             => drp_clk_in_i,
      -------------------------------- Global Ports ------------------------------
      MGT0_POWERDOWN_IN        => tied_to_ground_i,
      MGT0_TXINHIBIT_IN        => tied_to_ground_i,
      ---------------------------------- PLL Lock --------------------------------
      MGT0_RXLOCK_OUT          => mgt0_rxlock_i,
      MGT0_TXLOCK_OUT          => mgt0_txlock_i,
      --------------------------- Polarity Control Ports -------------------------
      MGT0_RXPOLARITY_IN       => tied_to_ground_i,
      MGT0_TXPOLARITY_IN       => tied_to_ground_i,
      ---------------------------- Ports for Simulation --------------------------
      MGT0_COMBUSIN_IN         => tile0_combusout_a_i,
      MGT0_COMBUSOUT_OUT       => tile0_combusout_b_i,
      -------------------- Receive Data Path and Control Ports -------------------
      MGT0_RXDATA_OUT          => mgt0_rxdata_i,  --RX_DATA_OUT,
      ------------------------------ Reference Clocks ----------------------------
      MGT0_REFCLK1_IN           => refclk1_i,
      ----------------------------------- Resets ---------------------------------
      MGT0_RXPMARESET_IN       => rx_pmareset_c,
      MGT0_RXRESET_IN          => rxreset_c,
      MGT0_TXPMARESET_IN       => tx_pmareset_c,
      MGT0_TXRESET_IN          => txreset_c,
      -------------------------------- Serial Ports ------------------------------
      MGT0_RX1N_IN             => mgt0_rx1n_i,
      MGT0_RX1P_IN             => mgt0_rx1p_i,
      MGT0_TX1N_OUT            => mgt0_tx1n_i,
      MGT0_TX1P_OUT            => mgt0_tx1p_i,
      ----------------------------------- Status ---------------------------------
      MGT0_RXSTATUS_OUT        => mgt0_rxstatus_i,
      ------------------------------ Synchronization -----------------------------
      MGT0_RXSYNC_IN           => rx_sync_i,
      MGT0_TXSYNC_IN           => tx_sync_i,
      -------------------- Transmit Data Path and Control Ports ------------------
      MGT0_TXDATA_IN           => mgt0_txdata_i,
      -------------------------------- User Clocks -------------------------------
      MGT0_RXRECCLK1_OUT       => mgt0_rxrecclk1_i,
      MGT0_RXRECCLK2_OUT       => mgt0_rxrecclk2_i,
      MGT0_RXUSRCLK2_IN        => mgt0_usr_clk2_i,
      MGT0_TXOUTCLK1_OUT       => mgt0_txoutclk1_i,
      MGT0_TXOUTCLK2_OUT       => mgt0_txoutclk2_i,
      MGT0_TXUSRCLK2_IN        => mgt0_usr_clk2_i
      );


  rio2 : rio
    generic map
    (
      SIMULATION_P     => SIMULATION_P,
      MGT0_GT11_MODE_P => "B",
      MGT0_MGT_ID_P    => 1
      )
    port map
    (
      --_____________________________________________________________________
      --_____________________________________________________________________
      --MGT0   (X1Y0)
      -------------------------- Calibration Block Ports -------------------------
      MGT0_ACTIVE_OUT          => mgt1_active_i,
      MGT0_DISABLE_IN          => tied_to_ground_i,
      MGT0_DRP_RESET_IN        => drp_reset_i,
      MGT0_RX_SIGNAL_DETECT_IN => tied_to_vcc_i,
      MGT0_TX_SIGNAL_DETECT_IN => tied_to_vcc_i,
      --------------------- Dynamic Reconfiguration Port (DRP) -------------------
      MGT0_DCLK_IN             => drp_clk_in_i,
      -------------------------------- Global Ports ------------------------------
      MGT0_POWERDOWN_IN        => tied_to_ground_i,
      MGT0_TXINHIBIT_IN        => tied_to_ground_i,
      ---------------------------------- PLL Lock --------------------------------
      MGT0_RXLOCK_OUT          => mgt1_rxlock_i,
      MGT0_TXLOCK_OUT          => mgt1_txlock_i,
      --------------------------- Polarity Control Ports -------------------------
      MGT0_RXPOLARITY_IN       => tied_to_ground_i,
      MGT0_TXPOLARITY_IN       => tied_to_ground_i,
      ---------------------------- Ports for Simulation --------------------------
      MGT0_COMBUSIN_IN         => tile0_combusout_b_i,
      MGT0_COMBUSOUT_OUT       => tile0_combusout_a_i,
      -------------------- Receive Data Path and Control Ports -------------------
      MGT0_RXDATA_OUT          => mgt1_rxdata_i,  --RX_DATA_OUT,
      ------------------------------ Reference Clocks ----------------------------
      MGT0_REFCLK1_IN          => refclk1_i,
      ----------------------------------- Resets ---------------------------------
      MGT0_RXPMARESET_IN       => rx_pmareset_c,
      MGT0_RXRESET_IN          => rxreset_c,
      MGT0_TXPMARESET_IN       => tx_pmareset_c,
      MGT0_TXRESET_IN          => txreset_c,
      -------------------------------- Serial Ports ------------------------------
      MGT0_RX1N_IN             => mgt1_rx1n_i,
      MGT0_RX1P_IN             => mgt1_rx1p_i,
      MGT0_TX1N_OUT            => mgt1_tx1n_i,
      MGT0_TX1P_OUT            => mgt1_tx1p_i,
      ----------------------------------- Status ---------------------------------
      MGT0_RXSTATUS_OUT        => mgt1_rxstatus_i,
      ------------------------------ Synchronization -----------------------------
      MGT0_RXSYNC_IN           => rx_sync_i,
      MGT0_TXSYNC_IN           => tx_sync_i,
      -------------------- Transmit Data Path and Control Ports ------------------
      MGT0_TXDATA_IN           => mgt1_txdata_i,
      -------------------------------- User Clocks -------------------------------
      MGT0_RXRECCLK1_OUT       => mgt1_rxrecclk1_i,
      MGT0_RXRECCLK2_OUT       => mgt1_rxrecclk2_i,
      MGT0_RXUSRCLK2_IN        => mgt1_usr_clk2_i,
      MGT0_TXOUTCLK1_OUT       => mgt1_txoutclk1_i,
      MGT0_TXOUTCLK2_OUT       => mgt1_txoutclk2_i,
      MGT0_TXUSRCLK2_IN        => mgt1_usr_clk2_i
      );

end rio_rxtx_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012