ddr2_data_buffer.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_data_buffer.vhd,v $
--*  $Revision: 1.3.2.4 $                                          *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

library unisim;

use unisim.vcomponents.all;


entity ddr2_data_buffer is
  port (
    CLKA     : in  std_logic;
    CLKB     : in  std_logic;
    RESET    : in  std_logic;
    WEN      : in  std_logic;
    REN      : in  std_logic;
    EMPTY    : out std_logic;
    DATA_IN  : in  std_logic_vector (255 downto 0);
    DATA_OUT : out std_logic_vector (127 downto 0)
    );
end ddr2_data_buffer;


architecture ddr2_data_buffer_arc of ddr2_data_buffer is
----------------------------- signals -----------------------------
  signal addr_a : std_logic_vector(6 downto 0) := (others => '0');
  signal addr_b : std_logic_vector(5 downto 0) := (others => '0');

---------------------------- components -----------------------------

  component raw_buffer
    port (
      addra : in  std_logic_vector(6 downto 0);
      addrb : in  std_logic_vector(5 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dinb  : in  std_logic_vector(255 downto 0);
      douta : out std_logic_vector(127 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      web   : in  std_logic);
  end component;

---------------------------- main code ----------------------------
begin


  raw_data_buffer : raw_buffer
    port map (
      addra => addr_a,
      addrb => addr_b,
      clka  => CLKA,
      clkb  => CLKB,
      dinb  => DATA_IN,
      douta => DATA_OUT,
      ena   => REN ,
      enb   => '1' ,
      web   => WEN 
      );


  wr_addr_gen : process(CLKB)
  begin
    if CLKB'event and CLKB = '1' then
      if RESET = '1' then
        addr_b <= (others => '0');
      elsif WEN = '1' then
        addr_b <= addr_b + 1;
      else
        addr_b <= addr_b;
      end if;
    end if;
  end process wr_addr_gen;




  rd_addr_gen : process(CLKA)
    variable diff_stack_point : integer := 0;
  begin
    if CLKA'event and CLKA = '1' then
      if RESET = '1' then
        addr_a <= (others => '0');
      elsif REN = '1' then
        addr_a <= addr_a + 1;
      else
        addr_a <= addr_a;
        if addr_b >= addr_a then
          diff_stack_point := conv_integer(addr_b - addr_a);
          if diff_stack_point > 10 then
            EMPTY <= '0';
          else
            EMPTY <= '1';
          end if;
        else
          EMPTY <= '0';
        end if;
      end if;
    end if;
  end process rd_addr_gen;

end ddr2_data_buffer_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:03 2008 for BCM-AAA by  1.5.7.1-20081012