pmdelay.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/Attic/pmdelay.vhd,v $
--*  $Revision: 1.1.2.5 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *



--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;





entity pmdelay is
  
  generic (
    LAYOFF : integer range 0 to 254 := 10);

  port (
    CLK    : in  std_logic;
    RES    : in  std_logic;
    PM_IN  : in  std_logic;
    ORBIT  : in  std_logic;
    PM_OUT : out std_logic
    );

end pmdelay;








architecture pmdelay_arc of pmdelay is


  component edge
    port(
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic
      );
  end component;

  signal pm_i    : std_logic              := '0';
  signal orbit_i : std_logic              := '0';
  signal inhib_n : std_logic              := '1';
  signal cnt     : integer range 0 to 255 := 255;

begin  -- pmdelay_arc


  pulse_1 : edge
    port map(
      CLK   => CLK ,
      A     => PM_IN ,
      PULSE => pm_i
      );


  pulse_2 : edge
    port map(
      CLK   => CLK ,
      A     => ORBIT ,
      PULSE => orbit_i
      );





  monoflop : process (CLK, RES)
  begin  -- process monoflop
    if RES = '1' then                   -- asynchronous reset (active high)
      PM_OUT  <= '0';
      inhib_n <= '1';
      cnt     <= 255;
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      
      if (pm_i and inhib_n) = '1' then
        cnt     <= 0;
        inhib_n <= '0';
      end if;

      if (inhib_n = '0') and (orbit_i = '1') then
        cnt <= cnt + 1;
      end if;

      if cnt = LAYOFF then
        PM_OUT  <= '1';
        inhib_n <= '1';
        cnt     <= 255;
      else
        PM_OUT <= '0';
      end if;
      
    end if;
  end process monoflop;

end pmdelay_arc;

---

Author: M.Niegl

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