proc_data_emul.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/proc_data_emul.vhd,v $
--*  $Revision: 1.3.2.3 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;




entity proc_data_emul is
  
  port (
    CLK   : in  std_logic;
    RESET : in  std_logic;
    EN    : in  std_logic;
    CH1   : out std_logic_vector(23 downto 0);
    CH2   : out std_logic_vector(23 downto 0);
    CH3   : out std_logic_vector(23 downto 0);
    CH4   : out std_logic_vector(23 downto 0);
    CH5   : out std_logic_vector(23 downto 0);
    CH6   : out std_logic_vector(23 downto 0);
    CH7   : out std_logic_vector(23 downto 0);
    CH8   : out std_logic_vector(23 downto 0)
    );

end proc_data_emul;




architecture proc_data_emul_arc of proc_data_emul is

--  component LFSR14_23A3
--    port (
--      clock : in  std_logic;
--      en    : in  std_logic;
--      q     : out std_logic_vector(13 downto 0)
--      );
--  end component;


  component loop_cnt_sh
    port (
      CLK   : in  std_logic;
      EN    : in  std_logic;
      RESET : in  std_logic;
      Y     : out std_logic_vector(5 downto 0));
  end component;

  type   datarr is array (1 to 8) of std_logic_vector(23 downto 0);
  type   datarr_l is array (1 to 8) of std_logic_vector(5 downto 0);
  type   datarr_s is array (1 to 8) of std_logic_vector(4 downto 0);
  signal data_i    : datarr;
  signal data_il   : datarr_l;
  signal data_is   : datarr_s;
  signal data_il_n : datarr_l;
  signal data_is_n : datarr_s;
  
begin  -- proc_data_emul_arc

  CH1 <= data_i(1);
  CH2 <= data_i(2);
  CH3 <= data_i(3);
  CH4 <= data_i(4);
  CH5 <= data_i(5);
  CH6 <= data_i(6);
  CH7 <= data_i(7);
  CH8 <= data_i(8);

  data_gen : for I in 1 to 8 generate

--    lfsr_data : LFSR14_23A3
--      port map (
--        clock          => CLK,
--        en             => EN,
--        q(4 downto 0)  => data_is(I),
--        q(13 downto 5) => open
--        );

    data_is(I) <= "11111";

    cnt_data : loop_cnt_sh
      port map (
        CLK   => CLK ,
        EN    => EN ,
        RESET => RESET ,
        Y     => data_il (I)
        );

    data_il_n(I) <= not data_il(I);
    data_is_n(I) <= not data_is(I);
    data_i(I)    <= '1' & data_il(I) & data_is(I) & '1' & data_il_n(I) & data_is_n(I);
    
  end generate data_gen;
  
end proc_data_emul_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012