raw_data_emul.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/raw_data_emul.vhd,v $
--*  $Revision: 1.5.2.3 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
library work;
use work.main_components.all;





entity raw_data_emul is

  generic (
    CONF : bit_vector(1 to 8) := "10101010"
    );
  port (
    CLK   : in  std_logic;
    RESET : in  std_logic;
    EN    : in  std_logic;
    CH1   : out std_logic_vector(31 downto 0);
    CH2   : out std_logic_vector(31 downto 0);
    CH3   : out std_logic_vector(31 downto 0);
    CH4   : out std_logic_vector(31 downto 0);
    CH5   : out std_logic_vector(31 downto 0);
    CH6   : out std_logic_vector(31 downto 0);
    CH7   : out std_logic_vector(31 downto 0);
    CH8   : out std_logic_vector(31 downto 0)
    );

end raw_data_emul;




architecture raw_data_emul_arc of raw_data_emul is


  component LFSR14_23A3
    port (
      clock : in  std_logic;
      en    : in  std_logic;
      q     : out std_logic_vector(13 downto 0)
      );
  end component;


  component loop_cnt
    port (
      CLK   : in  std_logic;
      RESET : in  std_logic;
      EN    : in  std_logic;
      Y     : out std_logic_vector(31 downto 0));
  end component;

  type   datarr is array (1 to 8) of std_logic_vector(31 downto 0);
  type   datarr_s is array (1 to 8) of std_logic_vector(13 downto 0);
  signal data_i  : datarr;
  signal data_is : datarr_s;
  
begin  -- raw_data_emul_arc

  CH1 <= data_i(1);
  CH2 <= data_i(2);
  CH3 <= data_i(3);
  CH4 <= data_i(4);
  CH5 <= data_i(5);
  CH6 <= data_i(6);
  CH7 <= data_i(7);
  CH8 <= data_i(8);

  counter_data : for I in 1 to 8 generate

    CHSEL : if CONF(I) = '1' generate

      data_gen : loop_cnt
        port map (
          CLK   => CLK,
          RESET => RESET,
          EN    => EN,
          Y     => data_i (I));

    end generate CHSEL;
    
  end generate counter_data;

  lfsr_data : for J in 1 to 8 generate

    CHSEL2 : if CONF(J) = '0' generate

      data_gen2 : LFSR14_23A3
        port map (
          clock => CLK,
          en    => EN,
          q     => data_is(J));

      data_i(J) <= gnd_vec_long(31 downto 20) & data_is(J) & gnd_vec_long(5 downto 0) when rising_edge(CLK);
      
    end generate CHSEL2;
    
  end generate lfsr_data;

end raw_data_emul_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012