00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/sata/sata_gt11_init_rx.vhd,v $
00015 --* $Revision: 1.3.2.5 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 23:30:24 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023 -------------------------------------------------------------------------------
00024 --$Date: 2008/11/03 23:30:24 $
00025 --$RCSfile: sata_gt11_init_rx.vhd,v $
00026 --$Revision: 1.3.2.5 $
00027 --------------------------------------------------------------------------------
00028 -- ____ ____
00029 -- / /\/ /
00030 -- /___/ \ / Vendor: Xilinx
00031 -- \ \ \/ Version : 1.4
00032 -- \ \ Application : RocketIO Wizard
00033 -- / / Filename : gt11_init_rx.vhd
00034 -- /___/ /\ Timestamp :
00035 -- \ \ / \
00036 -- \___\/\___\
00037 --
00038 --
00039 -- Module GT11_INIT_RX
00040 -- Generated by Xilinx RocketIO Wizard
00041
00042
00043 library ieee;
00044
00045 use ieee.std_logic_1164.all;
00046
00047 use ieee.numeric_std.all;
00048 -- synopsys translate_off
00049
00050 library unisim;
00051
00052 use unisim.vcomponents.all;
00053 -- synopsys translate_on
00054
00055 --***********************************Entity Declaration*******************************
00056
00057
00058
00059 entity sata_GT11_INIT_RX is
00060 generic (
00061 C_SIMULATION : := 0
00062 );
00063 port
00064 (
00065 CLK : in ;
00066 START_INIT : in ;
00067 LOCK : in ;
00068 USRCLK_STABLE : in ;
00069 PCS_ERROR : in ;
00070 PMA_RESET : out ;
00071 SYNC : out ;
00072 PCS_RESET : out ;
00073 READY : out
00074 );
00075 end sata_GT11_INIT_RX;
00076
00077
00078
00079 architecture rtl of sata_GT11_INIT_RX is
00080
00081 --********************************Parameter Declarations**********************
00082 ------------------------------------------------------------------------------
00083 -- Delays - these numbers are defined by the number of USRCLK needed in each
00084 -- state for each reset. Refer to the User Guide on the block
00085 -- diagrams on the reset and the required delay.
00086 ------------------------------------------------------------------------------
00087 constant C_DELAY_PMA_RESET : (2 downto 0) := "011"; --3
00088 constant C_DELAY_SYNC : (7 downto 0) := "01000000"; --64
00089 constant C_DELAY_PCS_RESET : (2 downto 0) := "011"; --3
00090 constant C_DELAY_LOCK : (4 downto 0) := "10000"; --16
00091 constant C_DELAY_WAIT_PCS : (3 downto 0) := "0101"; --5
00092 constant C_DELAY_WAIT_READY : (7 downto 0) := "01000000"; --64
00093 constant C_PCS_ERROR_COUNT : (4 downto 0) := "10000"; --16
00094 ------------------------------------------------------------------------------
00095
00096 constant C_RESET : (7 downto 0) := "00000001";
00097
00098 constant C_PMA_RESET : (7 downto 0) := "00000010";
00099
00100 constant C_WAIT_LOCK : (7 downto 0) := "00000100";
00101
00102 constant C_SYNC : (7 downto 0) := "00001000";
00103
00104 constant C_PCS_RESET : (7 downto 0) := "00010000";
00105
00106 constant C_WAIT_PCS : (7 downto 0) := "00100000";
00107
00108 constant C_ALMOST_READY : (7 downto 0) := "01000000";
00109
00110 constant C_READY : (7 downto 0) := "10000000";
00111 --*******************************Register Declarations************************
00112 signal reset_r : (1 downto 0);
00113 signal lock_r : ;
00114 signal lock_r2 : ;
00115 signal pcs_error_r1 : ;
00116 signal pcs_error_r2 : ;
00117 signal pma_reset_count_r : (2 downto 0);
00118 signal sync_count_r : (7 downto 0);
00119 signal pcs_reset_count_r : (2 downto 0);
00120 signal wait_pcs_count_r : (3 downto 0);
00121 signal pcs_error_count_r : (4 downto 0);
00122 signal wait_ready_count_r : (7 downto 0);
00123 signal init_state_r : (7 downto 0);
00124 signal init_next_state_r : (7 downto 0);
00125 signal init_fsm_name : (40*7 downto 0);
00126 signal init_fsm_wait_lock_check : ;
00127 --*******************************Wire Declarations****************************
00128 signal pma_reset_done_i : ;
00129 signal lock_pulse_i : ;
00130 signal stage_1_enable_i : ;
00131 signal stage_2_enable_i : ;
00132 signal stage_3_enable_i : ;
00133 signal lockupdate_ready_i : ;
00134 signal shift_register_1_enable_i : ;
00135 signal shift_register_2_enable_i : ;
00136 signal shift_register_3_enable_i : ;
00137 signal shift_register_0_d_i : ;
00138 signal shift_register_1_d_i : ;
00139 signal shift_register_2_d_i : ;
00140 signal shift_register_3_d_i : ;
00141 signal shift_register_0_q_i : ;
00142 signal shift_register_1_q_i : ;
00143 signal shift_register_2_q_i : ;
00144 signal shift_register_3_q_i : ;
00145 signal sync_done_i : ;
00146 signal pcs_reset_done_i : ;
00147 signal wait_pcs_done_i : ;
00148 signal pcs_error_count_done_i : ;
00149 signal wait_ready_done_i : ;
00150 signal tied_to_ground_i : ;
00151 signal tied_to_vcc_i : ;
00152 signal not_lock_i : ;
00153
00154 --**************************** Component Declarations ************************
00155
00156
00157 component FDE
00158 generic
00159 (
00160 INIT : := '0'
00161 );
00162 port
00163 (
00164 Q : out ;
00165 C : in ;
00166 CE : in ;
00167 D : in
00168 );
00169 end component;
00170
00171
00172 component SRL16E
00173 generic
00174 (
00175 INIT : bit_vector := X"0000"
00176 );
00177 port
00178 (
00179 Q : out ;
00180 A0 : in ;
00181 A1 : in ;
00182 A2 : in ;
00183 A3 : in ;
00184 CE : in ;
00185 CLK : in ;
00186 D : in
00187 );
00188 end component;
00189
00190
00191 component FDRE
00192 generic
00193 (
00194 INIT : := '0'
00195 );
00196 port
00197 (
00198 Q : out ;
00199 C : in ;
00200 CE : in ;
00201 D : in ;
00202 R : in
00203 );
00204 end component;
00205
00206 --**************************** Function Declaration ************************
00207
00208 function ExtendString (string_in : ;
00209 string_len : )
00210 return is
00211 variable string_out : (1 to string_len) := (others => ' ');
00212 begin
00213 if string_in'length > string_len then
00214 string_out := string_in(1 to string_len);
00215 else
00216 string_out(1 to string_in'length) := string_in;
00217 end if;
00218 return string_out;
00219 end ExtendString;
00220
00221 --*********************************Main Body of Code**************************
00222
00223 begin
00224 ------------------------------------------------------------------------------
00225 -- Static Assignments
00226 ------------------------------------------------------------------------------
00227 tied_to_ground_i <= '0';
00228 tied_to_vcc_i <= '1';
00229
00230
00231 process (CLK, START_INIT)
00232 begin
00233 if (START_INIT = '1') then
00234 reset_r <= "11";
00235 elsif (rising_edge(CLK)) then
00236 reset_r <= '0' & reset_r(1);
00237 end if;
00238 end process;
00239
00240
00241 process(CLK)
00242 begin
00243 if(CLK'event and CLK = '1') then
00244 if (reset_r(0) = '1') then
00245 lock_r <= '0';
00246 else
00247 lock_r <= LOCK;
00248 end if;
00249 end if;
00250 end process;
00251
00252
00253 process(CLK)
00254 begin
00255 if(CLK'event and CLK = '1') then
00256 if(reset_r(0) = '1') then
00257 pcs_error_r1 <= '0';
00258 else
00259 pcs_error_r1 <= PCS_ERROR;
00260 end if;
00261 end if;
00262 end process;
00263
00264 ------------------------------------------------------------------------------
00265 -- Ready, PMA and PCS reset signals
00266 ------------------------------------------------------------------------------
00267 PMA_RESET <= '1' when (init_state_r = C_PMA_RESET) else '0';
00268 SYNC <= '1' when (init_state_r = C_SYNC) else '0';
00269 PCS_RESET <= '1' when (init_state_r = C_PCS_RESET) else '0';
00270 READY <= '1' when (init_state_r = C_READY) else '0';
00271
00272
00273 process(CLK)
00274 begin
00275 if(CLK'event and CLK = '1') then
00276 if(init_state_r /= C_PMA_RESET) then
00277 pma_reset_count_r <= C_DELAY_PMA_RESET;
00278 else
00279 pma_reset_count_r <= pma_reset_count_r - 1;
00280 end if;
00281 end if;
00282 end process;
00283
00284 pma_reset_done_i <= '1' when (pma_reset_count_r = 1) else '0';
00285
00286 for_simulation : if (C_SIMULATION /= 0) generate
00287 begin
00288 lockupdate_ready_i <= tied_to_vcc_i;
00289 end generate for_simulation;
00290
00291 for_hardware : if (C_SIMULATION = 0) generate
00292 begin
00293
00294
00295
00296
00297
00298
00299
00300
00301
00302
00303 process(CLK)
00304 begin
00305 if(CLK'event and CLK = '1') then
00306 if (reset_r(0) = '1') then
00307 lock_r2 <= '0';
00308 else
00309 lock_r2 <= lock_r;
00310 end if;
00311 end if;
00312 end process;
00313
00314 lock_pulse_i <= lock_r and not lock_r2;
00315
00316 shift_register_0_d_i <= lock_r and (lock_pulse_i or stage_1_enable_i);
00317
00318
00319 shift_register_0 : SRL16E
00320 port map
00321 (
00322 Q => shift_register_0_q_i,
00323 A0 => tied_to_ground_i,
00324 A1 => tied_to_vcc_i,
00325 A2 => tied_to_vcc_i,
00326 A3 => tied_to_vcc_i,
00327 CE => tied_to_vcc_i,
00328 CLK => CLK ,
00329 D => shift_register_0_d_i
00330 );
00331
00332
00333 flop_stage_0 : FDE
00334 port map
00335 (
00336 Q => stage_1_enable_i,
00337 C => CLK ,
00338 CE => tied_to_vcc_i,
00339 D => shift_register_0_q_i
00340 );
00341
00342 shift_register_1_d_i <= lock_r and (lock_pulse_i or
00343 (stage_1_enable_i and stage_2_enable_i));
00344 shift_register_1_enable_i <= not lock_r2 or stage_1_enable_i;
00345
00346
00347 shift_register_1 : SRL16E
00348 port map
00349 (
00350 Q => shift_register_1_q_i,
00351 A0 => tied_to_ground_i,
00352 A1 => tied_to_vcc_i,
00353 A2 => tied_to_vcc_i,
00354 A3 => tied_to_vcc_i,
00355 CE => shift_register_1_enable_i,
00356 CLK => CLK ,
00357 D => shift_register_1_d_i
00358 );
00359
00360
00361 flop_stage_1 : FDE
00362 port map
00363 (
00364 Q => stage_2_enable_i,
00365 C => CLK ,
00366 CE => shift_register_1_enable_i,
00367 D => shift_register_1_q_i
00368 );
00369
00370 shift_register_2_d_i <= lock_r and (lock_pulse_i or
00371 (stage_1_enable_i and stage_2_enable_i and
00372 stage_3_enable_i));
00373
00374 shift_register_2_enable_i <= not lock_r2 or
00375 (stage_1_enable_i and stage_2_enable_i);
00376
00377
00378 shift_register_2 : SRL16E
00379 port map
00380 (
00381 Q => shift_register_2_q_i,
00382 A0 => tied_to_ground_i,
00383 A1 => tied_to_vcc_i,
00384 A2 => tied_to_vcc_i,
00385 A3 => tied_to_vcc_i,
00386 CE => shift_register_2_enable_i,
00387 CLK => CLK ,
00388 D => shift_register_2_d_i
00389 );
00390
00391
00392 flop_stage_2 : FDE
00393 port map
00394 (
00395 Q => stage_3_enable_i,
00396 C => CLK ,
00397 CE => shift_register_2_enable_i,
00398 D => shift_register_2_q_i
00399 );
00400
00401 shift_register_3_d_i <= lock_r and (lock_pulse_i or
00402 (stage_1_enable_i and stage_2_enable_i and
00403 stage_3_enable_i and lockupdate_ready_i));
00404
00405 shift_register_3_enable_i <= not lock_r2 or
00406 (stage_1_enable_i and stage_2_enable_i and
00407 stage_3_enable_i and not lockupdate_ready_i);
00408
00409
00410
00411
00412 shift_register_3 : SRL16E
00413 port map
00414 (
00415 Q => shift_register_3_q_i,
00416 A0 => tied_to_vcc_i,
00417 A1 => tied_to_vcc_i,
00418 A2 => tied_to_ground_i,
00419 A3 => tied_to_ground_i,
00420 CE => shift_register_3_enable_i,
00421 CLK => CLK ,
00422 D => shift_register_3_d_i
00423 );
00424
00425 not_lock_i <= not lock_r;
00426
00427
00428 flop_stage_3 : FDRE
00429 port map
00430 (
00431 Q => lockupdate_ready_i,
00432 C => CLK ,
00433 CE => shift_register_3_enable_i,
00434 D => shift_register_3_q_i,
00435 R => not_lock_i
00436 );
00437 end generate for_hardware;
00438
00439
00440 process(CLK)
00441 begin
00442 if(CLK'event and CLK = '1') then
00443 if(init_state_r /= C_SYNC) then
00444 sync_count_r <= C_DELAY_SYNC;
00445 else
00446 sync_count_r <= sync_count_r - 1;
00447 end if;
00448 end if;
00449 end process;
00450
00451 sync_done_i <= '1' when (sync_count_r = 1) else '0';
00452
00453
00454 process(CLK)
00455 begin
00456 if(CLK'event and CLK = '1') then
00457 if(init_state_r /= C_PCS_RESET) then
00458 pcs_reset_count_r <= C_DELAY_PCS_RESET;
00459 else
00460 pcs_reset_count_r <= pcs_reset_count_r - 1;
00461 end if;
00462 end if;
00463 end process;
00464
00465 pcs_reset_done_i <= '1' when (pcs_reset_count_r = 1) else '0';
00466
00467
00468 process(CLK)
00469 begin
00470 if(CLK'event and CLK = '1') then
00471 if(init_state_r /= C_WAIT_PCS) then
00472 wait_pcs_count_r <= C_DELAY_WAIT_PCS;
00473 else
00474 wait_pcs_count_r <= wait_pcs_count_r - 1;
00475 end if;
00476 end if;
00477 end process;
00478
00479 wait_pcs_done_i <= '1' when (wait_pcs_count_r = 1) else '0';
00480
00481
00482 process(CLK)
00483 begin
00484 if(CLK'event and CLK = '1') then
00485 if(init_state_r = C_PMA_RESET) then
00486 pcs_error_count_r <= C_PCS_ERROR_COUNT;
00487 elsif (((init_state_r = C_ALMOST_READY) or (init_state_r = C_READY)) and (pcs_error_r1 and lock_r) = '1') then
00488 pcs_error_count_r <= pcs_error_count_r - 1;
00489 end if;
00490 end if;
00491 end process;
00492
00493 pcs_error_count_done_i <= '1' when (pcs_error_count_r = 1) else '0';
00494
00495
00496 process(CLK)
00497 begin
00498 if(CLK'event and CLK = '1') then
00499 if((init_state_r /= C_ALMOST_READY) or (pcs_error_r1 = '1')) then
00500 wait_ready_count_r <= C_DELAY_WAIT_READY;
00501 elsif(pcs_error_r1 = '0') then
00502 wait_ready_count_r <= wait_ready_count_r - 1;
00503 end if;
00504 end if;
00505 end process;
00506
00507 wait_ready_done_i <= '1' when (wait_ready_count_r = 1) else '0';
00508
00509
00510 process (CLK)
00511 begin
00512 if (rising_edge(CLK)) then
00513 if (reset_r(0) = '1') then
00514 init_state_r <= C_RESET;
00515 else
00516 init_state_r <= init_next_state_r;
00517 end if;
00518 end if;
00519 end process;
00520
00521 init_fsm_wait_lock_check <= lock_r and USRCLK_STABLE and lockupdate_ready_i;
00522
00523
00524
00525
00526
00527
00528
00529
00530
00531
00532
00533
00534
00535
00536
00537
00538
00539
00540
00541
00542
00543
00544
00545
00546
00547
00548
00549
00550
00551
00552
00553
00554 process (reset_r(0), pma_reset_done_i, init_fsm_wait_lock_check, lock_r,
00555 sync_done_i, pcs_reset_done_i, wait_pcs_done_i, pcs_error_r1,
00556 pcs_error_count_done_i, wait_ready_done_i)
00557 variable init_fsm_name : (1 to 25);
00558 begin
00559 case init_state_r is
00560
00561 when C_RESET =>
00562
00563 if (reset_r(0) = '1') then
00564 init_next_state_r <= C_RESET;
00565 else
00566 init_next_state_r <= C_PMA_RESET;
00567 end if;
00568 init_fsm_name := ExtendString("C_RESET", 25);
00569
00570 when C_PMA_RESET =>
00571
00572 if (pma_reset_done_i = '1') then
00573 init_next_state_r <= C_WAIT_LOCK;
00574 else
00575 init_next_state_r <= C_PMA_RESET;
00576 end if;
00577 init_fsm_name := ExtendString("C_PMA_RESET", 25);
00578
00579 when C_WAIT_LOCK =>
00580
00581 if(init_fsm_wait_lock_check = '1') then
00582 init_next_state_r <= C_SYNC;
00583 else
00584 init_next_state_r <= C_WAIT_LOCK;
00585 end if;
00586 init_fsm_name := ExtendString("C_WAIT_LOCK", 25);
00587
00588 when C_SYNC =>
00589 if (lock_r = '1') then
00590 if (sync_done_i = '1') then
00591 init_next_state_r <= C_PCS_RESET;
00592 else
00593 init_next_state_r <= C_SYNC;
00594 end if;
00595 else
00596 init_next_state_r <= C_PMA_RESET; --C_WAIT_LOCK;
00597 end if;
00598 init_fsm_name := ExtendString("C_SYNC", 25);
00599
00600 when C_PCS_RESET =>
00601 if (lock_r = '1') then
00602 if (pcs_reset_done_i = '1') then
00603 init_next_state_r <= C_WAIT_PCS;
00604 else
00605 init_next_state_r <= C_PCS_RESET;
00606 end if;
00607 else
00608 init_next_state_r <= C_PMA_RESET; --C_WAIT_LOCK;
00609 end if;
00610 init_fsm_name := ExtendString("C_PCS_RESET", 25);
00611
00612 when C_WAIT_PCS =>
00613 if (lock_r = '1') then
00614 if (wait_pcs_done_i = '1') then
00615 init_next_state_r <= C_ALMOST_READY;
00616 else
00617 init_next_state_r <= C_WAIT_PCS;
00618 end if;
00619 else
00620 init_next_state_r <= C_PMA_RESET; --C_WAIT_LOCK;
00621 end if;
00622 init_fsm_name := ExtendString("C_WAIT_PCS", 25);
00623
00624 when C_ALMOST_READY =>
00625 if (lock_r = '0') then
00626 init_next_state_r <= C_PMA_RESET; --C_WAIT_LOCK;
00627 elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '0')) then
00628 init_next_state_r <= C_SYNC;
00629 elsif ((pcs_error_r1 = '1') and (pcs_error_count_done_i = '1')) then
00630 init_next_state_r <= C_PMA_RESET;
00631 elsif (wait_ready_done_i = '1') then
00632 init_next_state_r <= C_READY;
00633 else
00634 init_next_state_r <= C_ALMOST_READY;
00635 end if;
00636 init_fsm_name := ExtendString("C_ALMOST_READY", 25);
00637
00638 when C_READY =>
00639 if ((lock_r = '1') and (pcs_error_r1 = '0')) then
00640 init_next_state_r <= C_READY;
00641 elsif ((lock_r = '1') and (pcs_error_r1 = '1')) then
00642 init_next_state_r <= C_PCS_RESET;
00643 else
00644 init_next_state_r <= C_PMA_RESET; --C_WAIT_LOCK;
00645 end if;
00646 init_fsm_name := ExtendString("C_READY", 25);
00647
00648 when others =>
00649 init_next_state_r <= C_RESET;
00650 init_fsm_name := ExtendString("C_RESET", 25);
00651
00652 end case;
00653 end process;
00654
00655 end rtl;
00656