generic_shift_reg.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/Attic/generic_shift_reg.vhd,v $
--*  $Revision: 1.1.2.5 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *



--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;



entity generic_shift_reg is
  
  generic (
    WIDTH : positive range 1 to 255 := 1;
    DEPTH : positive range 1 to 255 := 1
    );
  port (
    CLK  : in  std_logic;
    RES  : in  std_logic;
    DIN  : in  std_logic_vector(WIDTH-1 downto 0);
    DOUT : out std_logic_vector(WIDTH-1 downto 0)
    );

end generic_shift_reg;



architecture generic_shift_reg_arc of generic_shift_reg is


  type reg_arr is array (WIDTH-1 downto 0) of std_logic_vector(DEPTH-1 downto 0);
  signal sreg : reg_arr                            := (others => (others => '0'));
  signal tmp  : std_logic_vector(DEPTH-1 downto 0) := (others => '0');

begin  -- generic_shift_reg_arc

  shift_reg_bank : for I in WIDTH-1 downto 0 generate

    DOUT(I) <= tmp(DEPTH-1);
    tmp     <= sreg(I);

    -- purpose: shift register
    -- type   : sequential
    -- inputs : CLK, RES, DIN
    -- outputs: sreg(I,DEPTH-1)
    shift_reg : process (CLK, RES)
      variable regvar : std_logic_vector(DEPTH-1 downto 0) := (others => '0');
    begin  -- process shift_reg
      if RES = '1' then                   -- asynchronous reset (active high)
        sreg(I) <= (others => '0');
        regvar  := (others => '0');
      elsif CLK'event and CLK = '1' then  -- rising clock edge
        regvar  := regvar(DEPTH-2 downto 0) & DIN(I);
        sreg(I) <= regvar;
      end if;
    end process shift_reg;
    
  end generate shift_reg_bank;

end generic_shift_reg_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012