mgt_clock_module.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rio/mgt_clock_module.vhd,v $
--*  $Revision: 1.4.2.5 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:48 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
--$Date: 2008/11/03 17:57:48 $
--$RCSfile: mgt_clock_module.vhd,v $
--$Revision: 1.4.2.5 $
--------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;
-- synopsys translate_off

library unisim;
use unisim.all;
-- synopsys translate_on

--******************************* Entity Declaration***************************












entity MGT_CLOCK_MODULE is
  port
    (
      ------------------- Input Differential Clocks from Pads -------------------
      UPPER_MGTCLK_PAD_N_IN : in  std_logic;
      UPPER_MGTCLK_PAD_P_IN : in  std_logic;
      ------------------------- Output Reference Clocks -------------------------
      REFCLK1_OUT           : out std_logic

      );
end MGT_CLOCK_MODULE;


architecture RTL of MGT_CLOCK_MODULE is

--**************************** Component Declarations ***************************


  component GT11CLK
    generic
      (
        REFCLKSEL    : string := "MGTCLK";
        SYNCLK1OUTEN : string := "ENABLE";
        SYNCLK2OUTEN : string := "DISABLE"
        );
    port
      (
        SYNCLK1OUT : out std_ulogic;
        SYNCLK2OUT : out std_ulogic;
        MGTCLKN    : in  std_ulogic;
        MGTCLKP    : in  std_ulogic;
        REFCLK     : in  std_ulogic;
        RXBCLK     : in  std_ulogic;
        SYNCLK1IN  : in  std_ulogic;
        SYNCLK2IN  : in  std_ulogic
        );
  end component;

--******************************* Beginning of Code****************************
  
begin

  ------------ GT11CLK_MGT Instantiations for upper reference clocks --------   


  upper_gt11clk_mgt_inst : GT11CLK
    generic map
    (
      SYNCLK1OUTEN => "ENABLE",
      SYNCLK2OUTEN => "DISABLE",
      REFCLKSEL    => "MGTCLK"
      )
    port map
    (
      MGTCLKN    => UPPER_MGTCLK_PAD_N_IN,
      MGTCLKP    => UPPER_MGTCLK_PAD_P_IN,
      REFCLK     => '0',
      RXBCLK     => '0',
      SYNCLK1IN  => '0',
      SYNCLK2IN  => '0',
      SYNCLK1OUT => REFCLK1_OUT,
      SYNCLK2OUT => open
      );

end RTL;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:05 2008 for BCM-AAA by  1.5.7.1-20081012