edge_fal.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/edge_fal.vhd,v $
--*  $Revision: 1.1.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;




entity edge_fal is
  port (CLK   : in  std_logic;
        A     : in  std_logic;
        PULSE : out std_logic);
end edge_fal;




architecture edge_fal_arc of edge_fal is
  signal latch1 : std_logic := '0';
  signal latch2 : std_logic := '0';
begin

  latches : process(CLK)
  begin
    if CLK'event and CLK = '1' then
      latch1 <= A;
      latch2 <= latch1;
    end if;
  end process latches;

  PULSE <= latch2 and (not latch1);

end edge_fal_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012