BCM-AAA: bcm_rod.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/rod/bcm_rod.vhd,v $
00015 --*  $Revision: 1.13.2.6 $                                         *
00016 --*  $Name: dev $                                              *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:48 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 library ieee;
00025 
00026 use ieee.std_logic_1164.all;
00027 
00028 use ieee.std_logic_arith.all;
00029 
00030 use ieee.std_logic_unsigned.all;
00031 
00032 
00033 
00034 
00035 
00036 
00037 entity bcm_rod is
00038   port (
00039     -- clocks and synchronus reset 
00040     CLK                     : in  std_logic;
00041     CLK_2X                  : in  std_logic;
00042     SCLR                    : in  std_logic;
00043     -- registers:
00044     rod_format_version      : in  std_logic_vector(31 downto 0) := X"03010001";
00045     rod_source_ID           : in  std_logic_vector(31 downto 0) := X"00810000";
00046     rod_run_number          : in  std_logic_vector(31 downto 0) := X"7fffffff";
00047     rod_CTP_trigger_type    : in  std_logic_vector(31 downto 0) := X"00000011";
00048     rod_detector_event_type : in  std_logic_vector(31 downto 0) := X"000000dd";
00049     -- data:
00050     data_input              : in  std_logic_vector(191 downto 0);
00051     data_lvl1id             : in  std_logic_vector(31 downto 0);
00052     data_input_valid        : in  std_logic;
00053     data_input_endoffrag    : in  std_logic;
00054     data_input_busy         : out std_logic;
00055     -- SLINK interface:
00056     hola_LFF                : in  std_logic;
00057     hola_LDOWN              : in  std_logic;
00058     hola_LRL                : in  std_logic_vector(3 downto 0);
00059     hola_CLK                : out std_logic;
00060     hola_UD                 : out std_logic_vector(31 downto 0);
00061     hola_URESET             : out std_logic;
00062     hola_UTEST              : out std_logic;
00063     hola_UCTRL              : out std_logic;
00064     hola_UWEN               : out std_logic;
00065     hola_UDW                : out std_logic_vector(1 downto 0)  := "00"
00066     );
00067 end bcm_rod;
00068 
00069 
00070 architecture bcm_rod_arc of bcm_rod is
00071 
00072 
00073   component bcm_rod_treadmil
00074     port (
00075       CLK_2X                : in  std_logic;
00076       SCLR                  : in  std_logic;
00077       data_input            : in  std_logic_vector(223 downto 0);
00078       data_input_valid      : in  std_logic;
00079       data_input_endoffrag  : in  std_logic;
00080       stop                  : in  std_logic;
00081       data_output           : out std_logic_vector(31 downto 0);
00082       data_output_valid     : out std_logic;
00083       data_output_endoffrag : out std_logic;
00084       busy                  : out std_logic;
00085       error                 : out std_logic
00086       );
00087   end component;
00088 
00089 
00090   component bcm_rod_ram is
00091     port (
00092       CLK                   : in  std_logic;
00093       CLK_2X                : in  std_logic;
00094       SCLR                  : in  std_logic;
00095       data_input            : in  std_logic_vector(31 downto 0);
00096       data_input_valid      : in  std_logic;
00097       data_input_endoffrag  : in  std_logic;
00098       stop                  : in  std_logic;
00099       data_output           : out std_logic_vector(31 downto 0);
00100       data_output_vld       : out std_logic;
00101       data_output_available : out std_logic;
00102       data_output_endoffrag : out std_logic;
00103       data_output_next      : in  std_logic;
00104       busy                  : out std_logic;
00105       write_error           : out std_logic;
00106       read_error            : out std_logic
00107       );
00108   end component;
00109 
00110 
00111   component bcm_rod_formatter
00112     generic (
00113       INPUT_DATA_WIDTH             : positive;
00114       MAX_FRAGMENT_SIZE            : std_logic_vector(11 downto 0);
00115       SLINK_BEGIN_OF_FRAGMENT      : std_logic_vector(31 downto 0);
00116       SLINK_END_OF_FRAGMENT        : std_logic_vector(31 downto 0);
00117       ROD_HEADER                   : std_logic_vector(31 downto 0);
00118       ROD_HEADER_WORDS             : std_logic_vector(31 downto 0);
00119       ROD_STATUS_BLOCK_WORD1       : std_logic_vector(31 downto 0);
00120       ROD_STATUS_BLOCK_WORD2       : std_logic_vector(31 downto 0);
00121       ROD_STATUS_BLOCK_WORDS       : std_logic_vector(31 downto 0);
00122       ROD_STATUS_BLOCK_BEFORE_DATA : std_logic_vector(31 downto 0);
00123       ROD_STATUS_BLOCK_AFTER_DATA  : std_logic_vector(31 downto 0);
00124       ROD_EMPTY                    : std_logic_vector(31 downto 0));
00125     port (
00126       CLK                     : in  std_logic;
00127       SCLR                    : in  std_logic;
00128       rod_data_vld            : in  std_logic;
00129       rod_data_available      : in  std_logic                     := '0';
00130       rod_fragment_end        : in  std_logic                     := '0';
00131       rod_input_data          : in  std_logic_vector(INPUT_DATA_WIDTH-1 downto 0);
00132       rod_data_next           : out std_logic                     := '0';
00133       rod_format_version      : in  std_logic_vector(31 downto 0) := X"03010000";
00134       rod_source_ID           : in  std_logic_vector(31 downto 0) := X"00810000";
00135       rod_run_number          : in  std_logic_vector(31 downto 0) := X"7fffffff";
00136       rod_CTP_trigger_type    : in  std_logic_vector(31 downto 0) := X"00000011";
00137       rod_detector_event_type : in  std_logic_vector(31 downto 0) := X"000000dd";
00138       hola_LFF                : in  std_logic;
00139       hola_LDOWN              : in  std_logic;
00140       hola_LRL                : in  std_logic_vector(3 downto 0);
00141       hola_CLK                : out std_logic;
00142       hola_UD                 : out std_logic_vector(31 downto 0);
00143       hola_URESET             : out std_logic;
00144       hola_UTEST              : out std_logic;
00145       hola_UCTRL              : out std_logic;
00146       hola_UWEN               : out std_logic;
00147       hola_UDW                : out std_logic_vector(1 downto 0)  := "00");
00148   end component;
00149 
00150   signal treadmil_data_output    : std_logic_vector(31 downto 0);
00151   signal treadmil_data_valid     : std_logic;
00152   signal treadmil_data_endoffrag : std_logic;
00153   signal treadmil_error          : std_logic;
00154   signal treadmil_stop           : std_logic;
00155   signal ram_data_output         : std_logic_vector(31 downto 0);
00156   signal ram_data_available      : std_logic;
00157   signal ram_data_endoffrag      : std_logic;
00158   signal ram_write_error         : std_logic;
00159   signal ram_read_error          : std_logic;
00160   signal rod_data_next           : std_logic;
00161   signal ram_data_vld            : std_logic := '0';
00162   signal rod_busy_i              : std_logic := '0';
00163 
00164 begin
00165 
00166   data_input_busy <= rod_busy_i or (not hola_LFF) or (not hola_LDOWN);
00167 
00168 
00169   treadmil : bcm_rod_treadmil
00170     port map (
00171       CLK_2X                     => CLK_2X,
00172       SCLR                       => SCLR,
00173       data_input(31 downto 0)    => data_lvl1id,
00174       data_input(63 downto 32)   => data_input(191 downto 160),
00175       data_input(95 downto 64)   => data_input(159 downto 128),
00176       data_input(127 downto 96)  => data_input(127 downto 96),
00177       data_input(159 downto 128) => data_input(95 downto 64),
00178       data_input(191 downto 160) => data_input(63 downto 32),
00179       data_input(223 downto 192) => data_input(31 downto 0),
00180       data_input_valid           => data_input_valid,
00181       data_input_endoffrag       => data_input_endoffrag,
00182       stop                       => treadmil_stop,
00183       data_output                => treadmil_data_output,
00184       data_output_valid          => treadmil_data_valid,
00185       data_output_endoffrag      => treadmil_data_endoffrag,
00186       busy                       => rod_busy_i,
00187       error                      => treadmil_error
00188       );
00189 
00190 
00191   ram : bcm_rod_ram
00192     port map (
00193       CLK                   => CLK,
00194       CLK_2X                => CLK_2X,
00195       SCLR                  => SCLR,
00196       data_input            => treadmil_data_output ,
00197       data_input_valid      => treadmil_data_valid,
00198       data_input_endoffrag  => treadmil_data_endoffrag,
00199       stop                  => treadmil_stop,
00200       data_output           => ram_data_output ,
00201       data_output_vld       => ram_data_vld,
00202       data_output_available => ram_data_available,
00203       data_output_endoffrag => ram_data_endoffrag,
00204       data_output_next      => rod_data_next,
00205       busy                  => treadmil_stop,
00206       write_error           => ram_write_error ,
00207       read_error            => ram_read_error
00208       );
00209 
00210 
00211   formatter : bcm_rod_formatter
00212     port map (
00213       CLK                     => CLK,
00214       SCLR                    => SCLR,
00215       rod_data_vld            => ram_data_vld,
00216       rod_data_available      => ram_data_available,
00217       rod_fragment_end        => ram_data_endoffrag,
00218       rod_input_data          => ram_data_output,
00219       rod_data_next           => rod_data_next,
00220       rod_format_version      => rod_format_version,
00221       rod_source_ID           => rod_source_ID,
00222       rod_run_number          => rod_run_number,
00223       rod_CTP_trigger_type    => rod_CTP_trigger_type,
00224       rod_detector_event_type => rod_detector_event_type,
00225       hola_LFF                => hola_LFF,
00226       hola_LDOWN              => hola_LDOWN,
00227       hola_LRL                => hola_LRL,
00228       hola_CLK                => hola_CLK,
00229       hola_UD                 => hola_UD,
00230       hola_URESET             => hola_URESET ,
00231       hola_UTEST              => hola_UTEST,
00232       hola_UCTRL              => hola_UCTRL,
00233       hola_UWEN               => hola_UWEN,
00234       hola_UDW                => hola_UDW
00235       );
00236 
00237 end bcm_rod_arc;
00238