clock_divider.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/sata/clock_divider.vhd,v $
--*  $Revision: 1.7.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:49 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;


entity clock_divider is
  generic(
    DIVISION_FACTOR : integer range 0 to 127 := 2;
    INITIAL_VALUE   : integer range 0 to 127 := 2
    );
  port(
    CLK_IN  : in  std_logic;
    CLK_OUT : out std_logic
    );
end clock_divider;


architecture clock_divider_arc of clock_divider is

  signal clock_out_i : std_logic              := '0';
  signal counter_i   : integer range 0 to 127 := INITIAL_VALUE;
  
begin


  process (CLK_IN)
  begin
    if (CLK_IN'event and CLK_IN = '1') then
      if (counter_i = 2) then
        clock_out_i <= not clock_out_i;
        counter_i   <= DIVISION_FACTOR;
      else
        counter_i <= counter_i - 2;
      end if;
    end if;
  end process;

  CLK_OUT <= clock_out_i;

end clock_divider_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:03 2008 for BCM-AAA by  1.5.7.1-20081012