ddr2_mem_v4_dm_iob.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_v4_dm_iob.vhd,v $
--*  $Revision: 1.3.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;


library unisim;

use unisim.vcomponents.all;


entity ddr2_mem_v4_dm_iob is
  port (
    CLK90          : in  std_logic;
    MASK_DATA_RISE : in  std_logic;
    MASK_DATA_FALL : in  std_logic;
    DDR_DM         : out std_logic
    );
end entity;


architecture arc_v4_dm_iob of ddr2_mem_v4_dm_iob is


  component ODDR
    generic(
      DDR_CLK_EDGE : string := "SAME_EDGE";
      SRTYPE       : string := "SYNC"
      );
    port(
      Q  : out std_ulogic;
      C  : in  std_ulogic;
      CE : in  std_ulogic;
      D1 : in  std_ulogic;
      D2 : in  std_ulogic;
      R  : in  std_ulogic;
      S  : in  std_ulogic
      );
  end component;


  component OBUF
    port(
      I : in  std_logic;
      O : out std_logic
      );

  end component;

  signal dm_out : std_logic;
  signal vcc    : std_logic;
  signal gnd    : std_logic;



begin

  vcc <= '1';
  gnd <= '0';


  oddr_dm : ODDR
    generic map(
      DDR_CLK_EDGE => "SAME_EDGE",
      SRTYPE       => "SYNC"
      )
    port map (
      Q  => dm_out ,
      C   => CLK90 ,
      CE => vcc ,
      D1 => MASK_DATA_RISE,
      D2  => MASK_DATA_Fall,
      R  => gnd ,
      S   => gnd 
      );


  obuf_dm : OBUF
    port map (
      I => dm_out,
      O => DDR_DM
      );

end arc_v4_dm_iob;

---

Author: M.Niegl

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