BCM-AAA: sata.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/sata/sata.vhd,v $                                                  *
00015 --*  $Revision: 1.10.2.4 $                                                *
00016 --*  $Name: dev $                                                    *
00017 --*  $Author: mniegl $                                                  *
00018 --*  $Date: 2008/11/03 17:57:49 $                                                    *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 library ieee;
00025 
00026 use ieee.std_logic_1164.all;
00027 
00028 use ieee.std_logic_arith.all;
00029 
00030 use ieee.std_logic_unsigned.all;
00031 
00032 library unisim;
00033 
00034 use unisim.vcomponents.all;
00035 
00036 
00037 entity sata is
00038   generic (
00039     C_SIMULATION : integer := 0
00040     );
00041   port
00042     (
00043       --CLOCK-PORTS---------------------------------------------------------------------
00044       CLK_RIO_IN           : in  std_logic;
00045       CLK_DRP_IN           : in  std_logic;
00046       CLK_DATA_IN          : in  std_logic;
00047       USRCLK_STABLE_IN     : in  std_logic;
00048       --RESET-PORTS---------------------------------------------------------------------
00049       TX_A_SYSTEM_RESET_IN : in  std_logic;
00050       TX_B_SYSTEM_RESET_IN : in  std_logic;
00051       --PACKAGE-PINS--------------------------------------------------------------------
00052       RXP_SATA_IN          : in  std_logic_vector (1 downto 0);
00053       RXN_SATA_IN          : in  std_logic_vector (1 downto 0);
00054       TXP_SATA_OUT         : out std_logic_vector (1 downto 0);
00055       TXN_SATA_OUT         : out std_logic_vector (1 downto 0);
00056       --STATUS-PORTS--------------------------------------------------------------------
00057       MGTA_TXLOCK_OUT      : out std_logic;
00058       MGTA_RXLOCK_OUT      : out std_logic;
00059       MGTB_TXLOCK_OUT      : out std_logic;
00060       MGTB_RXLOCK_OUT      : out std_logic;
00061       TX_A_READY           : out std_logic;
00062       RX_A_READY           : out std_logic;
00063       TX_B_READY           : out std_logic;
00064       RX_B_READY           : out std_logic;
00065       --DATA-PORTS----------------------------------------------------------------------
00066       A_DATA_IN            : in  std_logic_vector (31 downto 0);
00067       B_DATA_IN            : in  std_logic_vector (31 downto 0);
00068       A_DATA_CONTROL_IN    : in  std_logic_vector (3 downto 0);
00069       B_DATA_CONTROL_IN    : in  std_logic_vector (3 downto 0);
00070       A_DATA_READY_IN      : in  std_logic;
00071       B_DATA_READY_IN      : in  std_logic;
00072       A_EOP_IN             : in  std_logic;
00073       B_EOP_IN             : in  std_logic;
00074       A_DATA_OUT           : out std_logic_vector (31 downto 0);
00075       B_DATA_OUT           : out std_logic_vector (31 downto 0);
00076       A_DATA_READY_OUT     : out std_logic;
00077       B_DATA_READY_OUT     : out std_logic;
00078       A_DATA_CONTROL_OUT   : out std_logic_vector (3 downto 0);
00079       B_DATA_CONTROL_OUT   : out std_logic_vector (3 downto 0);
00080       A_EOP_OUT            : out std_logic;
00081       B_EOP_OUT            : out std_logic;
00082       A_PACKAGE_OK_OUT     : out std_logic;
00083       B_PACKAGE_OK_OUT     : out std_logic;
00084       A_DATA_ERROR_OUT     : out std_logic;
00085       B_DATA_ERROR_OUT     : out std_logic;
00086       --CHIPSCOPE-PORTS-----------------------------------------------------------------
00087       SCOPE_OUT            : out std_logic_vector (191 downto 0)
00088       );
00089 end sata;
00090 
00091 
00092 architecture sata_arc of sata is
00093 
00094 
00095   component ROCKETIO_SATA is
00096     generic
00097       (
00098         SIMULATION_P     : integer                       := 0;  -- Set to 1 when using module in simulation
00099         TX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00001001101";  -- Floor (128*Ttxoutclk1/Tdclk) - 3
00100         TX_FD_EN_P       : std_logic                     := '1';  -- 1 = enable calblock TX frequency test
00101         RX_FD_MIN_P      : std_logic_vector(10 downto 0) := "00001001101";  -- Floor (128*Trxrecclk1/Tdclk) - 3
00102         RX_FD_EN_P       : std_logic                     := '1';  -- 1 = enable calblock RX frequency test
00103         TX_FD_WIDTH_P    : integer                       := 11;  -- TX Fdetect MIN value width
00104         RX_FD_WIDTH_P    : integer                       := 11;  -- RX Fdetect MIN value width
00105         MGT0_GT11_MODE_P : string                        := "B";  -- Default Location
00106         MGT0_MGT_ID_P    : integer                       := 1;  -- 0=A, 1=B
00107         MGT1_GT11_MODE_P : string                        := "A";  -- Default Location
00108         MGT1_MGT_ID_P    : integer                       := 0   -- 0=A, 1=B
00109         );
00110     port
00111       (
00112         RXCOMMADETUSE0_IN      : in  std_logic;
00113         RXCOMMADETUSE1_IN      : in  std_logic;
00114         --------------------------------- CRC Ports --------------------------------
00115         MGT_TXCRCCLK_IN        : in  std_logic;
00116         MGT0_TXCRCDATAVALID_IN : in  std_logic;
00117         MGT1_TXCRCDATAVALID_IN : in  std_logic;
00118         MGT0_TXCRCINIT_IN      : in  std_logic;
00119         MGT1_TXCRCINIT_IN      : in  std_logic;
00120         MGT_TXCRCINTCLK_IN     : in  std_logic;
00121         MGT0_TXCRCOUT_OUT      : out std_logic_vector(31 downto 0);
00122         MGT1_TXCRCOUT_OUT      : out std_logic_vector(31 downto 0);
00123         MGT0_TXCRCRESET_IN     : in  std_logic;
00124         MGT1_TXCRCRESET_IN     : in  std_logic;
00125         MGT_RXCRCCLK_IN        : in  std_logic;
00126         MGT0_RXCRCDATAVALID_IN : in  std_logic;
00127         MGT1_RXCRCDATAVALID_IN : in  std_logic;
00128         MGT0_RXCRCIN_IN        : in  std_logic_vector(31 downto 0);
00129         MGT1_RXCRCIN_IN        : in  std_logic_vector(31 downto 0);
00130         MGT0_RXCRCINIT_IN      : in  std_logic;
00131         MGT1_RXCRCINIT_IN      : in  std_logic;
00132         MGT_RXCRCINTCLK_IN     : in  std_logic;
00133         MGT0_RXCRCOUT_OUT      : out std_logic_vector(31 downto 0);
00134         MGT1_RXCRCOUT_OUT      : out std_logic_vector(31 downto 0);
00135         MGT0_RXCRCRESET_IN     : in  std_logic;
00136         MGT1_RXCRCRESET_IN     : in  std_logic;
00137         --__________________________________________________________________________
00138         --__________________________________________________________________________
00139         --MGT0  (X0Y0)
00140 
00141         ----------------- 8B10B Receive Data Path and Control Ports ----------------
00142         MGT0_RXCHARISCOMMA_OUT   : out std_logic_vector(3 downto 0);
00143         MGT0_RXCHARISK_OUT       : out std_logic_vector(3 downto 0);
00144         MGT0_RXDATA_OUT          : out std_logic_vector(31 downto 0);
00145         MGT0_RXDISPERR_OUT       : out std_logic_vector(3 downto 0);
00146         MGT0_RXNOTINTABLE_OUT    : out std_logic_vector(3 downto 0);
00147         MGT0_RXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00148         ----------------- 8B10B Transmit Data Path and Control Ports ---------------
00149         MGT0_TXBYPASS8B10B_IN    : in  std_logic_vector(3 downto 0);
00150         MGT0_TXCHARDISPMODE_IN   : in  std_logic_vector(3 downto 0);
00151         MGT0_TXCHARDISPVAL_IN    : in  std_logic_vector(3 downto 0);
00152         MGT0_TXCHARISK_IN        : in  std_logic_vector(3 downto 0);
00153         MGT0_TXDATA_IN           : in  std_logic_vector(31 downto 0);
00154         MGT0_TXKERR_OUT          : out std_logic_vector(3 downto 0);
00155         MGT0_TXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00156         -------------------------- Calibration Block Ports -------------------------
00157         MGT0_ACTIVE_OUT          : out std_logic;
00158         MGT0_DISABLE_IN          : in  std_logic;
00159         MGT0_DRP_RESET_IN        : in  std_logic;
00160         MGT0_RX_SIGNAL_DETECT_IN : in  std_logic;
00161         MGT0_TX_SIGNAL_DETECT_IN : in  std_logic;
00162         ----------------------------- Calibration Ports ----------------------------
00163         MGT0_RXCLKSTABLE_IN      : in  std_logic;
00164         MGT0_TXCLKSTABLE_IN      : in  std_logic;
00165         --------------------- Dynamic Reconfiguration Port (DRP) -------------------
00166         MGT0_DADDR_IN            : in  std_logic_vector(7 downto 0);
00167         MGT0_DCLK_IN             : in  std_logic;
00168         MGT0_DEN_IN              : in  std_logic;
00169         MGT0_DI_IN               : in  std_logic_vector(15 downto 0);
00170         MGT0_DO_OUT              : out std_logic_vector(15 downto 0);
00171         MGT0_DRDY_OUT            : out std_logic;
00172         MGT0_DWE_IN              : in  std_logic;
00173         -------------------------------- Global Ports ------------------------------
00174         MGT0_LOOPBACK_IN         : in  std_logic_vector(1 downto 0);
00175         MGT0_POWERDOWN_IN        : in  std_logic;
00176         MGT0_TXINHIBIT_IN        : in  std_logic;
00177         ------------------------ Out of Band Signalling Ports ----------------------
00178         MGT0_RXSIGDET_OUT        : out std_logic;
00179         MGT0_TXENOOB_IN          : in  std_logic;
00180         ---------------------------------- PLL Lock --------------------------------
00181         MGT0_RXLOCK_OUT          : out std_logic;
00182         MGT0_TXLOCK_OUT          : out std_logic;
00183         --------------------------- Polarity Control Ports -------------------------
00184         MGT0_RXPOLARITY_IN       : in  std_logic;
00185         MGT0_TXPOLARITY_IN       : in  std_logic;
00186         ---------------------------- Ports for Simulation --------------------------
00187         MGT0_COMBUSIN_IN         : in  std_logic_vector(15 downto 0);
00188         MGT0_COMBUSOUT_OUT       : out std_logic_vector(15 downto 0);
00189         ------------------------------ Reference Clocks ----------------------------
00190         MGT0_REFCLK1_IN          : in  std_logic;
00191         ----------------------------------- Resets ---------------------------------
00192         MGT0_RXPMARESET_IN       : in  std_logic;
00193         MGT0_RXRESET_IN          : in  std_logic;
00194         MGT0_TXPMARESET_IN       : in  std_logic;
00195         MGT0_TXRESET_IN          : in  std_logic;
00196         ------------------------------ Serdes Alignment ----------------------------
00197         MGT0_ENMCOMMAALIGN_IN    : in  std_logic;
00198         MGT0_ENPCOMMAALIGN_IN    : in  std_logic;
00199         MGT0_RXCOMMADET_OUT      : out std_logic;
00200         MGT0_RXREALIGN_OUT       : out std_logic;
00201         -------------------------------- Serial Ports ------------------------------
00202         MGT0_RX1N_IN             : in  std_logic;
00203         MGT0_RX1P_IN             : in  std_logic;
00204         MGT0_TX1N_OUT            : out std_logic;
00205         MGT0_TX1P_OUT            : out std_logic;
00206         ----------------------------------- Status ---------------------------------
00207         MGT0_RXSTATUS_OUT        : out std_logic_vector(5 downto 0);
00208         ------------------------------ Synchronization -----------------------------
00209         MGT0_RXSYNC_IN           : in  std_logic;
00210         MGT0_TXSYNC_IN           : in  std_logic;
00211         -------------------------------- User Clocks -------------------------------
00212         MGT0_RXRECCLK1_OUT       : out std_logic;
00213         MGT0_RXRECCLK2_OUT       : out std_logic;
00214         MGT0_RXUSRCLK2_IN        : in  std_logic;
00215         MGT0_TXOUTCLK1_OUT       : out std_logic;
00216         MGT0_TXOUTCLK2_OUT       : out std_logic;
00217         MGT0_TXUSRCLK2_IN        : in  std_logic;
00218 
00219 
00220         --__________________________________________________________________________
00221         --__________________________________________________________________________
00222         --MGT1  (X0Y1)
00223 
00224         ----------------- 8B10B Receive Data Path and Control Ports ----------------
00225         MGT1_RXCHARISCOMMA_OUT   : out std_logic_vector(3 downto 0);
00226         MGT1_RXCHARISK_OUT       : out std_logic_vector(3 downto 0);
00227         MGT1_RXDATA_OUT          : out std_logic_vector(31 downto 0);
00228         MGT1_RXDISPERR_OUT       : out std_logic_vector(3 downto 0);
00229         MGT1_RXNOTINTABLE_OUT    : out std_logic_vector(3 downto 0);
00230         MGT1_RXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00231         ----------------- 8B10B Transmit Data Path and Control Ports ---------------
00232         MGT1_TXBYPASS8B10B_IN    : in  std_logic_vector(3 downto 0);
00233         MGT1_TXCHARDISPMODE_IN   : in  std_logic_vector(3 downto 0);
00234         MGT1_TXCHARDISPVAL_IN    : in  std_logic_vector(3 downto 0);
00235         MGT1_TXCHARISK_IN        : in  std_logic_vector(3 downto 0);
00236         MGT1_TXDATA_IN           : in  std_logic_vector(31 downto 0);
00237         MGT1_TXKERR_OUT          : out std_logic_vector(3 downto 0);
00238         MGT1_TXRUNDISP_OUT       : out std_logic_vector(3 downto 0);
00239         -------------------------- Calibration Block Ports -------------------------
00240         MGT1_ACTIVE_OUT          : out std_logic;
00241         MGT1_DISABLE_IN          : in  std_logic;
00242         MGT1_DRP_RESET_IN        : in  std_logic;
00243         MGT1_RX_SIGNAL_DETECT_IN : in  std_logic;
00244         MGT1_TX_SIGNAL_DETECT_IN : in  std_logic;
00245         ----------------------------- Calibration Ports ----------------------------
00246         MGT1_RXCLKSTABLE_IN      : in  std_logic;
00247         MGT1_TXCLKSTABLE_IN      : in  std_logic;
00248         --------------------- Dynamic Reconfiguration Port (DRP) -------------------
00249         MGT1_DADDR_IN            : in  std_logic_vector(7 downto 0);
00250         MGT1_DCLK_IN             : in  std_logic;
00251         MGT1_DEN_IN              : in  std_logic;
00252         MGT1_DI_IN               : in  std_logic_vector(15 downto 0);
00253         MGT1_DO_OUT              : out std_logic_vector(15 downto 0);
00254         MGT1_DRDY_OUT            : out std_logic;
00255         MGT1_DWE_IN              : in  std_logic;
00256         -------------------------------- Global Ports ------------------------------
00257         MGT1_LOOPBACK_IN         : in  std_logic_vector(1 downto 0);
00258         MGT1_POWERDOWN_IN        : in  std_logic;
00259         MGT1_TXINHIBIT_IN        : in  std_logic;
00260         ------------------------ Out of Band Signalling Ports ----------------------
00261         MGT1_RXSIGDET_OUT        : out std_logic;
00262         MGT1_TXENOOB_IN          : in  std_logic;
00263         ---------------------------------- PLL Lock --------------------------------
00264         MGT1_RXLOCK_OUT          : out std_logic;
00265         MGT1_TXLOCK_OUT          : out std_logic;
00266         --------------------------- Polarity Control Ports -------------------------
00267         MGT1_RXPOLARITY_IN       : in  std_logic;
00268         MGT1_TXPOLARITY_IN       : in  std_logic;
00269         ---------------------------- Ports for Simulation --------------------------
00270         MGT1_COMBUSIN_IN         : in  std_logic_vector(15 downto 0);
00271         MGT1_COMBUSOUT_OUT       : out std_logic_vector(15 downto 0);
00272         ------------------------------ Reference Clocks ----------------------------
00273         MGT1_REFCLK1_IN          : in  std_logic;
00274         ----------------------------------- Resets ---------------------------------
00275         MGT1_RXPMARESET_IN       : in  std_logic;
00276         MGT1_RXRESET_IN          : in  std_logic;
00277         MGT1_TXPMARESET_IN       : in  std_logic;
00278         MGT1_TXRESET_IN          : in  std_logic;
00279         ------------------------------ Serdes Alignment ----------------------------
00280         MGT1_ENMCOMMAALIGN_IN    : in  std_logic;
00281         MGT1_ENPCOMMAALIGN_IN    : in  std_logic;
00282         MGT1_RXCOMMADET_OUT      : out std_logic;
00283         MGT1_RXREALIGN_OUT       : out std_logic;
00284         -------------------------------- Serial Ports ------------------------------
00285         MGT1_RX1N_IN             : in  std_logic;
00286         MGT1_RX1P_IN             : in  std_logic;
00287         MGT1_TX1N_OUT            : out std_logic;
00288         MGT1_TX1P_OUT            : out std_logic;
00289         ----------------------------------- Status ---------------------------------
00290         MGT1_RXSTATUS_OUT        : out std_logic_vector(5 downto 0);
00291         ------------------------------ Synchronization -----------------------------
00292         MGT1_RXSYNC_IN           : in  std_logic;
00293         MGT1_TXSYNC_IN           : in  std_logic;
00294         -------------------------------- User Clocks -------------------------------
00295         MGT1_RXRECCLK1_OUT       : out std_logic;
00296         MGT1_RXRECCLK2_OUT       : out std_logic;
00297         MGT1_RXUSRCLK2_IN        : in  std_logic;
00298         MGT1_TXOUTCLK1_OUT       : out std_logic;
00299         MGT1_TXOUTCLK2_OUT       : out std_logic;
00300         MGT1_TXUSRCLK2_IN        : in  std_logic
00301 
00302         );
00303   end component;
00304 
00305   component sata_gt11_init_tx
00306     generic
00307       (
00308         C_SIMULATION : integer := 0     -- Set to 1 for simulation
00309         );
00310     port
00311       (
00312         CLK           : in  std_logic;
00313         START_INIT    : in  std_logic;
00314         LOCK          : in  std_logic;
00315         USRCLK_STABLE : in  std_logic;
00316         PCS_ERROR     : in  std_logic;
00317         PMA_RESET     : out std_logic;
00318         SYNC          : out std_logic;
00319         PCS_RESET     : out std_logic;
00320         READY         : out std_logic
00321 
00322         );
00323   end component;
00324 
00325   component sata_gt11_init_rx
00326     generic
00327       (
00328         C_SIMULATION : integer := 0     -- Set to 1 for simulation
00329         );
00330     port
00331       (
00332         CLK           : in  std_logic;
00333         START_INIT    : in  std_logic;
00334         LOCK          : in  std_logic;
00335         USRCLK_STABLE : in  std_logic;
00336         PCS_ERROR     : in  std_logic;
00337         PMA_RESET     : out std_logic;
00338         SYNC          : out std_logic;
00339         PCS_RESET     : out std_logic;
00340         READY         : out std_logic
00341         );
00342   end component;
00343 
00344 
00345   --static signals-------------------------------------------------------------------------------------
00346   signal tied_to_ground_i         : std_logic                    := '0';
00347   signal tied_to_ground_vec_i     : std_logic_vector(63 downto 0);
00348   signal tied_to_vcc_i            : std_logic                    := '1';
00349   signal tied_to_vcc_vec_i        : std_logic_vector(63 downto 0);
00350   --clock signals-------------------------------------------------------------------------------------
00351   signal clk2_usr_i               : std_logic;
00352   signal clk2_usr_not_i           : std_logic;
00353   signal clk_drp_in_i             : std_logic                    := '0';  --clock for PLL correction block & for reset circuits
00354   signal tx_usrclks_stable_i      : std_logic;
00355   signal rx_usrclks_stable_i      : std_logic;
00356   signal mgtB_rxrecclk1_i         : std_logic;  --unused
00357   signal mgtB_rxrecclk1_ii        : std_logic;
00358   signal mgtA_rxrecclk1_i         : std_logic;  --unused
00359   signal mgtA_rxrecclk1_ii        : std_logic;
00360   signal mgtB_rxrecclk2_i         : std_logic;  --unused
00361   signal mgtA_rxrecclk2_i         : std_logic;  --unused
00362   signal mgtB_txoutclk1_i         : std_logic;  --unused
00363   signal mgtA_txoutclk1_i         : std_logic;  --unused
00364   signal mgtB_txoutclk2_i         : std_logic;  --unused
00365   signal mgtA_txoutclk2_i         : std_logic;  --unused
00366   signal mgt_data_recovered_clk_i : std_logic;
00367   signal clk_half_sata            : std_logic;
00368   --status signals-------------------------------------------------------------------------------------
00369   signal mgtB_txlock_i            : std_logic;  --PLL lock status from individual mgts
00370   signal mgtB_rxlock_i            : std_logic;
00371   signal mgtA_txlock_i            : std_logic;
00372   signal mgtA_rxlock_i            : std_logic;
00373   signal tx_A_system_ready_i      : std_logic;  --'1' when both tx are ready (reset is done successfully)
00374   signal rx_A_system_ready_i      : std_logic;  --'1' when both rx are ready (reset is done successfully)
00375   signal tx_B_system_ready_i      : std_logic;  --'1' when both tx are ready (reset is done successfully)
00376   signal rx_B_system_ready_i      : std_logic;  --'1' when both rx are ready (reset is done successfully)
00377   --reset signals-------------------------------------------------------------------------------------
00378   signal tx_A_system_reset_in_i   : std_logic;
00379   signal tx_B_system_reset_in_i   : std_logic;
00380   signal drpA_reset_i             : std_logic;
00381   signal drpB_reset_i             : std_logic;
00382   signal txA_sync_i               : std_logic;
00383   signal txB_sync_i               : std_logic;
00384   signal rxA_sync_i               : std_logic;
00385   signal rxB_sync_i               : std_logic;
00386   signal txA_pmareset_c           : std_logic;
00387   signal txB_pmareset_c           : std_logic;
00388   signal rxA_pmareset_c           : std_logic;
00389   signal rxB_pmareset_c           : std_logic;
00390   signal txA_reset_c              : std_logic;
00391   signal txB_reset_c              : std_logic;
00392   signal rxA_reset_c              : std_logic;
00393   signal rxB_reset_c              : std_logic;
00394   --?? & unused signals------------------------------------------------------------------------------
00395   signal mgtB_calibration_active  : std_logic;  --unused ?? GLEDAJ KAJ SE DOGAJA
00396   signal mgtA_calibration_active  : std_logic;  --unused ?? GLEDAJ KAJ SE DOGAJA
00397   signal mgtB_rxstatus_i          : std_logic_vector(5 downto 0);  --unused --receiver status
00398   signal mgtA_rxstatus_i          : std_logic_vector(5 downto 0);  --unused --receiver status
00399   --Out of Band signals------------------------------------------------------------------------------
00400   signal mgtA_OOBsigdet_i         : std_logic;
00401   signal mgtA_OOBsigsen_i         : std_logic;
00402   signal mgtB_OOBsigdet_i         : std_logic;
00403   signal mgtB_OOBsigsen_i         : std_logic;
00404   --Connection signals-------------------------------------------------------------------------------
00405   signal mgt_tx_inhibit_i         : std_logic;
00406   signal mgtA_txbypass8b10b_i     : std_logic_vector(3 downto 0) := "0000";
00407   signal mgtB_txbypass8b10b_i     : std_logic_vector(3 downto 0) := "0000";
00408   --simulation signal-s------------------------------------------------------------------------------
00409   signal tile0_combusout_a_i      : std_logic_vector(15 downto 0);  --for simulation
00410   signal tile0_combusout_b_i      : std_logic_vector(15 downto 0);  --for simulation
00411   --comma signals------------------------------------------------------------------------------------
00412   signal mgtA_rxrealign_i         : std_logic;  --alignment of bits
00413   signal mgtA_enmcommaalign_i     : std_logic;
00414   signal mgtA_enpcommaalign_i     : std_logic;
00415   signal mgtA_rxcommadet_i        : std_logic;  --comma detected
00416   signal mgtB_rxrealign_i         : std_logic;  --alignment of bits
00417   signal mgtB_enmcommaalign_i     : std_logic;
00418   signal mgtB_enpcommaalign_i     : std_logic;
00419   signal mgtB_rxcommadet_i        : std_logic;  --comma detected
00420   signal align_char_c             : std_logic_vector(31 downto 0);  --comma characters for bit & byte allignement
00421   signal align_control_bits_c     : std_logic_vector(3 downto 0);
00422   signal idle_char_c              : std_logic_vector(31 downto 0);  --comma characters for idle char
00423   signal idle_control_bits_c      : std_logic_vector(3 downto 0);
00424   signal mgtA_txcharisk_i         : std_logic_vector(3 downto 0);
00425   signal mgtB_txcharisk_i         : std_logic_vector(3 downto 0);
00426   signal mgtA_rxcharisk_i         : std_logic_vector(3 downto 0);
00427   signal mgtB_rxcharisk_i         : std_logic_vector(3 downto 0);
00428   signal mgtA_rxchariscomma_i     : std_logic_vector(3 downto 0);
00429   signal mgtB_rxchariscomma_i     : std_logic_vector(3 downto 0);
00430   signal encommaalign_A_i         : std_logic                    := '0';
00431   signal encommaalign_B_i         : std_logic                    := '0';
00432   signal mgtA_align_detected_i    : std_logic                    := '0';
00433   signal mgtB_align_detected_i    : std_logic                    := '0';
00434   signal mgtA_idle_detected_i     : std_logic                    := '0';
00435   signal mgtB_idle_detected_i     : std_logic                    := '0';
00436   --data signals-------------------------------------------------------------------------------------
00437   signal mgtA_tx_data_i           : std_logic_vector(31 downto 0);  --data to be sent
00438   signal mgtB_tx_data_i           : std_logic_vector(31 downto 0);  --data to be sent
00439   signal mgtA_rx_data_i           : std_logic_vector(31 downto 0);  --data received
00440   signal mgtB_rx_data_i           : std_logic_vector(31 downto 0);  --data received
00441   signal mgtA_tx_crc_value_i      : std_logic_vector(31 downto 0);  --CRC computed by tx
00442   signal mgtB_tx_crc_value_i      : std_logic_vector(31 downto 0);  --CRC computed by tx
00443   signal mgtA_data_output_i       : std_logic_vector(31 downto 0);
00444   signal mgtB_data_output_i       : std_logic_vector(31 downto 0);
00445   --error signals------------------------------------------------------------------------------------
00446   signal mgtA_txkerr_i            : std_logic_vector(3 downto 0);
00447   signal mgtB_txkerr_i            : std_logic_vector(3 downto 0);
00448   signal mgtA_txrundisp_i         : std_logic_vector(3 downto 0);
00449   signal mgtB_txrundisp_i         : std_logic_vector(3 downto 0);
00450   signal mgtA_rxrundisp_i         : std_logic_vector(3 downto 0);
00451   signal mgtB_rxrundisp_i         : std_logic_vector(3 downto 0);
00452   signal mgtA_rxnotintable_i      : std_logic_vector(3 downto 0);
00453   signal mgtB_rxnotintable_i      : std_logic_vector(3 downto 0);
00454   signal mgtA_rxdisperr_i         : std_logic_vector(3 downto 0);
00455   signal mgtB_rxdisperr_i         : std_logic_vector(3 downto 0);
00456   signal rxA_error_i              : std_logic;
00457   signal rxB_error_i              : std_logic;
00458   signal destination_aligned_i    : std_logic                    := '0';
00459   signal destination_counter_i    : std_logic_vector(5 downto 0) := "000000";
00460   signal tx_comma_init_i          : std_logic                    := '1';
00461   signal tx_ready_reg_i           : std_logic;
00462   signal rxA_aligned_i            : std_logic                    := '0';
00463   signal rxB_aligned_i            : std_logic                    := '0';
00464   signal rx_ready_buff            : std_logic                    := '1';
00465   --state signals------------------------------------------------------------------------------------
00466   signal tx_A_package_state_i     : std_logic_vector(1 downto 0) := "00";
00467   signal tx_B_package_state_i     : std_logic_vector(1 downto 0) := "00";
00468   signal tx_A_crc_data_valid_i    : std_logic                    := '1';
00469   signal tx_B_crc_data_valid_i    : std_logic                    := '1';
00470   signal tx_A_crc_init_i          : std_logic                    := '0';
00471   signal tx_B_crc_init_i          : std_logic                    := '0';
00472   signal tx_A_send_comma_i        : std_logic                    := '0';
00473   signal tx_B_send_comma_i        : std_logic                    := '0';
00474   signal tx_A_send_crc_i          : std_logic                    := '0';
00475   signal tx_B_send_crc_i          : std_logic                    := '0';
00476   signal tx_send_idle_i           : std_logic                    := '0';
00477   signal rxA_package_state_i      : std_logic_vector(1 downto 0) := "00";
00478   signal rxA_crc_data_valid_i     : std_logic                    := '1';
00479   signal rxA_crc_init_i           : std_logic                    := '0';
00480   signal rxA_crc_value_i          : std_logic_vector (31 downto 0);
00481   signal rxB_package_state_i      : std_logic_vector(1 downto 0) := "00";
00482   signal rxB_crc_data_valid_i     : std_logic                    := '1';
00483   signal rxB_crc_init_i           : std_logic                    := '0';
00484   signal rxB_crc_value_i          : std_logic_vector (31 downto 0);
00485   signal rxA_data_ready_i         : std_logic;
00486   signal rxB_data_ready_i         : std_logic;
00487   signal rxA_data_error_i         : std_logic;
00488   signal rxB_data_error_i         : std_logic;
00489   signal mgtA_control_out_i       : std_logic_vector (3 downto 0);
00490   signal mgtB_control_out_i       : std_logic_vector (3 downto 0);
00491   signal mgtA_eop_out_i           : std_logic;
00492   signal mgtB_eop_out_i           : std_logic;
00493   signal mgtA_data_ready_out_i    : std_logic;
00494   signal mgtB_data_ready_out_i    : std_logic;
00495   signal mgtA_data_error_out_i    : std_logic;
00496   signal mgtB_data_error_out_i    : std_logic;
00497   signal mgtA_package_ok_out_i    : std_logic;
00498   signal mgtB_package_ok_out_i    : std_logic;
00499 
00500 begin
00501 
00502   --ChipScope-------------------------------------------------------------------
00503   SCOPE_OUT <= (others => '0');
00504   --Static Assignments----------------------------------------------------------
00505 
00506   tied_to_ground_i     <= '0';
00507   tied_to_ground_vec_i <= (others => '0');
00508   tied_to_vcc_i        <= '1';
00509   tied_to_vcc_vec_i    <= (others => '1');
00510 
00511   --Output Assignments----------------------------------------------------------
00512 
00513   MGTA_TXLOCK_OUT <= mgtA_txlock_i;
00514   MGTA_RXLOCK_OUT <= mgtA_rxlock_i;
00515   MGTB_TXLOCK_OUT <= mgtB_txlock_i;
00516   MGTB_RXLOCK_OUT <= mgtB_rxlock_i;
00517   TX_A_READY      <= tx_A_system_ready_i;
00518   RX_A_READY      <= rx_A_system_ready_i;
00519   TX_B_READY      <= tx_B_system_ready_i;
00520   RX_B_READY      <= rx_B_system_ready_i;
00521 
00522   --Input Assignments-----------------------------------------------------------
00523 
00524   tx_A_system_reset_in_i <= TX_A_SYSTEM_RESET_IN;
00525   tx_B_system_reset_in_i <= TX_B_SYSTEM_RESET_IN;
00526   tx_usrclks_stable_i    <= USRCLK_STABLE_IN;  --we drive both with the same clock so the same 'STABLE' signal can be used
00527   rx_usrclks_stable_i    <= USRCLK_STABLE_IN;  --we drive both with the same clock so the same 'STABLE' signal can be used
00528 
00529   --constants-------------------------------------------------------------------
00530   mgt_tx_inhibit_i <= tied_to_ground_i;
00531 
00532   align_char_c         <= x"000000bc";  --comma characters for bit & byte allignement
00533   align_control_bits_c <= "0001";
00534   idle_char_c          <= x"fdfdfdfd";  --comma characters for idle state
00535   idle_control_bits_c  <= "1111";
00536 
00537   --clock signals--------------------------------------------------------
00538   clk2_usr_i     <= CLK_DATA_IN;
00539   clk2_usr_not_i <= not CLK_DATA_IN;
00540 
00541   --this was generated by wizard, perhaps we can remove it ???? in order to save resources
00542   process (clk2_usr_i)
00543   begin
00544     if (clk2_usr_i'event and clk2_usr_i = '1') then
00545       clk_half_sata <= not clk_half_sata;
00546     end if;
00547   end process;
00548 
00549   drp_clk_in_bufr_i : BUFR
00550     port map
00551     (
00552       CE  => '1' ,
00553       CLR => '0' ,
00554       I   => clk_half_sata,             --CLK_DRP_IN,
00555       O   => clk_drp_in_i
00556       );
00557 
00558   --Out of Band signals---------------------------------------------------------
00559   --mgtA_OOBsigdet_i;--unused for now 
00560   mgtA_OOBsigsen_i <= tied_to_ground_i;
00561   --mgtB_OOBsigdet_i;--unused for now 
00562   mgtB_OOBsigsen_i <= tied_to_ground_i;
00563 
00564   --Transmitter-----------------------------------------------------------------
00565   --Incoming data---------------------------------------------------------------
00566 
00567   process (clk2_usr_not_i)
00568   begin
00569     if(clk2_usr_not_i'event and clk2_usr_not_i = '1') then
00570       if (tx_A_system_ready_i = '1') then
00571         if (tx_A_package_state_i = "00") then
00572           if (A_EOP_IN = '1') then
00573                                         --we are sending the alignement comma
00574             mgtA_txcharisk_i      <= align_control_bits_c;
00575             mgtA_tx_data_i        <= align_char_c;
00576                                         --the next state
00577             tx_A_package_state_i  <= "01";
00578             tx_A_send_comma_i     <= '1';
00579             tx_A_crc_data_valid_i <= '0';
00580           else
00581                                         --we are sending the content of package
00582             if(A_DATA_READY_IN = '1') then
00583               mgtA_txcharisk_i <= A_DATA_CONTROL_IN;
00584               mgtA_tx_data_i   <= A_DATA_IN;
00585             else
00586               mgtA_txcharisk_i <= idle_control_bits_c;
00587               mgtA_tx_data_i   <= idle_char_c;
00588             end if;
00589             tx_A_send_comma_i     <= '0';
00590             tx_A_send_crc_i       <= '0';
00591             tx_A_crc_data_valid_i <= '1';
00592             tx_A_crc_init_i       <= '0';
00593           end if;
00594         elsif (tx_A_package_state_i = "01") then
00595                                         --we send normal data
00596           if(A_DATA_READY_IN = '1') then
00597             mgtA_txcharisk_i <= A_DATA_CONTROL_IN;
00598             mgtA_tx_data_i   <= A_DATA_IN;
00599           else
00600             mgtA_txcharisk_i <= idle_control_bits_c;
00601             mgtA_tx_data_i   <= idle_char_c;
00602           end if;
00603                                         --the next state
00604           tx_A_package_state_i  <= "10";
00605                                         --crc start
00606           tx_A_send_comma_i     <= '0';
00607           tx_A_crc_data_valid_i <= '1';
00608           tx_A_crc_init_i       <= '1';
00609         elsif (tx_A_package_state_i = "10") then
00610                                         --we send normal data
00611           if(A_DATA_READY_IN = '1') then
00612             mgtA_txcharisk_i <= A_DATA_CONTROL_IN;
00613             mgtA_tx_data_i   <= A_DATA_IN;
00614           else
00615             mgtA_txcharisk_i <= idle_control_bits_c;
00616             mgtA_tx_data_i   <= idle_char_c;
00617           end if;
00618                                         --the next state
00619           tx_A_package_state_i <= "11";
00620                                         --crc start
00621           tx_A_crc_init_i      <= '0';
00622         elsif (tx_A_package_state_i = "11") then
00623                                         --we send the CRC
00624           mgtA_txcharisk_i      <= tied_to_ground_vec_i(3 downto 0);
00625           mgtA_tx_data_i        <= mgtA_tx_crc_value_i;
00626                                         --the next state
00627           tx_A_package_state_i  <= "00";
00628                                         --crc start
00629           tx_A_crc_data_valid_i <= '0';
00630           tx_A_send_crc_i       <= '1';
00631         end if;
00632       else
00633         --if transmitter not ready than we bypass 8/10 encoding and send 0 all the time to force receiver to be out of lock
00634         mgtA_txcharisk_i     <= tied_to_ground_vec_i(3 downto 0);
00635         mgtA_tx_data_i       <= x"00000000";
00636         tx_A_package_state_i <= "00";
00637       end if;
00638     end if;
00639   end process;
00640 
00641   process (clk2_usr_not_i)
00642   begin
00643     if(clk2_usr_not_i'event and clk2_usr_not_i = '1') then
00644       if (tx_B_system_ready_i = '1') then
00645         if (tx_B_package_state_i = "00") then
00646           if (B_EOP_IN = '1') then
00647                                         --we are sending the alignement comma
00648             mgtB_txcharisk_i      <= align_control_bits_c;
00649             mgtB_tx_data_i        <= align_char_c;
00650                                         --the next state
00651             tx_B_package_state_i  <= "01";
00652             tx_B_send_comma_i     <= '1';
00653             tx_B_crc_data_valid_i <= '0';
00654           else
00655                                         --we are sending the content of package
00656             if(B_DATA_READY_IN = '1') then
00657               mgtB_txcharisk_i <= B_DATA_CONTROL_IN;
00658               mgtB_tx_data_i   <= B_DATA_IN;
00659             else
00660               mgtB_txcharisk_i <= idle_control_bits_c;
00661               mgtB_tx_data_i   <= idle_char_c;
00662             end if;
00663             tx_B_send_comma_i     <= '0';
00664             tx_B_send_crc_i       <= '0';
00665             tx_B_crc_data_valid_i <= '1';
00666             tx_B_crc_init_i       <= '0';
00667           end if;
00668         elsif (tx_B_package_state_i = "01") then
00669                                         --we send normal data
00670           if(B_DATA_READY_IN = '1') then
00671             mgtB_txcharisk_i <= B_DATA_CONTROL_IN;
00672             mgtB_tx_data_i   <= B_DATA_IN;
00673           else
00674             mgtB_txcharisk_i <= idle_control_bits_c;
00675             mgtB_tx_data_i   <= idle_char_c;
00676           end if;
00677                                         --the next state
00678           tx_B_package_state_i  <= "10";
00679                                         --crc start
00680           tx_B_send_comma_i     <= '0';
00681           tx_B_crc_data_valid_i <= '1';
00682           tx_B_crc_init_i       <= '1';
00683         elsif (tx_B_package_state_i = "10") then
00684                                         --we send normal data
00685           if(B_DATA_READY_IN = '1') then
00686             mgtB_txcharisk_i <= B_DATA_CONTROL_IN;
00687             mgtB_tx_data_i   <= B_DATA_IN;
00688           else
00689             mgtB_txcharisk_i <= idle_control_bits_c;
00690             mgtB_tx_data_i   <= idle_char_c;
00691           end if;
00692                                         --the next state
00693           tx_B_package_state_i <= "11";
00694                                         --crc start
00695           tx_B_crc_init_i      <= '0';
00696         elsif (tx_B_package_state_i = "11") then
00697                                         --we send the CRC
00698           mgtB_txcharisk_i      <= tied_to_ground_vec_i(3 downto 0);
00699           mgtB_tx_data_i        <= mgtB_tx_crc_value_i;
00700                                         --the next state
00701           tx_B_package_state_i  <= "00";
00702                                         --crc start
00703           tx_B_crc_data_valid_i <= '0';
00704           tx_B_send_crc_i       <= '1';
00705         end if;
00706       else
00707         --if transmitter not ready than we bypass 8/10 encoding and send 0 all the time to force receiver to be out of lock
00708         mgtB_txcharisk_i     <= tied_to_ground_vec_i(3 downto 0);
00709         mgtB_tx_data_i       <= x"00000000";
00710         tx_B_package_state_i <= "00";
00711       end if;
00712     end if;
00713   end process;
00714 
00715   --if transmitter not ready than we bypass 8/10 encoding and send 0 all the time to force receiver to be out of order
00716   mgtA_txbypass8b10b_i <= "0000" when (tx_A_system_ready_i = '1') else "1111";
00717   mgtB_txbypass8b10b_i <= "0000" when (tx_B_system_ready_i = '1') else "1111";
00718 
00719   --Receiver--------------------------------------------------------------------
00720   --comma signals---------------------------------------------------------------
00721   --mgtA_rxrealign_i;--unused for now --alignment of bits has happened
00722   --mgtA_rxcommadet_i;--unused for now --comma detected
00723   --mgtB_rxrealign_i;--unused for now --alignment of bits has happened
00724   --mgtB_rxcommadet_i;--unused for now --comma detected
00725 --      process (clk2_usr_not_i)
00726 --      begin
00727 --              if(clk2_usr_not_i'event and clk2_usr_not_i='1') then
00728 --                      encommaalign_i <= rx_system_ready_i;
00729 --              end if;
00730 --      end process;
00731   encommaalign_A_i     <= rx_A_system_ready_i;
00732   encommaalign_B_i     <= rx_B_system_ready_i;
00733   mgtA_enmcommaalign_i <= encommaalign_A_i;
00734   mgtA_enpcommaalign_i <= encommaalign_A_i;
00735   mgtB_enmcommaalign_i <= encommaalign_B_i;
00736   mgtB_enpcommaalign_i <= encommaalign_B_i;
00737 
00738   --Clock buffers---------------------------------------------------------------
00739   CLK_BUFFER_A : BUFR
00740     port map (
00741       CLR => '0' ,
00742       CE  => '1' ,
00743       O   => mgtA_rxrecclk1_i,          -- Clock buffer output
00744       I   => CLK_DATA_IN                -- Clock buffer input
00745       );        
00746 
00747 --      CLK_BUFFER_B : BUFR
00748 --         port map (
00749 --            CLR => '0',
00750 --                      CE => '1',
00751 --                      O => mgtB_rxrecclk1_i,     -- Clock buffer output
00752 --            I => CLK_DATA_IN      -- Clock buffer input
00753 --   ); 
00754   mgtB_rxrecclk1_i <= mgtA_rxrecclk1_i;
00755 
00756   --Alignement control----------------------------------------------------------
00757   process (mgtA_rxrecclk1_i)
00758   begin
00759     if(mgtA_rxrecclk1_i'event and mgtA_rxrecclk1_i = '1') then
00760       if ((rx_A_system_ready_i = '0') or (rxA_error_i = '1')) then
00761         rxA_aligned_i <= '0';
00762       end if;
00763       if (mgtA_align_detected_i = '1') then
00764         rxA_aligned_i <= '1';
00765       end if;
00766     end if;
00767   end process;
00768   process (mgtB_rxrecclk1_i)
00769   begin
00770     if(mgtB_rxrecclk1_i'event and mgtB_rxrecclk1_i = '1') then
00771       if (rx_B_system_ready_i = '0' or rxB_error_i = '1') then
00772         rxB_aligned_i <= '0';
00773       end if;
00774       if (mgtB_align_detected_i = '1') then
00775         rxB_aligned_i <= '1';
00776       end if;
00777     end if;
00778   end process;
00779 
00780   mgtA_align_detected_i <= '1' when (mgtA_rx_data_i = align_char_c and rx_A_system_ready_i = '1') else '0';
00781   mgtB_align_detected_i <= '1' when (mgtB_rx_data_i = align_char_c and rx_B_system_ready_i = '1') else '0';
00782   mgtA_idle_detected_i  <= '1' when (mgtA_rx_data_i = idle_char_c and rx_A_system_ready_i = '1')  else '0';
00783   mgtB_idle_detected_i  <= '1' when (mgtB_rx_data_i = idle_char_c and rx_B_system_ready_i = '1')  else '0';
00784 
00785   --Outgoing data---------------------------------------------------------------
00786   process (mgtA_rxrecclk1_i)
00787   begin
00788     if(mgtA_rxrecclk1_i'event and mgtA_rxrecclk1_i = '0') then
00789       if(rx_A_system_ready_i = '1') then
00790         if (rxA_package_state_i = "00") then
00791           if(mgtA_align_detected_i = '1') then
00792                                         --we received EOP char
00793             mgtA_data_output_i    <= mgtA_rx_data_i;
00794             mgtA_control_out_i    <= mgtA_rxcharisk_i;
00795                                         --the next state
00796             rxA_package_state_i   <= "01";
00797             mgtA_eop_out_i        <= '1';
00798             rxA_crc_data_valid_i  <= '0';
00799             mgtA_data_ready_out_i <= '0';
00800             mgtA_data_error_out_i <= '0';
00801           else
00802                                         --we are receiving normal data
00803             mgtA_data_output_i    <= mgtA_rx_data_i;
00804             mgtA_control_out_i    <= mgtA_rxcharisk_i;
00805             mgtA_data_ready_out_i <= rxA_data_ready_i;
00806             mgtA_data_error_out_i <= rxA_data_error_i;
00807             mgtA_package_ok_out_i <= '0';
00808             mgtA_eop_out_i        <= '0';
00809             rxA_crc_data_valid_i  <= '1';
00810             rxA_crc_init_i        <= '0';
00811           end if;
00812         elsif (rxA_package_state_i = "01") then
00813                                         --we receive normal data
00814           mgtA_data_output_i    <= mgtA_rx_data_i;
00815           mgtA_control_out_i    <= mgtA_rxcharisk_i;
00816           mgtA_data_ready_out_i <= rxA_data_ready_i;
00817           mgtA_data_error_out_i <= rxA_data_error_i;
00818                                         --the next state
00819           rxA_package_state_i   <= "10";
00820           mgtA_eop_out_i        <= '0';
00821           rxA_crc_data_valid_i  <= '1';
00822           rxA_crc_init_i        <= '1';
00823         elsif (rxA_package_state_i = "10") then
00824                                         --we receive normal data
00825           mgtA_data_output_i    <= mgtA_rx_data_i;
00826           mgtA_control_out_i    <= mgtA_rxcharisk_i;
00827           mgtA_data_ready_out_i <= rxA_data_ready_i;
00828           mgtA_data_error_out_i <= rxA_data_error_i;
00829                                         --the next state
00830           rxA_package_state_i   <= "11";
00831           rxA_crc_init_i        <= '0';
00832         elsif (rxA_package_state_i = "11") then
00833                                         --we are receiving crc
00834           mgtA_data_output_i    <= mgtA_rx_data_i;
00835           mgtA_control_out_i    <= mgtA_rxcharisk_i;
00836                                         --the next state
00837           rxA_crc_data_valid_i  <= '0';
00838           mgtA_data_ready_out_i <= '0';
00839           mgtA_data_error_out_i <= '0';
00840           rxA_package_state_i   <= "00";
00841           if(rxA_crc_value_i = mgtA_rx_data_i) then
00842             mgtA_package_ok_out_i <= '1';
00843           else
00844             mgtA_package_ok_out_i <= '0';
00845           end if;
00846         end if;
00847       else
00848         mgtA_data_output_i    <= mgtA_rx_data_i;
00849         mgtA_control_out_i    <= mgtA_rxcharisk_i;
00850         mgtA_data_ready_out_i <= '0';
00851         mgtA_data_error_out_i <= '0';
00852         rxA_package_state_i   <= "00";
00853       end if;
00854     end if;
00855   end process;
00856 
00857   process (mgtB_rxrecclk1_i)
00858   begin
00859     if(mgtB_rxrecclk1_i'event and mgtB_rxrecclk1_i = '0') then
00860       if(rx_B_system_ready_i = '1') then
00861         if (rxB_package_state_i = "00") then
00862           if(mgtB_align_detected_i = '1') then
00863                                         --we received EOP char
00864             mgtB_data_output_i    <= mgtB_rx_data_i;
00865             mgtB_control_out_i    <= mgtB_rxcharisk_i;
00866                                         --the next state
00867             rxB_package_state_i   <= "01";
00868             mgtB_eop_out_i        <= '1';
00869             rxB_crc_data_valid_i  <= '0';
00870             mgtB_data_ready_out_i <= '0';
00871             mgtB_data_error_out_i <= '0';
00872           else
00873                                         --we are receiving normal data
00874             mgtB_data_output_i    <= mgtB_rx_data_i;
00875             mgtB_control_out_i    <= mgtB_rxcharisk_i;
00876             mgtB_data_ready_out_i <= rxB_data_ready_i;
00877             mgtB_data_error_out_i <= rxB_data_error_i;
00878             mgtB_package_ok_out_i <= '0';
00879             mgtB_eop_out_i        <= '0';
00880             rxB_crc_data_valid_i  <= '1';
00881             rxB_crc_init_i        <= '0';
00882           end if;
00883         elsif (rxB_package_state_i = "01") then
00884                                         --we receive normal data
00885           mgtB_data_output_i    <= mgtB_rx_data_i;
00886           mgtB_control_out_i    <= mgtB_rxcharisk_i;
00887           mgtB_data_ready_out_i <= rxB_data_ready_i;
00888           mgtB_data_error_out_i <= rxB_data_error_i;
00889                                         --the next state
00890           rxB_package_state_i   <= "10";
00891           mgtB_eop_out_i        <= '0';
00892           rxB_crc_data_valid_i  <= '1';
00893           rxB_crc_init_i        <= '1';
00894         elsif (rxB_package_state_i = "10") then
00895                                         --we receive normal data
00896           mgtB_data_output_i    <= mgtB_rx_data_i;
00897           mgtB_control_out_i    <= mgtB_rxcharisk_i;
00898           mgtB_data_ready_out_i <= rxB_data_ready_i;
00899           mgtB_data_error_out_i <= rxB_data_error_i;
00900                                         --the next state
00901           rxB_package_state_i   <= "11";
00902           rxB_crc_init_i        <= '0';
00903         elsif (rxB_package_state_i = "11") then
00904                                         --we are receiving crc
00905           mgtB_data_output_i    <= mgtB_rx_data_i;
00906           mgtB_control_out_i    <= mgtB_rxcharisk_i;
00907                                         --the next state
00908           rxB_crc_data_valid_i  <= '0';
00909           mgtB_data_ready_out_i <= '0';
00910           mgtB_data_error_out_i <= '0';
00911           rxB_package_state_i   <= "00";
00912           if(rxB_crc_value_i = mgtB_rx_data_i) then
00913             mgtB_package_ok_out_i <= '1';
00914           else
00915             mgtB_package_ok_out_i <= '0';
00916           end if;
00917         end if;
00918       else
00919         mgtB_data_output_i    <= mgtB_rx_data_i;
00920         mgtB_control_out_i    <= mgtB_rxcharisk_i;
00921         mgtB_data_ready_out_i <= '0';
00922         mgtB_data_error_out_i <= '0';
00923         rxB_package_state_i   <= "00";
00924       end if;
00925     end if;
00926   end process;
00927 
00928   A_DATA_OUT         <= mgtA_data_output_i;
00929   B_DATA_OUT         <= mgtB_data_output_i;
00930   A_DATA_READY_OUT   <= mgtA_data_ready_out_i;
00931   B_DATA_READY_OUT   <= mgtB_data_ready_out_i;
00932   A_DATA_CONTROL_OUT <= mgtA_control_out_i;
00933   B_DATA_CONTROL_OUT <= mgtB_control_out_i;
00934   A_EOP_OUT          <= mgtA_eop_out_i;
00935   B_EOP_OUT          <= mgtB_eop_out_i;
00936   A_PACKAGE_OK_OUT   <= mgtA_package_ok_out_i;
00937   B_PACKAGE_OK_OUT   <= mgtB_package_ok_out_i;
00938   A_DATA_ERROR_OUT   <= mgtA_data_error_out_i;
00939   B_DATA_ERROR_OUT   <= mgtB_data_error_out_i;
00940 
00941 --      rxA_data_ready_i        <=      rxA_aligned and (not rxA_error_i) and (not mgtA_align_detected_i) and (not mgtA_idle_detected_i);
00942   rxA_data_ready_i <= '1' when (rxA_aligned_i = '1' and rxA_error_i = '0' and mgtA_align_detected_i = '0' and mgtA_idle_detected_i = '0')                               else '0';
00943   rxB_data_ready_i <= '1' when (rxB_aligned_i = '1' and rxB_error_i = '0' and mgtB_align_detected_i = '0' and mgtB_idle_detected_i = '0')                               else '0';
00944   rxA_data_error_i <= '1' when (rxA_aligned_i = '1' and rxA_error_i = '1' and rx_A_system_ready_i = '1' and mgtA_align_detected_i = '0' and mgtA_idle_detected_i = '0') else '0';
00945   rxB_data_error_i <= '1' when (rxB_aligned_i = '1' and rxB_error_i = '1' and rx_B_system_ready_i = '1' and mgtB_align_detected_i = '0' and mgtB_idle_detected_i = '0') else '0';
00946 
00947   --Error signals---------------------------------------------------------------
00948   rxA_error_i <= '0' when (mgtA_rxnotintable_i = "0000") else '1';  --mgtA_rxdisperr_i = "0000" and 
00949   rxB_error_i <= '0' when (mgtB_rxnotintable_i = "0000") else '1';  --mgtB_rxdisperr_i = "0000" and 
00950 
00951   --Reset for  transmitter------------------------------------------------------
00952   reset_A_TX_I_inst : sata_GT11_INIT_TX
00953     generic map
00954     (
00955       C_SIMULATION => C_SIMULATION        -- Set to 1 for simulation
00956       )
00957     port map
00958     (
00959       CLK           => clk_drp_in_i,
00960       START_INIT    => tx_A_system_reset_in_i ,
00961       LOCK          => mgtA_txlock_i,
00962       USRCLK_STABLE => tx_usrclks_stable_i,
00963       PCS_ERROR     => tied_to_ground_i ,  --unused
00964       PMA_RESET     => txA_pmareset_c,
00965       PCS_RESET     => txA_reset_c,
00966       SYNC          => txA_sync_i,
00967       READY         => tx_A_system_ready_i
00968       );
00969 
00970   --Reset for transmitter-------------------------------------------------------
00971   reset_B_TX_I_inst : sata_GT11_INIT_TX
00972     generic map
00973     (
00974       C_SIMULATION  => C_SIMULATION         -- Set to 1 for simulation
00975       )
00976     port map
00977     (
00978       CLK           => clk_drp_in_i,
00979       START_INIT    => tx_B_system_reset_in_i,
00980       LOCK          => mgtB_txlock_i,
00981       USRCLK_STABLE => tx_usrclks_stable_i,
00982       PCS_ERROR     => tied_to_ground_i ,  --unused
00983       PMA_RESET     => txB_pmareset_c,
00984       PCS_RESET     => txB_reset_c,
00985       SYNC          => txB_sync_i,
00986       READY         => tx_B_system_ready_i
00987       );
00988 
00989   --Reset for receiver-----------------------------------------------------------
00990   reset_A_RX_I_inst : sata_GT11_INIT_RX
00991     generic map
00992     (
00993       C_SIMULATION => C_SIMULATION        -- Set to 1 for simulation
00994       )
00995     port map
00996     (
00997       CLK           => clk_drp_in_i,
00998       START_INIT    => tied_to_ground_i ,  --unused   
00999       LOCK          => mgtA_rxlock_i,
01000       USRCLK_STABLE => rx_usrclks_stable_i,
01001       PCS_ERROR     => tied_to_ground_i ,  --unused 
01002       PMA_RESET     => rxA_pmareset_c,
01003       PCS_RESET     => rxA_reset_c,
01004       SYNC          => rxA_sync_i,
01005       READY         => rx_A_system_ready_i
01006       );
01007 
01008   --Reset for receiver-----------------------------------------------------------
01009   reset_B_RX_I_inst : sata_GT11_INIT_RX
01010     generic map
01011     (
01012       C_SIMULATION => C_SIMULATION        -- Set to 1 for simulation
01013       )
01014     port map
01015     (
01016       CLK           => clk_drp_in_i,
01017       START_INIT    => tied_to_ground_i ,  --unused   
01018       LOCK          => mgtB_rxlock_i,
01019       USRCLK_STABLE => rx_usrclks_stable_i,
01020       PCS_ERROR     => tied_to_ground_i ,  --unused 
01021       PMA_RESET     => rxB_pmareset_c,
01022       PCS_RESET     => rxB_reset_c,
01023       SYNC          => rxB_sync_i,
01024       READY         => rx_B_system_ready_i
01025       );
01026 
01027   -- DRP resets on either reset
01028   drpA_reset_i <= tx_A_system_reset_in_i;  -- or rx_system_reset_in_i;
01029   drpB_reset_i <= tx_B_system_reset_in_i;  -- or rx_system_reset_in_i;
01030 
01031   --Rockets-------------------------------------------------------------------
01032   rocketio_sata_i : ROCKETIO_SATA
01033     generic map
01034     (
01035       SIMULATION_P  => 0,  -- Set to 1 when using module in simulation
01036       TX_FD_MIN_P   => "00001001101",   -- Floor (128*Ttxoutclk1/Tdclk) - 3
01037       TX_FD_EN_P    => '1',            -- 1 = enable calblock TX frequency test
01038       RX_FD_MIN_P   => "00001001101",   -- Floor (128*Trxrecclk1/Tdclk) - 3
01039       RX_FD_EN_P    => '1',            -- 1 = enable calblock RX frequency test
01040       TX_FD_WIDTH_P => 11,              -- TX Fdetect MIN value width
01041       RX_FD_WIDTH_P => 11,              -- RX Fdetect MIN value width
01042 
01043 
01044       MGT0_GT11_MODE_P => "B",          -- Default Location
01045       MGT0_MGT_ID_P    => 1,            -- 0=A, 1=B
01046 
01047       MGT1_GT11_MODE_P => "A",                     -- Default Location
01048       MGT1_MGT_ID_P    => 0                        -- 0=A, 1=B
01049       )
01050     port map
01051     (
01052       RXCOMMADETUSE0_IN       => encommaalign_B_i,  --tied_to_vcc_i,
01053       RXCOMMADETUSE1_IN       => encommaalign_A_i,  --tied_to_vcc_i,
01054       --------------------------------- CRC Ports --------------------------------
01055       MGT_TXCRCCLK_IN        => clk2_usr_i,
01056       MGT0_TXCRCDATAVALID_IN => tx_B_crc_data_valid_i,
01057       MGT1_TXCRCDATAVALID_IN => tx_A_crc_data_valid_i,
01058       MGT0_TXCRCINIT_IN      => tx_B_crc_init_i,
01059       MGT1_TXCRCINIT_IN      => tx_A_crc_init_i,
01060       MGT_TXCRCINTCLK_IN     => clk2_usr_i,
01061       MGT0_TXCRCOUT_OUT      => mgtB_tx_crc_value_i,
01062       MGT1_TXCRCOUT_OUT      => mgtA_tx_crc_value_i,
01063       MGT0_TXCRCRESET_IN     => txB_sync_i,
01064       MGT1_TXCRCRESET_IN     => txA_sync_i,
01065       MGT_RXCRCCLK_IN        => clk2_usr_i,
01066       MGT0_RXCRCDATAVALID_IN => rxB_crc_data_valid_i,
01067       MGT1_RXCRCDATAVALID_IN => rxA_crc_data_valid_i,
01068       MGT0_RXCRCIN_IN        => mgtB_data_output_i,
01069       MGT1_RXCRCIN_IN        => mgtA_data_output_i,
01070       MGT0_RXCRCINIT_IN      => rxB_crc_init_i,
01071       MGT1_RXCRCINIT_IN      => rxA_crc_init_i,
01072       MGT_RXCRCINTCLK_IN     => clk2_usr_i,
01073       MGT0_RXCRCOUT_OUT      => rxB_crc_value_i,
01074       MGT1_RXCRCOUT_OUT      => rxA_crc_value_i,
01075       MGT0_RXCRCRESET_IN     => rxB_sync_i,
01076       MGT1_RXCRCRESET_IN     => rxA_sync_i,
01077       --__________________________________________________________________________
01078       --__________________________________________________________________________
01079       --MGT0  (X0Y0) B
01080 
01081       ----------------- 8B10B Receive Data Path and Control Ports ----------------
01082       MGT0_RXCHARISCOMMA_OUT   => mgtB_rxchariscomma_i,
01083       MGT0_RXCHARISK_OUT       => mgtB_rxcharisk_i,
01084       MGT0_RXDATA_OUT          => mgtB_rx_data_i,
01085       MGT0_RXDISPERR_OUT       => mgtB_rxdisperr_i,
01086       MGT0_RXNOTINTABLE_OUT    => mgtB_rxnotintable_i,
01087       MGT0_RXRUNDISP_OUT       => mgtB_rxrundisp_i,
01088       ----------------- 8B10B Transmit Data Path and Control Ports ---------------
01089       MGT0_TXBYPASS8B10B_IN    => mgtB_txbypass8b10b_i,
01090       MGT0_TXCHARDISPMODE_IN   => tied_to_ground_vec_i(3 downto 0),
01091       MGT0_TXCHARDISPVAL_IN    => tied_to_ground_vec_i(3 downto 0),
01092       MGT0_TXCHARISK_IN        => mgtB_txcharisk_i,
01093       MGT0_TXDATA_IN           => mgtB_tx_data_i,
01094       MGT0_TXKERR_OUT          => mgtB_txkerr_i,
01095       MGT0_TXRUNDISP_OUT       => mgtB_txrundisp_i,
01096       -------------------------- Calibration Block Ports -------------------------
01097       MGT0_ACTIVE_OUT          => mgtB_calibration_active ,
01098       MGT0_DISABLE_IN          => tied_to_ground_i,
01099       MGT0_DRP_RESET_IN        => drpB_reset_i,
01100       MGT0_RX_SIGNAL_DETECT_IN => tied_to_vcc_i,
01101       MGT0_TX_SIGNAL_DETECT_IN => tied_to_vcc_i,
01102       ----------------------------- Calibration Ports ----------------------------
01103       MGT0_RXCLKSTABLE_IN      => tied_to_vcc_i,  --this is taken into account in reset logic
01104       MGT0_TXCLKSTABLE_IN      => tied_to_vcc_i,  --this is taken into account in reset logic
01105       --------------------- Dynamic Reconfiguration Port (DRP) -------------------
01106       MGT0_DADDR_IN            => tied_to_ground_vec_i (7 downto 0),
01107       MGT0_DCLK_IN             => clk_drp_in_i,
01108       MGT0_DEN_IN              => tied_to_ground_i ,
01109       MGT0_DI_IN               => tied_to_ground_vec_i (15 downto 0),
01110       MGT0_DO_OUT              => open,
01111       MGT0_DRDY_OUT            => open,
01112       MGT0_DWE_IN              => tied_to_ground_i ,
01113       -------------------------------- Global Ports ------------------------------
01114       MGT0_LOOPBACK_IN         => tied_to_ground_vec_i (1 downto 0),  --internal serial loopback
01115       MGT0_POWERDOWN_IN        => tied_to_ground_i,
01116       MGT0_TXINHIBIT_IN        => mgt_tx_inhibit_i,
01117       ------------------------ Out of Band Signalling Ports ----------------------
01118       MGT0_RXSIGDET_OUT        => mgtB_OOBsigdet_i,
01119       MGT0_TXENOOB_IN          => mgtB_OOBsigsen_i,
01120       ---------------------------------- PLL Lock --------------------------------
01121       MGT0_RXLOCK_OUT          => mgtB_rxlock_i,  --'1' tells that the RX is locked to the external clock
01122       MGT0_TXLOCK_OUT          => mgtB_txlock_i,
01123       --------------------------- Polarity Control Ports -------------------------
01124       MGT0_RXPOLARITY_IN       => tied_to_ground_i,
01125       MGT0_TXPOLARITY_IN       => tied_to_ground_i,
01126       ---------------------------- Ports for Simulation --------------------------
01127       MGT0_COMBUSIN_IN         => tile0_combusout_a_i,
01128       MGT0_COMBUSOUT_OUT       => tile0_combusout_b_i,
01129       ------------------------------ Reference Clocks ----------------------------
01130       MGT0_REFCLK1_IN          => CLK_RIO_IN,
01131       ----------------------------------- Resets ---------------------------------
01132       MGT0_RXPMARESET_IN       => rxB_pmareset_c ,
01133       MGT0_RXRESET_IN          => rxB_reset_c,
01134       MGT0_TXPMARESET_IN       => txB_pmareset_c ,
01135       MGT0_TXRESET_IN          => txB_reset_c,
01136       ------------------------------ Serdes Alignment ----------------------------
01137       MGT0_ENMCOMMAALIGN_IN    => mgtB_enmcommaalign_i,
01138       MGT0_ENPCOMMAALIGN_IN    => mgtB_enpcommaalign_i,
01139       MGT0_RXCOMMADET_OUT      => mgtB_rxcommadet_i,
01140       MGT0_RXREALIGN_OUT       => mgtB_rxrealign_i,
01141       -------------------------------- Serial Ports ------------------------------
01142       MGT0_RX1N_IN             => RXN_SATA_IN(0),
01143       MGT0_RX1P_IN             => RXP_SATA_IN(0),
01144       MGT0_TX1N_OUT            => TXN_SATA_OUT(0),
01145       MGT0_TX1P_OUT            => TXP_SATA_OUT(0),
01146       ----------------------------------- Status ---------------------------------
01147       MGT0_RXSTATUS_OUT        => mgtB_rxstatus_i,
01148       ------------------------------ Synchronization -----------------------------
01149       MGT0_RXSYNC_IN           => rxB_sync_i,
01150       MGT0_TXSYNC_IN           => txB_sync_i,
01151       -------------------------------- User Clocks -------------------------------
01152       MGT0_RXRECCLK1_OUT       => mgtB_rxrecclk1_ii,
01153       MGT0_RXRECCLK2_OUT       => mgtB_rxrecclk2_i,
01154       MGT0_RXUSRCLK2_IN        => mgtB_rxrecclk1_i,  --clk2_usr_i,--clk2_usr_i,--mgtA_rxrecclk1_i,
01155       MGT0_TXOUTCLK1_OUT       => mgtB_txoutclk1_i,
01156       MGT0_TXOUTCLK2_OUT       => mgtB_txoutclk2_i,
01157       MGT0_TXUSRCLK2_IN        => clk2_usr_i,
01158 
01159 
01160       --__________________________________________________________________________
01161       --__________________________________________________________________________
01162       --MGT1  (X0Y1) A
01163 
01164       ----------------- 8B10B Receive Data Path and Control Ports ----------------
01165       MGT1_RXCHARISCOMMA_OUT   => mgtA_rxchariscomma_i,
01166       MGT1_RXCHARISK_OUT       => mgtA_rxcharisk_i,
01167       MGT1_RXDATA_OUT          => mgtA_rx_data_i,
01168       MGT1_RXDISPERR_OUT       => mgtA_rxdisperr_i,
01169       MGT1_RXNOTINTABLE_OUT    => mgtA_rxnotintable_i,
01170       MGT1_RXRUNDISP_OUT       => mgtA_rxrundisp_i,
01171       ----------------- 8B10B Transmit Data Path and Control Ports ---------------
01172       MGT1_TXBYPASS8B10B_IN    => mgtA_txbypass8b10b_i,
01173       MGT1_TXCHARDISPMODE_IN   => tied_to_ground_vec_i(3 downto 0),
01174       MGT1_TXCHARDISPVAL_IN    => tied_to_ground_vec_i(3 downto 0),
01175       MGT1_TXCHARISK_IN        => mgtA_txcharisk_i,
01176       MGT1_TXDATA_IN           => mgtA_tx_data_i,
01177       MGT1_TXKERR_OUT          => mgtA_txkerr_i,
01178       MGT1_TXRUNDISP_OUT       => mgtA_txrundisp_i,
01179       -------------------------- Calibration Block Ports -------------------------
01180       MGT1_ACTIVE_OUT          => mgtA_calibration_active ,
01181       MGT1_DISABLE_IN          => tied_to_ground_i,
01182       MGT1_DRP_RESET_IN        => drpA_reset_i,
01183       MGT1_RX_SIGNAL_DETECT_IN => tied_to_vcc_i,
01184       MGT1_TX_SIGNAL_DETECT_IN => tied_to_vcc_i,
01185       ----------------------------- Calibration Ports ----------------------------
01186       MGT1_RXCLKSTABLE_IN      => tied_to_vcc_i,  --this is taken into account in reset logic
01187       MGT1_TXCLKSTABLE_IN      => tied_to_vcc_i,  --this is taken into account in reset logic
01188       --------------------- Dynamic Reconfiguration Port (DRP) -------------------
01189       MGT1_DADDR_IN            => tied_to_ground_vec_i (7 downto 0),
01190       MGT1_DCLK_IN             => clk_drp_in_i,
01191       MGT1_DEN_IN              => tied_to_ground_i ,
01192       MGT1_DI_IN               => tied_to_ground_vec_i (15 downto 0),
01193       MGT1_DO_OUT              => open,
01194       MGT1_DRDY_OUT            => open,
01195       MGT1_DWE_IN              => tied_to_ground_i ,
01196       -------------------------------- Global Ports ------------------------------
01197       MGT1_LOOPBACK_IN         => tied_to_ground_vec_i (1 downto 0),  --internal serial loopback
01198       MGT1_POWERDOWN_IN        => tied_to_ground_i,
01199       MGT1_TXINHIBIT_IN        => mgt_tx_inhibit_i,
01200       ------------------------ Out of Band Signalling Ports ----------------------
01201       MGT1_RXSIGDET_OUT        => mgtA_OOBsigdet_i,
01202       MGT1_TXENOOB_IN          => mgtA_OOBsigsen_i,
01203       ---------------------------------- PLL Lock --------------------------------
01204       MGT1_RXLOCK_OUT          => mgtA_rxlock_i,
01205       MGT1_TXLOCK_OUT          => mgtA_txlock_i,
01206       --------------------------- Polarity Control Ports -------------------------
01207       MGT1_RXPOLARITY_IN       => tied_to_ground_i,
01208       MGT1_TXPOLARITY_IN       => tied_to_ground_i,
01209       ---------------------------- Ports for Simulation --------------------------
01210       MGT1_COMBUSIN_IN         => tile0_combusout_b_i,
01211       MGT1_COMBUSOUT_OUT       => tile0_combusout_a_i,
01212       ------------------------------ Reference Clocks ----------------------------
01213       MGT1_REFCLK1_IN          => CLK_RIO_IN,
01214       ----------------------------------- Resets ---------------------------------
01215       MGT1_RXPMARESET_IN       => rxA_pmareset_c,
01216       MGT1_RXRESET_IN          => rxA_reset_c,
01217       MGT1_TXPMARESET_IN       => txA_pmareset_c,
01218       MGT1_TXRESET_IN          => txA_reset_c,
01219       ------------------------------ Serdes Alignment ----------------------------
01220       MGT1_ENMCOMMAALIGN_IN    => mgtA_enmcommaalign_i,
01221       MGT1_ENPCOMMAALIGN_IN    => mgtA_enpcommaalign_i,
01222       MGT1_RXCOMMADET_OUT      => mgtA_rxcommadet_i,
01223       MGT1_RXREALIGN_OUT       => mgtA_rxrealign_i,
01224       -------------------------------- Serial Ports ------------------------------
01225       MGT1_RX1N_IN             => RXN_SATA_IN(1),
01226       MGT1_RX1P_IN             => RXP_SATA_IN(1),
01227       MGT1_TX1N_OUT            => TXN_SATA_OUT(1),
01228       MGT1_TX1P_OUT            => TXP_SATA_OUT(1),
01229       ----------------------------------- Status ---------------------------------
01230       MGT1_RXSTATUS_OUT        => mgtA_rxstatus_i,
01231       ------------------------------ Synchronization -----------------------------
01232       MGT1_RXSYNC_IN           => rxA_sync_i,
01233       MGT1_TXSYNC_IN           => txA_sync_i,
01234       -------------------------------- User Clocks -------------------------------
01235       MGT1_RXRECCLK1_OUT       => mgtA_rxrecclk1_ii,
01236       MGT1_RXRECCLK2_OUT       => mgtA_rxrecclk2_i,
01237       MGT1_RXUSRCLK2_IN        => mgtA_rxrecclk1_i,  --clk2_usr_i,--clk2_usr_i,--mgtA_rxrecclk1_i,
01238       MGT1_TXOUTCLK1_OUT       => mgtA_txoutclk1_i,
01239       MGT1_TXOUTCLK2_OUT       => mgtA_txoutclk2_i,
01240       MGT1_TXUSRCLK2_IN        => clk2_usr_i
01241       );
01242 
01243 end sata_arc;
01244