EVENT_cnt.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/EVENT_cnt.vhd,v $
--*  $Revision: 1.8.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;







entity EVENT_cnt is
  port (
    CLK          : in  std_logic;
    RESET        : in  std_logic;
    L1A          : in  std_logic;
    ECR          : in  std_logic;
    ECR_LOAD     : in  std_logic_vector (7 downto 0);
    ECR_LOAD_EN  : in  std_logic;
    L1A_LOAD     : in  std_logic_vector (23 downto 0);
    L1A_LOAD_EN  : in  std_logic;
    START_RUN    : in  std_logic;
    EXT_EVENT_ID : out std_logic_vector (31 downto 0));


  attribute use_dsp48              : string;

  attribute use_dsp48 of EVENT_cnt : entity is "yes";

end EVENT_cnt;







architecture EVENT_cnt_arc of EVENT_cnt is

  signal l1a_i    : std_logic_vector (23 downto 0) := (others => '1');
  signal ecr_i    : std_logic_vector (7 downto 0)  := (others => '0');
  signal l1a_edge : std_logic                      := '0';
  signal l1a_del  : std_logic                      := '0';
  signal l1a_del2 : std_logic                      := '0';
  signal ecr_edge : std_logic                      := '0';
  signal ecr_del  : std_logic                      := '0';
  signal ecr_inc  : std_logic                      := '0';


  component edge
    port (
      CLK   : in  std_logic;
      A     : in  std_logic;
      PULSE : out std_logic);
  end component;

begin

  EXT_EVENT_ID <= ecr_i & l1a_i;
  l1a_del      <= l1a_edge when rising_edge(CLK);
  l1a_del2     <= l1a_del  when rising_edge(CLK);
  ecr_del      <= ecr_edge when rising_edge(CLK);
  ecr_inc      <= '0' when (ecr_edge and l1a_del) = '1' else
                  '1' when (l1a_del2 and ecr_del) = '1' else
                  ecr_edge;


  ecr_edge_det : edge
    port map (
      CLK   => CLK ,
      A     => ECR ,
      PULSE => ecr_edge
      );


  l1a_edge_det : edge
    port map (
      CLK   => CLK ,
      A     => L1A ,
      PULSE => l1a_edge
      );


  ECR_cnt : process(CLK, RESET)
  begin
    if CLK'event and CLK = '1' then
      if RESET = '1' or START_RUN = '1' then
        ecr_i <= (others => '0');
      elsif ECR_LOAD_EN = '1' then
        ecr_i <= ECR_LOAD;
      elsif ecr_inc = '1' then
        ecr_i <= ecr_i + 1;
      end if;
    end if;
  end process;


  L1A_cnt : process(CLK, RESET)
  begin
    if CLK'event and CLK = '1' then
      if (RESET or START_RUN) = '1' then
        l1a_i <= (others => '1');
      elsif (l1a_edge and ecr_edge) = '1' then
        l1a_i <= (others => '0');
      elsif ecr_inc = '1' then
        l1a_i <= (others => '1');
      elsif L1A_LOAD_EN = '1' then
        l1a_i <= L1A_LOAD;
      elsif l1a_edge = '1' then
        l1a_i <= l1a_i + 1;
      end if;
    end if;
  end process;
  
end EVENT_cnt_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012