abort_controller.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/div/abort_controller.vhd,v $
--*  $Revision: 1.6.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;



entity abort_controller is
  port (
    CLK         : in  std_logic;
    RES         : in  std_logic;
    WR_EN       : in  std_logic;
    BCID        : in  std_logic_vector(11 downto 0);
    HIGH_GAIN   : in  std_logic_vector(3 downto 0);
    LOW_GAIN    : in  std_logic_vector(3 downto 0);
    CHECK_EN    : in  std_logic;
    BCID_R      : in  std_logic_vector(11 downto 0);
    HIGH_GAIN_R : in  std_logic_vector(3 downto 0);
    LOW_GAIN_R  : in  std_logic_vector(3 downto 0);
    ABORT       : out std_logic
    );
end abort_controller;



architecture abort_controller_arc of abort_controller is

  signal fire_abort      : std_logic                     := '0';
  signal we              : std_logic                     := '0';
  signal compare1        : std_logic                     := '0';
  signal compare2        : std_logic                     := '0';
  signal compare         : std_logic                     := '0';
  signal abort_middle    : std_logic                     := '0';
  signal abort_above     : std_logic                     := '0';
  signal abort_below     : std_logic                     := '0';
  signal rdvld           : std_logic                     := '0';
  signal rden            : std_logic                     := '0';
  signal bcid_i          : std_logic_vector(11 downto 0) := (others => '0');
  signal cnt_a           : std_logic_vector(11 downto 0) := (others => '0');
  signal cnt_b           : std_logic_vector(11 downto 0) := (others => '0');
  signal rdbid           : std_logic_vector(11 downto 0) := (others => '0');
  signal data_i          : std_logic_vector(5 downto 0)  := (others => '0');
  signal data_out_i      : std_logic_vector(5 downto 0)  := (others => '0');
  signal low_hits        : std_logic_vector(2 downto 0)  := (others => '0');
  signal high_hits       : std_logic_vector(2 downto 0)  := (others => '0');
  signal rlow_hits       : std_logic_vector(2 downto 0)  := (others => '0');
  signal rhigh_hits      : std_logic_vector(2 downto 0)  := (others => '0');
  signal rlow_hits2      : std_logic_vector(2 downto 0)  := (others => '0');
  signal rhigh_hits2     : std_logic_vector(2 downto 0)  := (others => '0');
  signal rlow_hits3      : std_logic_vector(2 downto 0)  := (others => '0');
  signal rhigh_hits3     : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_low_hits   : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_high_hits  : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_low_hits2  : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_high_hits2 : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_low_hits3  : std_logic_vector(2 downto 0)  := (others => '0');
  signal read_high_hits3 : std_logic_vector(2 downto 0)  := (others => '0');
  signal mid_high_cnt    : std_logic_vector(4 downto 0)  := (others => '0');
  signal mid_low_cnt     : std_logic_vector(4 downto 0)  := (others => '0');
  signal blw_high_cnt    : std_logic_vector(4 downto 0)  := (others => '0');
  signal blw_low_cnt     : std_logic_vector(4 downto 0)  := (others => '0');
  signal abv_high_cnt    : std_logic_vector(4 downto 0)  := (others => '0');
  signal abv_low_cnt     : std_logic_vector(4 downto 0)  := (others => '0');

  alias RESET is RES;


  component abort_buffer
    port (
      addra : in  std_logic_vector(11 downto 0);
      addrb : in  std_logic_vector(11 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(5 downto 0);
      doutb : out std_logic_vector(5 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      wea   : in  std_logic);
  end component;

begin  -- abort_controller_arc

  ABORT <= fire_abort or abort_middle;  -- or abort_above or abort_below;


  fire : process (CLK, RES)
    variable lowcnt : std_logic_vector(2 downto 0) := "000";
  begin  -- process fire
    if RES = '1' then                   -- asynchronous reset (active high)
      fire_abort <= '0';
      lowcnt     := "000";
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      fire_abort <= '0';
      lowcnt     := "000";
      if (HIGH_GAIN(0) and HIGH_GAIN(1) and HIGH_GAIN(2) and HIGH_GAIN(3)) = '1' then
        lowcnt := conv_std_logic_vector(conv_integer(LOW_GAIN(0)) + conv_integer(LOW_GAIN(1)) + conv_integer(LOW_GAIN(2)) + conv_integer(LOW_GAIN(3)), 3);
        if lowcnt >= 3 then
          fire_abort <= '1';
        else
          lowcnt     := "000";
          fire_abort <= '0';
        end if;
      else
        lowcnt     := "000";
        fire_abort <= '0';
      end if;
    end if;
  end process fire;

  we <= not RES and WR_EN;


  buf_i : abort_buffer
    port map
    (
      addra => cnt_a,
      addrb => cnt_b,
      clka  => CLK ,
      clkb  => CLK ,
      dina  => data_i,
      doutb => data_out_i,
      ena   => '1' ,
      enb   => rden,
      wea   => we 
      );


  addr_gen_a : process(CLK)
  begin
    if CLK'event and CLK = '1' then
      if RES = '1' then
        cnt_a  <= (others => '0');
        data_i <= (others => '0');
        bcid_i <= (others => '0');
      else
        if WR_EN = '1' then
          bcid_i <= BCID;
          cnt_a  <= bcid_i;
          data_i <= high_hits & low_hits;
        end if;
      end if;
    end if;
  end process addr_gen_a;


  low_cnt : process (CLK, RESET)
  begin  -- process low_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      low_hits <= "000";
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if WR_EN = '1' then
        low_hits <= conv_std_logic_vector(conv_integer(LOW_GAIN(0)) + conv_integer(LOW_GAIN(1)) + conv_integer(LOW_GAIN(2)) + conv_integer(LOW_GAIN(3)), 3);
      end if;
    end if;
  end process low_cnt;


  high_cnt : process (CLK, RESET)
  begin  -- process high_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      high_hits <= "000";
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if WR_EN = '1' then
        high_hits <= conv_std_logic_vector(conv_integer(HIGH_GAIN(0)) + conv_integer(HIGH_GAIN(1)) + conv_integer(HIGH_GAIN(2)) + conv_integer(HIGH_GAIN(3)), 3);
      end if;
    end if;
  end process high_cnt;


  rlow_cnt : process (CLK, RESET)
  begin  -- process rlow_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      rlow_hits <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if CHECK_EN = '1' then
        rlow_hits <= conv_std_logic_vector(conv_integer(LOW_GAIN_R(0)) + conv_integer(LOW_GAIN_R(1)) + conv_integer(LOW_GAIN_R(2)) + conv_integer(LOW_GAIN_R(3)), 3);
      end if;
    end if;
  end process rlow_cnt;


  rhigh_cnt : process (CLK, RESET)
  begin  -- process rhigh_cnt
    if RESET = '1' then                 -- asynchronous reset (active high)
      rhigh_hits <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if CHECK_EN = '1' then
        rhigh_hits <= conv_std_logic_vector(conv_integer(HIGH_GAIN_R(0)) + conv_integer(HIGH_GAIN_R(1)) + conv_integer(HIGH_GAIN_R(2)) + conv_integer(HIGH_GAIN_R(3)), 3);
      end if;
    end if;
  end process rhigh_cnt;

  rlow_hits2      <= rlow_hits              when rising_edge(CLK);  -- below
  rlow_hits3      <= rlow_hits2             when rising_edge(CLK);  -- above
  rhigh_hits2     <= rhigh_hits             when rising_edge(CLK);  -- below
  rhigh_hits3     <= rhigh_hits2            when rising_edge(CLK);  -- above
  compare1        <= CHECK_EN               when rising_edge(CLK);  -- enable middle
  compare2        <= compare1               when rising_edge(CLK);  -- enable below
  compare         <= compare2               when rising_edge(CLK);  -- enable above
  read_high_hits2 <= read_high_hits         when rising_edge(CLK);  -- below
  read_low_hits2  <= read_low_hits          when rising_edge(CLK);  -- below
  read_high_hits3 <= read_high_hits2        when rising_edge(CLK);  -- above
  read_low_hits3  <= read_low_hits2         when rising_edge(CLK);  -- above
  read_high_hits  <= data_out_i(5 downto 3) when rdvld = '1' else "000";  -- middle
  read_low_hits   <= data_out_i(2 downto 0) when rdvld = '1' else "000";  -- middle

  rden  <= not RES and (CHECK_EN or compare1 or compare2);
  rdvld <= rden   when rising_edge(CLK);
  rdbid <= BCID_R when CHECK_EN = '1' else
           BCID_R-1 when compare1 = '1' else
           BCID_R+1 when compare2 = '1' else
           (others => '0');
  cnt_b <= rdbid when RES = '0' else (others => '0');


  comp_mid : process (CLK, RESET)
  begin  -- process comp_mid
    if RESET = '1' then                 -- asynchronous reset (active high)
      abort_middle <= '0';
      mid_high_cnt <= (others => '0');
      mid_low_cnt  <= (others => '0');
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      abort_middle <= '0';
      if compare1 = '1' then
        mid_high_cnt <= conv_std_logic_vector(conv_integer(rhigh_hits) + conv_integer(read_high_hits), 5);
        mid_low_cnt  <= conv_std_logic_vector(conv_integer(rlow_hits) + conv_integer(read_low_hits), 5);
      else
        mid_high_cnt <= (others => '0');
        mid_low_cnt  <= (others => '0');
      end if;
      if mid_low_cnt >= 3 and mid_high_cnt >= 4 then
        abort_middle <= '1';
      else
        abort_middle <= '0';
      end if;
    end if;
  end process comp_mid;


  comp_blw : process (CLK, RESET)
  begin  -- process comp_blw
    if RESET = '1' then                 -- asynchronous reset (active high)
      abort_below <= '0';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if compare2 = '1' then
        blw_high_cnt <= conv_std_logic_vector(conv_integer(rhigh_hits2) + conv_integer(read_high_hits2), 5);
        blw_low_cnt  <= conv_std_logic_vector(conv_integer(rlow_hits2) + conv_integer(read_low_hits2), 5);
      else
        blw_high_cnt <= (others => '0');
        blw_low_cnt  <= (others => '0');
      end if;
      if blw_low_cnt >= 3 and blw_high_cnt >= 4 then
        abort_below <= '1';
      else
        abort_below <= '0';
      end if;
    end if;
  end process comp_blw;


  comp_abv : process (CLK, RESET)
  begin  -- process comp_abv
    if RESET = '1' then                 -- asynchronous reset (active high)
      abort_above <= '0';
    elsif CLK'event and CLK = '1' then  -- rising clock edge
      if compare = '1' then
        abv_high_cnt <= conv_std_logic_vector(conv_integer(rhigh_hits3) + conv_integer(read_high_hits3), 5);
        abv_low_cnt  <= conv_std_logic_vector(conv_integer(rlow_hits3) + conv_integer(read_low_hits3), 5);
      else
        abv_high_cnt <= (others => '0');
        abv_low_cnt  <= (others => '0');
      end if;
      if abv_low_cnt >= 3 and abv_high_cnt >= 4 then
        abort_above <= '1';
      else
        abort_above <= '0';
      end if;
    end if;
  end process comp_abv;
  
end abort_controller_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:02 2008 for BCM-AAA by  1.5.7.1-20081012