shift_reg.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /afs/cern.ch/project/cvs/reps/bcmfpga/bcm_aaa/bcm_aaa/main/bcm_aaa.vhd,
--v $
--*  $Revision: 1.1.2.4 $                                         *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:45 $                              *


--*                                                            *
--**************************************************************
--------------------------------------------------------------------------------
--     This file is owned and controlled by Xilinx and must be used           --
--     solely for design, simulation, implementation and creation of          --
--     design files limited to Xilinx devices or technologies. Use            --
--     with non-Xilinx devices or technologies is expressly prohibited        --
--     and immediately terminates your license.                               --
--                                                                            --
--     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"          --
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--     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION        --
--     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION            --
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--     (c) Copyright 1995-2007 Xilinx, Inc.                                   --
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--------------------------------------------------------------------------------
-- You must compile the wrapper file shift_reg.vhd when simulating
-- the core, shift_reg. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".

-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).


library ieee;

use ieee.std_logic_1164.all;
-- synthesis translate_off
library XilinxCoreLib;
-- synthesis translate_on


entity shift_reg is
  port
    (
      addra : in  std_logic_vector(7 downto 0);
      addrb : in  std_logic_vector(7 downto 0);
      clka  : in  std_logic;
      clkb  : in  std_logic;
      dina  : in  std_logic_vector(31 downto 0);
      doutb : out std_logic_vector(31 downto 0);
      ena   : in  std_logic;
      enb   : in  std_logic;
      wea   : in  std_logic
      );
end shift_reg;


architecture shift_reg_a of shift_reg is
-- synthesis translate_off

  component wrapped_shift_reg
    port
      (
        addra : in  std_logic_vector(7 downto 0);
        addrb : in  std_logic_vector(7 downto 0);
        clka  : in  std_logic;
        clkb  : in  std_logic;
        dina  : in  std_logic_vector(31 downto 0);
        doutb : out std_logic_vector(31 downto 0);
        ena   : in  std_logic;
        enb   : in  std_logic;
        wea   : in  std_logic
        );
  end component;


  for all : wrapped_shift_reg use entity XilinxCoreLib.blkmemdp_v6_3(behavioral)
    generic map
    (
      c_reg_inputsb           => 0,
      c_reg_inputsa           => 0,
      c_has_ndb               => 0,
      c_has_nda               => 0,
      c_ytop_addr             => "1024",
      c_has_rfdb              => 0,
      c_has_rfda              => 0,
      c_ywea_is_high          => 1,
      c_yena_is_high          => 1,
      c_yclka_is_rising       => 1,
      c_yhierarchy            => "hierarchy1",
      c_ysinita_is_high       => 1,
      c_ybottom_addr          => "0",
      c_width_b               => 32,
      c_width_a               => 32,
      c_sinita_value          => "0",
      c_sinitb_value          => "0",
      c_limit_data_pitch      => 18,
      c_write_modeb           => 0,
      c_write_modea           => 0,
      c_has_rdyb              => 0,
      c_yuse_single_primitive => 0,
      c_has_rdya              => 0,
      c_addra_width           => 8,
      c_addrb_width           => 8,
      c_has_limit_data_pitch  => 0,
      c_default_data          => "0",
      c_pipe_stages_b         => 0,
      c_yweb_is_high          => 1,
      c_yenb_is_high          => 1,
      c_pipe_stages_a         => 0,
      c_yclkb_is_rising       => 1,
      c_yydisable_warnings    => 1,
      c_enable_rlocs          => 0,
      c_ysinitb_is_high       => 1,
      c_has_web               => 0,
      c_has_default_data      => 1,
      c_has_sinitb            => 0,
      c_has_wea               => 1,
      c_has_sinita            => 0,
      c_has_dinb              => 0,
      c_has_dina              => 1,
      c_ymake_bmm             => 0,
      c_sim_collision_check   => "NONE",
      c_has_enb               => 1,
      c_has_ena               => 1,
      c_depth_b               => 256,
      c_mem_init_file         => "mif_file_16_1",
      c_depth_a               => 256,
      c_has_doutb             => 1,
      c_has_douta             => 0,
      c_yprimitive_type       => "32kx1"
      );
-- synthesis translate_on
begin
-- synthesis translate_off

  U0 : wrapped_shift_reg
    port map (
      addra => addra,
      addrb => addrb,
      clka  => clka,
      clkb  => clkb,
      dina  => dina,
      doutb => doutb,
      ena   => ena ,
      enb   => enb ,
      wea   => wea 
      );
-- synthesis translate_on

end shift_reg_a;

---

Author: M.Niegl

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