ddr_chksum_accu.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/eth/Attic/ddr_chksum_accu.vhd,v $
--*  $Revision: 1.1.2.4 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:46 $                              *



--*                                                            *
--**************************************************************
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.
--------------------------------------------------------------------------------
--   ____  ____ 
--  /   /\/   / 
-- /___/  \  /    Vendor: Xilinx 
-- \   \   \/     Version : 9.2.04i
--  \   \         Application : xaw2vhdl
--  /   /         Filename : ddr_chksum_accu.vhd
-- /___/   /\     Timestamp : 10/17/2008 11:01:52
-- \   \  /  \ 
--  \___\/\___\ 
--
--Command: xaw2vhdl-st C:\FPGA\coregen\dsp_chksum\ddr_chksum_accu.xaw C:\FPGA\coregen\dsp_chksum\ddr_chksum_accu
--Design Name: ddr_chksum_accu
--Device: xc4vfx60-ff1152-11
--
-- Module ddr_chksum_accu
-- Generated by Xilinx Architecture Wizard
-- Written for synthesis tool: XST


library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

library unisim;
use unisim.Vcomponents.all;


entity ddr_chksum_accu is
  port
    (
      AB_IN      : in  std_logic_vector (31 downto 0);
      CEA_IN     : in  std_logic;
      CEB_IN     : in  std_logic;
      CECTRL_IN  : in  std_logic;
      CEM_IN     : in  std_logic;
      CEP_IN     : in  std_logic;
      CLK_IN     : in  std_logic;
      LOAD_IN    : in  std_logic;
      RSTA_IN    : in  std_logic;
      RSTB_IN    : in  std_logic;
      RSTCTRL_IN : in  std_logic;
      RSTM_IN    : in  std_logic;
      RSTP_IN    : in  std_logic;
      BCOUT_OUT  : out std_logic_vector (17 downto 0);
      PCOUT_OUT  : out std_logic_vector (47 downto 0);
      P_OUT      : out std_logic_vector (47 downto 0)
      );
end ddr_chksum_accu;


architecture BEHAVIORAL of ddr_chksum_accu is
  signal GND_BUS_2  : std_logic_vector (1 downto 0);
  signal GND_BUS_18 : std_logic_vector (17 downto 0);
  signal GND_BUS_48 : std_logic_vector (47 downto 0);
  signal GND_OPMODE : std_logic;
  signal VCC_OPMODE : std_logic;
begin
  GND_BUS_2(1 downto 0)   <= "00";
  GND_BUS_18(17 downto 0) <= "000000000000000000";
  GND_BUS_48(47 downto 0) <=
    "000000000000000000000000000000000000000000000000";
  GND_OPMODE <= '0';
  VCC_OPMODE <= '1';
  DSP48_ACC : DSP48
    generic map
    (
      AREG          => 1,
      BREG          => 1,
      CREG          => 0,
      PREG          => 1,
      MREG          => 1,
      OPMODEREG     => 1,
      SUBTRACTREG   => 0,
      CARRYINSELREG => 0,
      CARRYINREG    => 0,
      B_INPUT       => "DIRECT",
      LEGACY_MODE   => "NONE")
    port map
    (
      A(17)                  => AB_IN(31),
      A(16)                  => AB_IN(31),
      A(15)                  => AB_IN(31),
      A(14)                  => AB_IN(31),
      A(13 downto 0)         => AB_IN (31 downto 18),
      B(17 downto 0)         => AB_IN (17 downto 0),
      BCIN(17 downto 0)      => GND_BUS_18(17 downto 0),
      C(47 downto 0)         => GND_BUS_48(47 downto 0),
      CARRYIN                => GND_OPMODE,
      CARRYINSEL(1 downto 0) => GND_BUS_2(1 downto 0),
      CEA                    => CEA_IN,
      CEB                    => CEB_IN,
      CEC                    => VCC_OPMODE,
      CECARRYIN              => GND_OPMODE ,
      CECINSUB               => VCC_OPMODE,
      CECTRL                 => CECTRL_IN,
      CEM                    => CEM_IN,
      CEP                    => CEP_IN,
      CLK                    => CLK_IN,
      OPMODE(6)              => GND_OPMODE ,
      OPMODE(5)              => LOAD_IN ,
      OPMODE(4)              => GND_OPMODE ,
      OPMODE(3)              => GND_OPMODE ,
      OPMODE(2)              => GND_OPMODE ,
      OPMODE(1)              => VCC_OPMODE ,
      OPMODE(0)              => VCC_OPMODE ,
      PCIN(47 downto 0)      => GND_BUS_48(47 downto 0),
      RSTA                   => RSTA_IN,
      RSTB                   => RSTB_IN,
      RSTC                   => GND_OPMODE,
      RSTCARRYIN             => GND_OPMODE ,
      RSTCTRL                => RSTCTRL_IN,
      RSTM                   => RSTM_IN,
      RSTP                   => RSTP_IN,
      SUBTRACT               => GND_OPMODE,
      BCOUT(17 downto 0)     => BCOUT_OUT(17 downto 0),
      P(47 downto 0)         => P_OUT (47 downto 0),
      PCOUT(47 downto 0)     => PCOUT_OUT(47 downto 0)
      );

end BEHAVIORAL;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012