BCM-AAA: rio2mem.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/main/rio2mem.vhd,v $
00015 --*  $Revision: 3.100.2.14 $                                          *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 19:00:04 $                              *
00019 
00020 
00021 --*                                                            *
00022 --**************************************************************
00023 
00024 library ieee;
00025 
00026 use ieee.std_logic_1164.all;
00027 
00028 use ieee.std_logic_arith.all;
00029 
00030 use ieee.std_logic_unsigned.all;
00031 
00032 library unisim;
00033 
00034 use unisim.vcomponents.all;
00035 library work;
00036 use work.udp_addresses.all;
00037 use work.main_components.all;
00038 use work.build_parameters.all;
00039 
00040 
00041 
00042 
00043 
00044 
00045 
00046 
00047 
00048 
00049 entity rio2mem is
00050   port (BCLK                : in    std_logic;
00051         RIOCLK_1            : in    std_logic;
00052         RIOCLK_2            : in    std_logic;
00053         BCLK2X_P            : in    std_logic;
00054         BCLK2X_N            : in    std_logic;
00055         BCLK4X_P            : in    std_logic;
00056         BCLK4X_N            : in    std_logic;
00057         REFCLK_P            : in    std_logic;
00058         REFCLK_N            : in    std_logic;
00059         EMAC_CLK            : in    std_logic;
00060         DDRCLK              : in    std_logic;
00061         SATA_REF_CLK        : in    std_logic;
00062         SATA_LOGIC_CLK      : in    std_logic;
00063         CLK_50              : in    std_logic;
00064         CLK_HZ              : in    std_logic;
00065         XT_CLK_DET          : in    std_logic;
00066         GP_ERR_FLAG         : out   std_logic;
00067         MODE                : out   std_logic;
00068         RESET               : in    std_logic;
00069         RES_PC              : out   std_logic;
00070         TRIG_PC             : out   std_logic;
00071         STOP_PC             : out   std_logic;
00072         FORCE_PM            : out   std_logic;
00073         CALIBRATE_RIOS      : in    std_logic;
00074         CHECK               : out   std_logic;
00075         LOCK_OUT            : out   std_logic;
00076         MAC_LOCK            : out   std_logic;
00077         SEND_ARP_ANN        : in    std_logic;
00078         RIOS_READY          : out   std_logic;
00079         CAL_DONE            : out   std_logic;
00080         SATA_OK             : out   std_logic;
00081         READ_OUT            : in    std_logic;
00082         READ_DONE           : out   std_logic;
00083         READ_READY          : in    std_logic;
00084         READ_OVER           : in    std_logic;
00085         TRIGGER_INHIBIT_N   : out   std_logic;
00086         MAIN_FSM_ST         : in    std_logic_vector(7 downto 0);
00087         RXP_SATA_IN         : in    std_logic_vector (1 downto 0);
00088         RXN_SATA_IN         : in    std_logic_vector (1 downto 0);
00089         TXP_SATA_OUT        : out   std_logic_vector (1 downto 0);
00090         TXN_SATA_OUT        : out   std_logic_vector (1 downto 0);
00091         RXN_C_IE            : in    std_logic_vector(1 downto 0);
00092         RXP_C_IE            : in    std_logic_vector(1 downto 0);
00093         RXN_C_AH            : in    std_logic_vector(1 downto 0);
00094         RXP_C_AH            : in    std_logic_vector(1 downto 0);
00095         RXN_A_WM            : in    std_logic_vector(1 downto 0);
00096         RXP_A_WM            : in    std_logic_vector(1 downto 0);
00097         RXN_A_HH            : in    std_logic_vector(1 downto 0);
00098         RXP_A_HH            : in    std_logic_vector(1 downto 0);
00099         TXN_C_IE            : out   std_logic_vector(1 downto 0);
00100         TXP_C_IE            : out   std_logic_vector(1 downto 0);
00101         TXN_C_AH            : out   std_logic_vector(1 downto 0);
00102         TXP_C_AH            : out   std_logic_vector(1 downto 0);
00103         TXN_A_WM            : out   std_logic_vector(1 downto 0);
00104         TXP_A_WM            : out   std_logic_vector(1 downto 0);
00105         TXN_A_HH            : out   std_logic_vector(1 downto 0);
00106         TXP_A_HH            : out   std_logic_vector(1 downto 0);
00107         MASK_IRENA          : out   std_logic;
00108         MASK_EWA            : out   std_logic;
00109         MASK_ANDREJ         : out   std_logic;
00110         MASK_HEINZ          : out   std_logic;
00111         MASK_MARKO          : out   std_logic;
00112         MASK_WILLIAM        : out   std_logic;
00113         MASK_HARRIS         : out   std_logic;
00114         MASK_HELMUT         : out   std_logic;
00115         OR_CH1              : out   std_logic;
00116         OR_CH2              : out   std_logic;
00117         cntrl0_DDR_A        : out   std_logic_vector(12 downto 0);
00118         cntrl0_DDR_BA       : out   std_logic_vector(1 downto 0);
00119         cntrl0_DDR_CKE      : out   std_logic;
00120         cntrl0_DDR_CS_N     : out   std_logic;
00121         cntrl0_DDR_RAS_N    : out   std_logic;
00122         cntrl0_DDR_CAS_N    : out   std_logic;
00123         cntrl0_DDR_WE_N     : out   std_logic;
00124         cntrl0_DDR_DM       : out   std_logic_vector(3 downto 0);
00125         cntrl0_DDR_CK       : out   std_logic;
00126         cntrl0_DDR_CK_N     : out   std_logic;
00127         cntrl0_DDR_DQ       : inout std_logic_vector(31 downto 0);
00128         cntrl0_DDR_DQS      : inout std_logic_vector(3 downto 0);
00129         cntrl0_DDR2_A       : out   std_logic_vector(13 downto 0);
00130         cntrl0_DDR2_BA      : out   std_logic_vector(1 downto 0);
00131         cntrl0_DDR2_RAS_N   : out   std_logic;
00132         cntrl0_DDR2_CAS_N   : out   std_logic;
00133         cntrl0_DDR2_WE_N    : out   std_logic;
00134         cntrl0_DDR2_RESET_N : out   std_logic;
00135         cntrl0_DDR2_CS_N    : out   std_logic;
00136         cntrl0_DDR2_ODT     : out   std_logic;
00137         cntrl0_DDR2_CKE     : out   std_logic;
00138         cntrl0_DDR2_DM      : out   std_logic_vector(7 downto 0);
00139         cntrl0_DDR2_CK      : out   std_logic;
00140         cntrl0_DDR2_CK_N    : out   std_logic;
00141         cntrl0_DDR2_DQ      : inout std_logic_vector(63 downto 0);
00142         cntrl0_DDR2_DQS     : inout std_logic_vector(7 downto 0);
00143         cntrl0_DDR2_DQS_N   : inout std_logic_vector(7 downto 0);
00144         gmii_rx_clk         : in    std_logic;
00145         gmii_rx_dv          : in    std_logic;
00146         gmii_rx_er          : in    std_logic;
00147         gmii_rxd            : in    std_logic_vector(0 to 7);
00148         mdio                : inout std_logic;
00149         mii_tx_clk          : in    std_logic;
00150         gmii_tx_en          : out   std_logic;
00151         gmii_tx_er          : out   std_logic;
00152         gmii_txd            : out   std_logic_vector(0 to 3);
00153         MDC_0               : out   std_logic;
00154         phy_rst_n           : out   std_logic;
00155         TRIG_EXT            : in    std_logic;
00156         GOTO_RD             : out   std_logic;
00157         CAPTURE             : in    std_logic;
00158         SL_LFF              : in    std_logic;
00159         SL_LDOWN            : in    std_logic;
00160         SL_LRL              : in    std_logic_vector(3 downto 0);
00161         SL_UCLK             : out   std_logic;
00162         SL_UD               : out   std_logic_vector(31 downto 0);
00163         SL_URESET           : out   std_logic;
00164         SL_UTEST            : out   std_logic;
00165         SL_UWEN             : out   std_logic;
00166         SL_UCTRL            : out   std_logic;
00167         SL_UDW              : out   std_logic_vector(1 downto 0);
00168         BUSY                : out   std_logic;
00169         ORBIT               : in    std_logic;
00170         BCR                 : in    std_logic;
00171         L1A                 : in    std_logic;
00172         ECR                 : in    std_logic;
00173         TRIGGER_TYPE        : in    std_logic_vector(8 downto 1);
00174         CTP                 : out   std_logic_vector(9 downto 1);
00175         INJECT_PERM_1       : out   std_logic;
00176         INJECT_PERM_2       : out   std_logic;
00177         BEAM_PERM_1         : out   std_logic;
00178         BEAM_PERM_2         : out   std_logic;
00179         DSS_WARNING_1       : out   std_logic;
00180         DSS_WARNING_2       : out   std_logic;
00181         DSS_ABORT_1         : out   std_logic;
00182         DSS_ABORT_2         : out   std_logic;
00183         L1A_DISP            : in    std_logic;
00184         RIOERR              : out   std_logic;
00185         RIOERR_TYPE         : out   std_logic_vector(7 downto 0);
00186         SEND_ERR_MSG        : in    std_logic;
00187         ERROR_CODE          : in    std_logic_vector(7 downto 0)
00188         );
00189 end rio2mem;
00190 
00191 
00192 
00193 
00194 
00195 
00196 
00197 
00198 architecture rio2mem_arc of rio2mem is
00199 
00200 --*************************** Signal Declarations *****************************
00201   signal cs                    : read_out_states;
00202   signal ems                   : emac_states                    := e_idle;
00203   signal ddr2_clk              : std_logic                      := '0';
00204   signal emac_clk_buf          : std_logic                      := '0';
00205   signal ctor_clk              : std_logic                      := '0';
00206   signal chkclk_r              : std_logic                      := '0';
00207   signal chkclk_p              : std_logic                      := '0';
00208   signal rios_work             : std_logic                      := '0';
00209   signal fetch_proc            : std_logic                      := '0';
00210   signal en_proc               : std_logic                      := '0';
00211   signal en_cnt_proc           : std_logic                      := '0';
00212   signal en_rd_proc            : std_logic                      := '0';
00213   signal empty_proc            : std_logic                      := '0';
00214   signal rw_proc_i             : std_logic                      := '0';
00215   signal proc_vld              : std_logic                      := '0';
00216   signal fetch_raw             : std_logic                      := '0';
00217   signal en_raw                : std_logic                      := '0';
00218   signal en_cnt_raw            : std_logic                      := '0';
00219   signal en_rd_raw             : std_logic                      := '0';
00220   signal empty_raw             : std_logic                      := '0';
00221   signal rw_raw_i              : std_logic                      := '0';
00222   signal raw_vld               : std_logic                      := '0';
00223   signal burstind_raw          : std_logic                      := '0';
00224   signal burstind_proc         : std_logic                      := '0';
00225   signal fetch_int             : std_logic                      := '0';
00226   signal fetch_int_latch       : std_logic                      := '0';
00227   signal get_eth_byte          : std_logic                      := '0';
00228   signal fetch_raw_eth         : std_logic                      := '0';
00229   signal fetch_proc_eth        : std_logic                      := '0';
00230   signal fetch_int_eth         : std_logic                      := '0';
00231   signal wr_eth_buf_int        : std_logic                      := '0';
00232   signal wr_buf_raw            : std_logic                      := '0';
00233   signal wr_buf_proc           : std_logic                      := '0';
00234   signal wr_buf_raw_i          : std_logic                      := '0';
00235   signal wr_buf_proc_i         : std_logic                      := '0';
00236   signal datatype_i            : std_logic                      := '0';
00237   signal mem_reset             : std_logic                      := '0';
00238   signal mem_reset_short       : std_logic                      := '0';
00239   signal trans_complete        : std_logic                      := '0';
00240   signal proc_trans_complete   : std_logic                      := '0';
00241   signal raw_trans_complete    : std_logic                      := '0';
00242   signal pkt_full              : std_logic                      := '0';
00243   signal pktdone               : std_logic                      := '0';
00244   signal start_rdout           : std_logic                      := '0';
00245   signal start_rdout_ext       : std_logic                      := '0';
00246   signal rios_ready_i          : std_logic                      := '0';
00247   signal clr_ddr               : std_logic                      := '0';
00248   signal clr_ddr2              : std_logic                      := '0';
00249   signal clear_raw             : std_logic                      := '0';
00250   signal clear_int             : std_logic                      := '0';
00251   signal clear_proc            : std_logic                      := '0';
00252   signal wr_buf_int            : std_logic                      := '0';
00253   signal ethbufres_proc        : std_logic                      := '0';
00254   signal ethbufres_raw         : std_logic                      := '0';
00255   signal ethbufres_int         : std_logic                      := '0';
00256   signal ethbufres_proc_i      : std_logic                      := '0';
00257   signal ethbufres_raw_i       : std_logic                      := '0';
00258   signal ethbufres_int_i       : std_logic                      := '0';
00259   signal delta_vld_a           : std_logic                      := '0';
00260   signal delta_vld_backa       : std_logic                      := '0';
00261   signal delta_vld_backc       : std_logic                      := '0';
00262   signal delta_vld2_a          : std_logic                      := '0';
00263   signal delta_vld_b           : std_logic                      := '0';
00264   signal delta_vld2_b          : std_logic                      := '0';
00265   signal delta_vld_c           : std_logic                      := '0';
00266   signal delta_vld2_c          : std_logic                      := '0';
00267   signal delta_vld_d           : std_logic                      := '0';
00268   signal delta_vld2_d          : std_logic                      := '0';
00269   signal data_rod_vld          : std_logic                      := '0';
00270   signal data_rod_vld_i        : std_logic                      := '0';
00271   signal cal_irena_i           : std_logic                      := '0';
00272   signal cal_ewa_i             : std_logic                      := '0';
00273   signal cal_andrej_i          : std_logic                      := '0';
00274   signal cal_heinz_i           : std_logic                      := '0';
00275   signal cal_marko_i           : std_logic                      := '0';
00276   signal cal_william_i         : std_logic                      := '0';
00277   signal cal_harris_i          : std_logic                      := '0';
00278   signal cal_helmut_i          : std_logic                      := '0';
00279   signal err_msg_complete      : std_logic                      := '0';
00280   signal eth_en_i              : std_logic                      := '0';
00281   signal err_eth_en_i          : std_logic                      := '0';
00282   signal fetch_err_eth         : std_logic                      := '0';
00283   signal swtoerr_i             : std_logic                      := '0';
00284   signal swtoerr_ff            : std_logic                      := '0';
00285   signal over_proc_i           : std_logic                      := '0';
00286   signal over_raw_i            : std_logic                      := '0';
00287   signal raw_cnt_reset         : std_logic                      := '0';
00288   signal proc_cnt_reset        : std_logic                      := '0';
00289   signal en_riomonitor         : std_logic                      := '0';
00290   signal pkt_rddone_proc       : std_logic                      := '0';
00291   signal pkt_rddone_raw        : std_logic                      := '0';
00292   signal pkt_rddone_proc1      : std_logic                      := '0';
00293   signal pkt_rddone_raw1       : std_logic                      := '0';
00294   signal get_raw_chksum        : std_logic                      := '0';
00295   signal get_proc_chksum       : std_logic                      := '0';
00296   signal get_chksum            : std_logic                      := '0';
00297   signal sata_tx_a_lock_i      : std_logic                      := '0';
00298   signal sata_tx_b_lock_i      : std_logic                      := '0';
00299   signal sata_rx_a_lock_i      : std_logic                      := '0';
00300   signal sata_rx_b_lock_i      : std_logic                      := '0';
00301   signal sata_tx_a_ready_i     : std_logic                      := '0';
00302   signal sata_rx_a_ready_i     : std_logic                      := '0';
00303   signal sata_tx_b_ready_i     : std_logic                      := '0';
00304   signal sata_rx_b_ready_i     : std_logic                      := '0';
00305   signal sata_data_ready_i     : std_logic                      := '0';
00306   signal sata_data_vld_a       : std_logic                      := '0';
00307   signal sata_error_a          : std_logic                      := '0';
00308   signal sata_data_vld_b       : std_logic                      := '0';
00309   signal sata_error_b          : std_logic                      := '0';
00310   signal sata_error_clk_i      : std_logic                      := '0';
00311   signal sata_eop_generate_i   : std_logic                      := '0';
00312   signal sata_eop_received_i   : std_logic                      := '0';
00313   signal sata_package_ok_i     : std_logic                      := '0';
00314   signal sata_data_send_i      : std_logic                      := '0';
00315   signal sata_data_clk         : std_logic                      := '0';
00316   signal sata_listening_a      : std_logic                      := '0';
00317   signal sata_listening_b      : std_logic                      := '0';
00318   signal sata_package_good_a   : std_logic                      := '0';
00319   signal sata_package_good_b   : std_logic                      := '0';
00320   signal sata_package_bad_a    : std_logic                      := '0';
00321   signal sata_package_bad_b    : std_logic                      := '0';
00322   signal sata_ok_i             : std_logic                      := '0';
00323   signal sl_trig_pc            : std_logic                      := '0';
00324   signal sl_trig_pc_i          : std_logic                      := '0';
00325   signal sl_trig_pc_ii         : std_logic                      := '0';
00326   signal sl_pause              : std_logic                      := '0';
00327   signal sl_pause_i            : std_logic                      := '0';
00328   signal sl_pause_ii           : std_logic                      := '0';
00329   signal buf_pause             : std_logic                      := '0';
00330   signal res_pc_i              : std_logic                      := '0';
00331   signal pc_cmdvld             : std_logic                      := '0';
00332   signal stop_pc_i             : std_logic                      := '0';
00333   signal trig_pc_i             : std_logic                      := '0';
00334   signal fill_buf_i            : std_logic                      := '0';
00335   signal start_run             : std_logic                      := '0';
00336   signal start_run_i           : std_logic                      := '0';
00337   signal start_run_ii          : std_logic                      := '0';
00338   signal dss_ab_i              : std_logic                      := '0';
00339   signal dss_w_i               : std_logic                      := '0';
00340   signal dss_ab_ii             : std_logic                      := '0';
00341   signal dss_w_ii              : std_logic                      := '0';
00342   signal b_perm_i              : std_logic                      := '0';
00343   signal i_perm_i              : std_logic                      := '0';
00344   signal b_perm_ii             : std_logic                      := '0';
00345   signal i_perm_ii             : std_logic                      := '0';
00346   signal lvl1_buf_res          : std_logic                      := '0';
00347   signal rate_block            : std_logic                      := '0';
00348   signal pat_fill              : std_logic                      := '0';
00349   signal en_fill               : std_logic                      := '0';
00350   signal arp_i                 : std_logic                      := '0';
00351   signal arp_ii                : std_logic                      := '0';
00352   signal arp_done              : std_logic                      := '0';
00353   signal mac_lock_i            : std_logic                      := '0';
00354   signal rd_rdy_i              : std_logic                      := '0';
00355   signal busy_ext              : std_logic                      := '1';  -- default to '1' !!!!
00356   signal busy_ext_rs           : std_logic                      := '0';
00357   signal busy_i                : std_logic                      := '0';
00358   signal run_num_en            : std_logic                      := '0';
00359   signal ev_type_en            : std_logic                      := '0';
00360   signal rd_ovr                : std_logic                      := '0';
00361   signal rd_ovr_i              : std_logic                      := '0';
00362   signal rate_reset            : std_logic                      := '0';
00363   signal rate_reset_i          : std_logic                      := '0';
00364   signal get_stats             : std_logic                      := '0';
00365   signal srcid_en              : std_logic                      := '0';
00366   signal algosel_en            : std_logic                      := '0';
00367   signal mask_en               : std_logic                      := '0';
00368   signal second                : std_logic                      := '0';
00369   signal second_active         : std_logic                      := '0';
00370   signal stat_msg_done         : std_logic                      := '0';
00371   signal inc_pktnr             : std_logic                      := '0';
00372   signal ack_vld               : std_logic                      := '0';
00373   signal fetch_stat_eth        : std_logic                      := '0';
00374   signal fetch_tdaq_eth        : std_logic                      := '0';
00375   signal get_stat_chksum       : std_logic                      := '0';
00376   signal get_tdaq_chksum       : std_logic                      := '0';
00377   signal start_pkt             : std_logic                      := '0';
00378   signal start_nxt             : std_logic                      := '0';
00379   signal start_nxt_st          : std_logic                      := '0';
00380   signal start_stat            : std_logic                      := '0';
00381   signal start_pkt_ff          : std_logic                      := '0';
00382   signal pktdone_ff            : std_logic                      := '0';
00383   signal ack_vld_ff            : std_logic                      := '0';
00384   signal en_mem                : std_logic                      := '0';
00385   signal en_stat_mac           : std_logic                      := '0';
00386   signal assemb_stat           : std_logic                      := '0';
00387   signal stat_asm_done_i       : std_logic                      := '0';
00388   signal en_stat_mac_set       : std_logic                      := '0';
00389   signal stat_msg_rd_done      : std_logic                      := '0';
00390   signal tdaq_asm_done_i       : std_logic                      := '0';
00391   signal en_tdaq_mac_set       : std_logic                      := '0';
00392   signal tdaq_msg_rd_done      : std_logic                      := '0';
00393   signal read_out_i            : std_logic                      := '0';
00394   signal set_ctp               : std_logic                      := '0';
00395   signal set_ctp_i             : std_logic                      := '0';
00396   signal set_dss_ab_i          : std_logic                      := '0';
00397   signal set_dss_w_i           : std_logic                      := '0';
00398   signal set_dss_warning       : std_logic                      := '0';
00399   signal set_dss_abort         : std_logic                      := '0';
00400   signal set_injection_permit  : std_logic                      := '0';
00401   signal set_beam_permit       : std_logic                      := '0';
00402   signal dss_warning           : std_logic                      := '0';
00403   signal dss_abort             : std_logic                      := '0';
00404   signal injection_permit      : std_logic                      := '0';
00405   signal beam_permit           : std_logic                      := '0';
00406   signal set_ecr_load_i        : std_logic                      := '0';
00407   signal set_l1a_load_i        : std_logic                      := '0';
00408   signal set_i_perm            : std_logic                      := '0';
00409   signal set_b_perm            : std_logic                      := '0';
00410   signal lf_empty              : std_logic                      := '1';  -- default to 1 !!!
00411   signal lf_full               : std_logic                      := '0';
00412   signal lf_rden               : std_logic                      := '0';
00413   signal lf_rden2              : std_logic                      := '0';
00414   signal lf_wren               : std_logic                      := '0';
00415   signal lf_wren_i             : std_logic                      := '0';
00416   signal lf_wren_ii            : std_logic                      := '0';
00417   signal l1a_done              : std_logic                      := '0';
00418   signal bcr_i                 : std_logic                      := '0';
00419   signal ecr_i                 : std_logic                      := '0';
00420   signal l1a_del               : std_logic                      := '0';
00421   signal l1a_i                 : std_logic                      := '0';
00422   signal l1a_ii                : std_logic                      := '0';
00423   signal l1a_inc               : std_logic                      := '0';
00424   signal lvl1_buf_rden         : std_logic                      := '0';
00425   signal fpgaid_en             : std_logic                      := '0';
00426   signal format_ver_en         : std_logic                      := '0';
00427   signal ecr_force             : std_logic                      := '0';
00428   signal bcr_force             : std_logic                      := '0';
00429   signal force_bcr_i           : std_logic                      := '0';
00430   signal force_ecr_i           : std_logic                      := '0';
00431   signal l1a_force             : std_logic                      := '0';
00432   signal l1a_force_i           : std_logic                      := '0';
00433   signal l1a_force_ii          : std_logic                      := '0';
00434   signal busy_clr              : std_logic                      := '0';
00435   signal ctp_src_i             : std_logic                      := '0';
00436   signal ctp_src_ii            : std_logic                      := '0';
00437   signal ctp_src_en            : std_logic                      := '0';
00438   signal orbit_load_en         : std_logic                      := '0';
00439   signal send_tdaq_status      : std_logic                      := '0';
00440   signal set_orbit             : std_logic                      := '0';
00441   signal dcs_errflag           : std_logic                      := '0';
00442   signal sl_lff_i              : std_logic                      := '1';
00443   signal sl_ldown_i            : std_logic                      := '1';
00444   signal next_l1a              : std_logic                      := '1';
00445   signal next_l1a1             : std_logic                      := '0';
00446   signal get_next_l1a          : std_logic                      := '0';
00447   signal nllatch1              : std_logic                      := '0';
00448   signal nllatch2              : std_logic                      := '0';
00449   signal dss_a_i               : std_logic                      := '0';
00450   signal dss_ab1_i             : std_logic                      := '0';
00451   signal dss_ab2_i             : std_logic                      := '0';
00452   signal dss_wa_i              : std_logic                      := '0';
00453   signal dss_wa1_i             : std_logic                      := '0';
00454   signal dss_wa2_i             : std_logic                      := '0';
00455   signal inj_p_i               : std_logic                      := '0';
00456   signal inj_p1_i              : std_logic                      := '0';
00457   signal inj_p2_i              : std_logic                      := '0';
00458   signal bem_p_i               : std_logic                      := '0';
00459   signal bem_p1_i              : std_logic                      := '0';
00460   signal bem_p2_i              : std_logic                      := '0';
00461   signal sata_dssw             : std_logic                      := '0';
00462   signal sata_dssa             : std_logic                      := '0';
00463   signal sata_iperm            : std_logic                      := '0';
00464   signal sata_bperm            : std_logic                      := '0';
00465   signal tdaq_active           : std_logic                      := '0';
00466   signal tdaq_msg_done         : std_logic                      := '0';
00467   signal assemb_tdaq           : std_logic                      := '0';
00468   signal en_tdaq_mac           : std_logic                      := '0';
00469   signal pktdone_long          : std_logic                      := '0';
00470   signal rod_status_i          : std_logic                      := '0';
00471   signal trig_del_en           : std_logic                      := '0';
00472   signal ack_ok                : std_logic                      := '0';
00473   signal ack_ok_simple         : std_logic                      := '0';
00474   signal ack_miss              : std_logic                      := '0';
00475   signal ack_err               : std_logic                      := '0';
00476   signal orbit_del             : std_logic                      := '0';
00477   signal inhib_del_en          : std_logic                      := '0';
00478   signal mode_i                : std_logic                      := '0';
00479   signal tty_src_i             : std_logic                      := '0';
00480   signal tty_src_ii            : std_logic                      := '0';
00481   signal tty_src_en            : std_logic                      := '0';
00482   signal dssw_src_i            : std_logic                      := '0';
00483   signal dssw_src_ii           : std_logic                      := '0';
00484   signal dssw_src_en           : std_logic                      := '0';
00485   signal dssa_src_i            : std_logic                      := '0';
00486   signal dssa_src_ii           : std_logic                      := '0';
00487   signal dssa_src_en           : std_logic                      := '0';
00488   signal cibi_src_i            : std_logic                      := '0';
00489   signal cibi_src_ii           : std_logic                      := '0';
00490   signal cibi_src_en           : std_logic                      := '0';
00491   signal cibb_src_i            : std_logic                      := '0';
00492   signal cibb_src_ii           : std_logic                      := '0';
00493   signal cibb_src_en           : std_logic                      := '0';
00494   signal tty_en                : std_logic                      := '0';
00495   signal input_en_status_b     : std_logic                      := '0';
00496   signal rxl1                  : std_logic                      := '0';
00497   signal rxl2                  : std_logic                      := '0';
00498   signal rxl3                  : std_logic                      := '0';
00499   signal rxl4                  : std_logic                      := '0';
00500   signal rxl5                  : std_logic                      := '0';
00501   signal rxl6                  : std_logic                      := '0';
00502   signal rxl7                  : std_logic                      := '0';
00503   signal rxl8                  : std_logic                      := '0';
00504   signal txl1                  : std_logic                      := '0';
00505   signal txl2                  : std_logic                      := '0';
00506   signal txl3                  : std_logic                      := '0';
00507   signal txl4                  : std_logic                      := '0';
00508   signal txl5                  : std_logic                      := '0';
00509   signal txl6                  : std_logic                      := '0';
00510   signal txl7                  : std_logic                      := '0';
00511   signal txl8                  : std_logic                      := '0';
00512   signal rxr1                  : std_logic                      := '0';
00513   signal rxr2                  : std_logic                      := '0';
00514   signal rxr3                  : std_logic                      := '0';
00515   signal rxr4                  : std_logic                      := '0';
00516   signal rxr5                  : std_logic                      := '0';
00517   signal rxr6                  : std_logic                      := '0';
00518   signal rxr7                  : std_logic                      := '0';
00519   signal rxr8                  : std_logic                      := '0';
00520   signal txr1                  : std_logic                      := '0';
00521   signal txr2                  : std_logic                      := '0';
00522   signal txr3                  : std_logic                      := '0';
00523   signal txr4                  : std_logic                      := '0';
00524   signal txr5                  : std_logic                      := '0';
00525   signal txr6                  : std_logic                      := '0';
00526   signal txr7                  : std_logic                      := '0';
00527   signal txr8                  : std_logic                      := '0';
00528   signal en_edge_det           : std_logic                      := '0';
00529   signal dump_beam             : std_logic                      := '0';
00530   signal en_abort_contr        : std_logic                      := '0';
00531   signal int_beam_permit       : std_logic                      := '1';
00532   signal int_inj_permit        : std_logic                      := '1';
00533   signal dss_alarm             : std_logic                      := '0';
00534   signal dss_warn              : std_logic                      := '0';
00535   signal SL_UWEN_i             : std_logic                      := '0';
00536   signal latency_en            : std_logic                      := '0';
00537   signal bcr_latency           : std_logic                      := '0';
00538   signal end_slink_i           : std_logic                      := '0';
00539   signal end_slink             : std_logic                      := '0';
00540   signal ackw                  : std_logic                      := '0';
00541   signal acka                  : std_logic                      := '0';
00542   signal acki                  : std_logic                      := '0';
00543   signal ackb                  : std_logic                      := '0';
00544   signal ackw_ii               : std_logic                      := '0';
00545   signal acka_ii               : std_logic                      := '0';
00546   signal acki_ii               : std_logic                      := '0';
00547   signal ackb_ii               : std_logic                      := '0';
00548   signal sirena1_i             : std_logic                      := '0';
00549   signal sewa1_i               : std_logic                      := '0';
00550   signal sandrej1_i            : std_logic                      := '0';
00551   signal sheinz1_i             : std_logic                      := '0';
00552   signal smarko1_i             : std_logic                      := '0';
00553   signal swilliam1_i           : std_logic                      := '0';
00554   signal sharris1_i            : std_logic                      := '0';
00555   signal shelmut1_i            : std_logic                      := '0';
00556   signal sirena2_i             : std_logic                      := '0';
00557   signal sewa2_i               : std_logic                      := '0';
00558   signal sandrej2_i            : std_logic                      := '0';
00559   signal sheinz2_i             : std_logic                      := '0';
00560   signal smarko2_i             : std_logic                      := '0';
00561   signal swilliam2_i           : std_logic                      := '0';
00562   signal sharris2_i            : std_logic                      := '0';
00563   signal shelmut2_i            : std_logic                      := '0';
00564   signal sirena1_ii            : std_logic                      := '0';
00565   signal sewa1_ii              : std_logic                      := '0';
00566   signal sandrej1_ii           : std_logic                      := '0';
00567   signal sheinz1_ii            : std_logic                      := '0';
00568   signal smarko1_ii            : std_logic                      := '0';
00569   signal swilliam1_ii          : std_logic                      := '0';
00570   signal sharris1_ii           : std_logic                      := '0';
00571   signal shelmut1_ii           : std_logic                      := '0';
00572   signal sirena2_ii            : std_logic                      := '0';
00573   signal sewa2_ii              : std_logic                      := '0';
00574   signal sandrej2_ii           : std_logic                      := '0';
00575   signal sheinz2_ii            : std_logic                      := '0';
00576   signal smarko2_ii            : std_logic                      := '0';
00577   signal swilliam2_ii          : std_logic                      := '0';
00578   signal sharris2_ii           : std_logic                      := '0';
00579   signal shelmut2_ii           : std_logic                      := '0';
00580   signal latency_i             : std_logic_vector(7 downto 0)   := (others => '0');
00581   signal latency_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00582   signal SL_UD_i               : std_logic_vector(31 downto 0)  := (others => '0');
00583   signal high_gain_i           : std_logic_vector(3 downto 0)   := (others => '0');
00584   signal low_gain_i            : std_logic_vector(3 downto 0)   := (others => '0');
00585   signal rio_reset_i           : std_logic_vector(7 downto 0)   := (others => '0');
00586   signal rio_reset_ii          : std_logic_vector(7 downto 0)   := (others => '0');
00587   signal tty_sel               : std_logic_vector(7 downto 0)   := (others => '0');
00588   signal dssw_sel              : std_logic_vector(7 downto 0)   := (others => '0');
00589   signal dssa_sel              : std_logic_vector(7 downto 0)   := (others => '0');
00590   signal cibi_sel              : std_logic_vector(7 downto 0)   := (others => '0');
00591   signal cibb_sel              : std_logic_vector(7 downto 0)   := (others => '0');
00592   signal cnt_ch1               : std_logic_vector(31 downto 0)  := (others => '0');
00593   signal cnt_ch2               : std_logic_vector(31 downto 0)  := (others => '0');
00594   signal cnt_ch3               : std_logic_vector(31 downto 0)  := (others => '0');
00595   signal cnt_ch4               : std_logic_vector(31 downto 0)  := (others => '0');
00596   signal cnt_ch5               : std_logic_vector(31 downto 0)  := (others => '0');
00597   signal cnt_ch6               : std_logic_vector(31 downto 0)  := (others => '0');
00598   signal cnt_ch7               : std_logic_vector(31 downto 0)  := (others => '0');
00599   signal cnt_ch8               : std_logic_vector(31 downto 0)  := (others => '0');
00600   signal cnt_coin              : std_logic_vector(31 downto 0)  := (others => '0');
00601   signal cnt_backa             : std_logic_vector(31 downto 0)  := (others => '0');
00602   signal cnt_backc             : std_logic_vector(31 downto 0)  := (others => '0');
00603   signal inhib_del_i           : std_logic_vector(7 downto 0)   := (others => '0');
00604   signal inhib_del_ii          : std_logic_vector(7 downto 0)   := (others => '0');
00605   signal trig_del_i            : std_logic_vector(7 downto 0)   := (others => '0');
00606   signal trig_del_ii           : std_logic_vector(7 downto 0)   := (others => '0');
00607   signal tty_i                 : std_logic_vector(7 downto 0)   := (others => '0');
00608   signal tty_ii                : std_logic_vector(7 downto 0)   := (others => '0');
00609   signal dss_a_iv              : std_logic_vector(7 downto 0)   := (others => '0');
00610   signal dss_wa_iv             : std_logic_vector(7 downto 0)   := (others => '0');
00611   signal inj_p_iv              : std_logic_vector(7 downto 0)   := (others => '0');
00612   signal bem_p_iv              : std_logic_vector(7 downto 0)   := (others => '0');
00613   signal lf_fullv              : std_logic_vector(7 downto 0)   := (others => '0');
00614   signal lf_emptyv             : std_logic_vector(7 downto 0)   := (others => '0');
00615   signal l1a_dispv             : std_logic_vector(7 downto 0)   := (others => '0');
00616   signal coarse_en             : std_logic_vector(7 downto 0)   := (others => '0');
00617   signal eth_debug             : std_logic_vector(19 downto 0)  := (others => '0');
00618   signal l1a_bid               : std_logic_vector(11 downto 0)  := (others => '0');
00619   signal l1a_bid_in            : std_logic_vector(11 downto 0)  := (others => '0');
00620   signal input_en_status_byte0 : std_logic_vector(7 downto 0)   := (others => '0');
00621   signal input_en_status_byte1 : std_logic_vector(7 downto 0)   := (others => '0');
00622   signal input_en_status_byte2 : std_logic_vector(7 downto 0)   := (others => '0');
00623   signal input_en_status_byte3 : std_logic_vector(7 downto 0)   := (others => '0');
00624   signal input_en_status_byte4 : std_logic_vector(7 downto 0)   := (others => '0');
00625   signal input_en_status_byte5 : std_logic_vector(7 downto 0)   := (others => '0');
00626   signal input_en_status_byte6 : std_logic_vector(7 downto 0)   := (others => '0');
00627   signal input_en_status_byte7 : std_logic_vector(7 downto 0)   := (others => '0');
00628   signal l1a_rate_i            : std_logic_vector(31 downto 0)  := (others => '0');
00629   signal sl_ldown_vec          : std_logic_vector(7 downto 0)   := (others => '0');
00630   signal sl_lff_vec            : std_logic_vector(7 downto 0)   := (others => '0');
00631   signal busy_vec              : std_logic_vector(7 downto 0)   := (others => '0');
00632   signal busy_ext_vec          : std_logic_vector(7 downto 0)   := (others => '0');
00633   signal input_en_status       : std_logic_vector(7 downto 0)   := (others => '0');
00634   signal input_en_status_rio   : std_logic_vector(7 downto 0)   := (others => '0');
00635   signal ack                   : std_logic_vector(7 downto 0)   := (others => '0');
00636   signal param_en_vec          : std_logic_vector(7 downto 0)   := (others => '0');
00637   signal mask_i                : std_logic_vector(7 downto 0)   := (others => '1');
00638   signal mask_ii               : std_logic_vector(7 downto 0)   := (others => '0');
00639   signal srcid_i               : std_logic_vector(31 downto 0)  := (others => '0');
00640   signal srcid_ii              : std_logic_vector(23 downto 0)  := (others => '0');
00641   signal algosel_i             : std_logic_vector(7 downto 0)   := (others => '0');
00642   signal algosel_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00643   signal run_num_i             : std_logic_vector(31 downto 0)  := (others => '0');
00644   signal run_num_ii            : std_logic_vector(31 downto 0)  := (others => '0');
00645   signal ev_type_i             : std_logic_vector(31 downto 0)  := (others => '0');
00646   signal ev_type_ii            : std_logic_vector(31 downto 0)  := (others => '0');
00647   signal set_orbit_val         : std_logic_vector(31 downto 0)  := (others => '0');
00648   signal orbit_load_i          : std_logic_vector(31 downto 0)  := (others => '0');
00649   signal orbit_load_ii         : std_logic_vector(31 downto 0)  := (others => '0');
00650   signal ctp_sel               : std_logic_vector(7 downto 0)   := (others => '1');
00651   signal ctp_int               : std_logic_vector(9 downto 1)   := (others => '0');
00652   signal ctp_out               : std_logic_vector(9 downto 1)   := (others => '0');
00653   signal ctp_load              : std_logic_vector(9 downto 1)   := (others => '0');
00654   signal ctp_load_i            : std_logic_vector(9 downto 1)   := (others => '0');
00655   signal ctp_load_ii           : std_logic_vector(9 downto 1)   := (others => '0');
00656   signal ecr_load_i            : std_logic_vector(7 downto 0)   := (others => '0');
00657   signal l1a_load_i            : std_logic_vector(23 downto 0)  := (others => '0');
00658   signal ecr_load_ii           : std_logic_vector(7 downto 0)   := (others => '0');
00659   signal l1a_load_ii           : std_logic_vector(23 downto 0)  := (others => '0');
00660   signal algo_data             : std_logic_vector(191 downto 0) := (others => '0');
00661   signal proc_data_i           : std_logic_vector(191 downto 0) := (others => '0');
00662   signal proc_data_ii          : std_logic_vector(191 downto 0) := (others => '0');
00663   signal proc_data_i_emu       : std_logic_vector(191 downto 0) := (others => '0');
00664   signal proc_data_lvl1        : std_logic_vector(175 downto 0) := (others => '0');
00665   signal proc_data_ddr         : std_logic_vector(63 downto 0)  := (others => '0');
00666   signal proc_data_eth         : std_logic_vector(63 downto 0)  := (others => '0');
00667   signal proc_data_eth_i       : std_logic_vector(63 downto 0)  := (others => '0');
00668   signal proc_data_eth_i_1     : std_logic_vector(63 downto 0)  := (others => '0');
00669   signal raw_data_i            : std_logic_vector(255 downto 0) := (others => '0');
00670   signal raw_data_ii           : std_logic_vector(255 downto 0) := (others => '0');
00671   signal raw_data_i_emu        : std_logic_vector(255 downto 0) := (others => '0');
00672   signal raw_data_ddr          : std_logic_vector(127 downto 0) := (others => '0');
00673   signal raw_data_eth          : std_logic_vector(127 downto 0) := (others => '0');
00674   signal raw_data_eth_i        : std_logic_vector(127 downto 0) := (others => '0');
00675   signal raw_data_eth_i_1      : std_logic_vector(127 downto 0) := (others => '0');
00676   signal raw_data_eth_i_2      : std_logic_vector(127 downto 0) := (others => '0');
00677   signal delta_t_a_i           : std_logic_vector(6 downto 0)   := (others => '0');
00678   signal delta_t_b_i           : std_logic_vector(6 downto 0)   := (others => '0');
00679   signal delta_t_c_i           : std_logic_vector(6 downto 0)   := (others => '0');
00680   signal delta_t_d_i           : std_logic_vector(6 downto 0)   := (others => '0');
00681   signal int_bufeth_in         : std_logic_vector(63 downto 0)  := (others => '0');
00682   signal int_bufeth_in_i       : std_logic_vector(63 downto 0)  := (others => '0');
00683   signal eth_byte              : std_logic_vector(7 downto 0)   := (others => '0');
00684   signal raw_byte              : std_logic_vector(7 downto 0)   := (others => '0');
00685   signal proc_byte             : std_logic_vector(7 downto 0)   := (others => '0');
00686   signal stat_byte             : std_logic_vector(7 downto 0)   := (others => '0');
00687   signal irena1_i              : std_logic_vector(7 downto 0)   := (others => '0');
00688   signal ewa1_i                : std_logic_vector(7 downto 0)   := (others => '0');
00689   signal andrej1_i             : std_logic_vector(7 downto 0)   := (others => '0');
00690   signal heinz1_i              : std_logic_vector(7 downto 0)   := (others => '0');
00691   signal marko1_i              : std_logic_vector(7 downto 0)   := (others => '0');
00692   signal william1_i            : std_logic_vector(7 downto 0)   := (others => '0');
00693   signal harris1_i             : std_logic_vector(7 downto 0)   := (others => '0');
00694   signal helmut1_i             : std_logic_vector(7 downto 0)   := (others => '0');
00695   signal irena2_i              : std_logic_vector(7 downto 0)   := (others => '0');
00696   signal ewa2_i                : std_logic_vector(7 downto 0)   := (others => '0');
00697   signal andrej2_i             : std_logic_vector(7 downto 0)   := (others => '0');
00698   signal heinz2_i              : std_logic_vector(7 downto 0)   := (others => '0');
00699   signal marko2_i              : std_logic_vector(7 downto 0)   := (others => '0');
00700   signal william2_i            : std_logic_vector(7 downto 0)   := (others => '0');
00701   signal harris2_i             : std_logic_vector(7 downto 0)   := (others => '0');
00702   signal helmut2_i             : std_logic_vector(7 downto 0)   := (others => '0');
00703   signal irena1_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00704   signal ewa1_ii               : std_logic_vector(7 downto 0)   := (others => '0');
00705   signal andrej1_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00706   signal heinz1_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00707   signal marko1_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00708   signal william1_ii           : std_logic_vector(7 downto 0)   := (others => '0');
00709   signal harris1_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00710   signal helmut1_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00711   signal irena2_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00712   signal ewa2_ii               : std_logic_vector(7 downto 0)   := (others => '0');
00713   signal andrej2_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00714   signal heinz2_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00715   signal marko2_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00716   signal william2_ii           : std_logic_vector(7 downto 0)   := (others => '0');
00717   signal harris2_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00718   signal helmut2_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00719   signal clr_shift             : std_logic_vector(4 downto 0)   := (others => '0');
00720   signal clr_shift2            : std_logic_vector(4 downto 0)   := (others => '0');
00721   signal a_i                   : std_logic_vector(8 downto 0)   := (others => '0');
00722   signal b_i                   : std_logic_vector(4 downto 0)   := (others => '0');
00723   signal data_rod              : std_logic_vector(191 downto 0) := (others => '0');
00724   signal evid_i                : std_logic_vector(31 downto 0)  := (others => '0');
00725   signal l1a_evid              : std_logic_vector(31 downto 0)  := (others => '0');
00726   signal orbid_i               : std_logic_vector(31 downto 0)  := (others => '0');
00727   signal ctp_tty_i             : std_logic_vector(31 downto 0)  := (others => '0');
00728   signal bcid_i                : std_logic_vector(11 downto 0)  := (others => '0');
00729   signal bcid_long             : std_logic_vector(31 downto 0)  := (others => '0');
00730   signal mask_err_n_i          : std_logic_vector(7 downto 0)   := (others => '1');
00731   signal rioerr_type_i         : std_logic_vector(7 downto 0)   := (others => '0');
00732   signal proc_chksum_1         : std_logic_vector(15 downto 0)  := (others => '0');
00733   signal proc_chksum_2         : std_logic_vector(15 downto 0)  := (others => '0');
00734   signal tdaq_chksum           : std_logic_vector(15 downto 0)  := (others => '0');
00735   signal stat_chksum           : std_logic_vector(15 downto 0)  := (others => '0');
00736   signal raw_chksum_1          : std_logic_vector(15 downto 0)  := (others => '0');
00737   signal chksum_1              : std_logic_vector(15 downto 0)  := (others => '0');
00738   signal raw_chksum_2          : std_logic_vector(15 downto 0)  := (others => '0');
00739   signal chksum_2              : std_logic_vector(15 downto 0)  := (others => '0');
00740   signal sata_data_out_a       : std_logic_vector(63 downto 0)  := (others => '0');
00741   signal sata_data_in_a        : std_logic_vector(63 downto 0)  := (others => '0');
00742   signal sata_data_out_b       : std_logic_vector(63 downto 0)  := (others => '0');
00743   signal sata_data_in_b        : std_logic_vector(63 downto 0)  := (others => '0');
00744   signal sata_data_control_i   : std_logic_vector(7 downto 0)   := (others => '0');
00745   signal pc_cmd                : std_logic_vector(7 downto 0)   := (others => '0');
00746   signal pc_datatype           : std_logic_vector(11 downto 0)  := (others => '0');
00747   signal tdaq_byte             : std_logic_vector(7 downto 0)   := (others => '0');
00748   signal en_adj_time           : std_logic_vector(7 downto 0)   := (others => '0');
00749   signal mult_irena_i          : std_logic_vector(7 downto 0)   := (others => '0');
00750   signal mult_ewa_i            : std_logic_vector(7 downto 0)   := (others => '0');
00751   signal mult_andrej_i         : std_logic_vector(7 downto 0)   := (others => '0');
00752   signal mult_heinz_i          : std_logic_vector(7 downto 0)   := (others => '0');
00753   signal mult_marko_i          : std_logic_vector(7 downto 0)   := (others => '0');
00754   signal mult_william_i        : std_logic_vector(7 downto 0)   := (others => '0');
00755   signal mult_harris_i         : std_logic_vector(7 downto 0)   := (others => '0');
00756   signal mult_helmut_i         : std_logic_vector(7 downto 0)   := (others => '0');
00757   signal mult_all              : std_logic_vector(127 downto 0) := (others => '0');
00758   signal data_src              : std_logic_vector(7 downto 0)   := (others => '0');
00759   signal hr_min_all            : std_logic_vector(127 downto 0) := (others => '0');
00760   signal hr_max_all            : std_logic_vector(127 downto 0) := (others => '0');
00761   signal hr_avg_all            : std_logic_vector(127 downto 0) := (others => '0');
00762   signal hr_avg_all_short      : std_logic_vector(127 downto 0) := (others => '0');
00763   signal l1a_fifo_fill         : std_logic_vector(4 downto 0)   := (others => '0');
00764   signal fpgaid_i              : std_logic_vector(7 downto 0)   := (others => '0');
00765   signal fpgaid_ii             : std_logic_vector(7 downto 0)   := (others => '0');
00766   signal format_ver_i          : std_logic_vector(31 downto 0)  := (others => '0');
00767   signal format_ver_ii         : std_logic_vector(31 downto 0)  := (others => '0');
00768   signal coarse0_i             : std_logic_vector(7 downto 0)   := (others => '0');
00769   signal coarse0_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00770   signal coarse1_i             : std_logic_vector(7 downto 0)   := (others => '0');
00771   signal coarse1_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00772   signal coarse2_i             : std_logic_vector(7 downto 0)   := (others => '0');
00773   signal coarse2_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00774   signal coarse3_i             : std_logic_vector(7 downto 0)   := (others => '0');
00775   signal coarse3_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00776   signal coarse4_i             : std_logic_vector(7 downto 0)   := (others => '0');
00777   signal coarse4_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00778   signal coarse5_i             : std_logic_vector(7 downto 0)   := (others => '0');
00779   signal coarse5_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00780   signal coarse6_i             : std_logic_vector(7 downto 0)   := (others => '0');
00781   signal coarse6_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00782   signal coarse7_i             : std_logic_vector(7 downto 0)   := (others => '0');
00783   signal coarse7_ii            : std_logic_vector(7 downto 0)   := (others => '0');
00784   signal fine_del_stdl_1       : std_logic_vector(7 downto 0)   := (others => '0');
00785   signal fine_del_stdl_2       : std_logic_vector(7 downto 0)   := (others => '0');
00786   signal fine_del_stdl_3       : std_logic_vector(7 downto 0)   := (others => '0');
00787   signal fine_del_stdl_4       : std_logic_vector(7 downto 0)   := (others => '0');
00788   signal fine_del_stdl_5       : std_logic_vector(7 downto 0)   := (others => '0');
00789   signal fine_del_stdl_6       : std_logic_vector(7 downto 0)   := (others => '0');
00790   signal fine_del_stdl_7       : std_logic_vector(7 downto 0)   := (others => '0');
00791   signal fine_del_stdl_0       : std_logic_vector(7 downto 0)   := (others => '0');
00792   signal err_code              : std_logic_vector(7 downto 0)   := (others => '0');
00793   signal rio_trip              : std_logic_vector(7 downto 0)   := (others => '0');
00794   signal cuts_en_i             : std_logic_vector(7 downto 0)   := (others => '0');
00795   signal colwinl               : std_logic_vector(7 downto 0)   := (others => '0');
00796   signal colwinh               : std_logic_vector(7 downto 0)   := (others => '0');
00797   signal colwinlw              : std_logic_vector(7 downto 0)   := (others => '0');
00798   signal colwinhw              : std_logic_vector(7 downto 0)   := (others => '0');
00799   signal colwinlo1             : std_logic_vector(7 downto 0)   := (others => '0');
00800   signal colwinho1             : std_logic_vector(7 downto 0)   := (others => '0');
00801   signal colwinlo2             : std_logic_vector(7 downto 0)   := (others => '0');
00802   signal colwinho2             : std_logic_vector(7 downto 0)   := (others => '0');
00803   signal colwinl_i             : std_logic_vector(7 downto 0)   := (others => '0');
00804   signal colwinh_i             : std_logic_vector(7 downto 0)   := (others => '0');
00805   signal colwinlw_i            : std_logic_vector(7 downto 0)   := (others => '0');
00806   signal colwinhw_i            : std_logic_vector(7 downto 0)   := (others => '0');
00807   signal colwinlo1_i           : std_logic_vector(7 downto 0)   := (others => '0');
00808   signal colwinho1_i           : std_logic_vector(7 downto 0)   := (others => '0');
00809   signal colwinlo2_i           : std_logic_vector(7 downto 0)   := (others => '0');
00810   signal colwinho2_i           : std_logic_vector(7 downto 0)   := (others => '0');
00811   signal rio_rx_locks          : std_logic_vector(7 downto 0)   := (others => '0');
00812   signal rio_tx_locks          : std_logic_vector(7 downto 0)   := (others => '0');
00813   signal rio_rx_rdys           : std_logic_vector(7 downto 0)   := (others => '0');
00814   signal rio_tx_rdys           : std_logic_vector(7 downto 0)   := (others => '0');
00815   signal trig_rate_AttC        : std_logic_vector(31 downto 0)  := (others => '0');
00816   signal trig_rate_AttA        : std_logic_vector(31 downto 0)  := (others => '0');
00817   signal trig_rate_Mult3pC     : std_logic_vector(31 downto 0)  := (others => '0');
00818   signal trig_rate_Mult2C      : std_logic_vector(31 downto 0)  := (others => '0');
00819   signal trig_rate_Mult1C      : std_logic_vector(31 downto 0)  := (others => '0');
00820   signal trig_rate_Mult3pA     : std_logic_vector(31 downto 0)  := (others => '0');
00821   signal trig_rate_Mult2A      : std_logic_vector(31 downto 0)  := (others => '0');
00822   signal trig_rate_Mult1A      : std_logic_vector(31 downto 0)  := (others => '0');
00823   signal trig_rate_Wide        : std_logic_vector(31 downto 0)  := (others => '0');
00824   signal trig_rate_CtoA        : std_logic_vector(31 downto 0)  := (others => '0');
00825   signal trig_rate_AtoC        : std_logic_vector(31 downto 0)  := (others => '0');
00826   signal numbunch_i            : std_logic_vector(6 downto 0)   := "0000001";
00827   signal numbunch_ii           : integer range 0 to 127         := 0;
00828   signal adj_time0             : integer range 0 to 64          := 0;
00829   signal adj_time1             : integer range 0 to 64          := 0;
00830   signal adj_time2             : integer range 0 to 64          := 0;
00831   signal adj_time3             : integer range 0 to 64          := 0;
00832   signal adj_time4             : integer range 0 to 64          := 0;
00833   signal adj_time5             : integer range 0 to 64          := 0;
00834   signal adj_time6             : integer range 0 to 64          := 0;
00835   signal adj_time7             : integer range 0 to 64          := 0;
00836   signal adj_time0i            : integer range 0 to 64          := 0;
00837   signal adj_time1i            : integer range 0 to 64          := 0;
00838   signal adj_time2i            : integer range 0 to 64          := 0;
00839   signal adj_time3i            : integer range 0 to 64          := 0;
00840   signal adj_time4i            : integer range 0 to 64          := 0;
00841   signal adj_time5i            : integer range 0 to 64          := 0;
00842   signal adj_time6i            : integer range 0 to 64          := 0;
00843   signal adj_time7i            : integer range 0 to 64          := 0;
00844   signal adj_time0_i           : integer range 0 to 32          := 0;
00845   signal adj_time1_i           : integer range 0 to 32          := 0;
00846   signal adj_time2_i           : integer range 0 to 32          := 0;
00847   signal adj_time3_i           : integer range 0 to 32          := 0;
00848   signal adj_time4_i           : integer range 0 to 32          := 0;
00849   signal adj_time5_i           : integer range 0 to 32          := 0;
00850   signal adj_time6_i           : integer range 0 to 32          := 0;
00851   signal adj_time7_i           : integer range 0 to 32          := 0;
00852   signal adj_time02_i          : integer range 0 to 32          := 0;
00853   signal adj_time12_i          : integer range 0 to 32          := 0;
00854   signal adj_time22_i          : integer range 0 to 32          := 0;
00855   signal adj_time32_i          : integer range 0 to 32          := 0;
00856   signal adj_time42_i          : integer range 0 to 32          := 0;
00857   signal adj_time52_i          : integer range 0 to 32          := 0;
00858   signal adj_time62_i          : integer range 0 to 32          := 0;
00859   signal adj_time72_i          : integer range 0 to 32          := 0;
00860 
00861 
00862   signal control0_i, control1_i, control2_i : std_logic_vector(35 downto 0);
00863   signal probe1_i, probe2_i, probe3_i       : std_logic_vector(49 downto 0);
00864   signal pktcnt                             : std_logic_vector(6 downto 0)  := (others => '0');
00865   signal pktcnt2                            : std_logic_vector(6 downto 0)  := (others => '0');
00866   signal pktcnt3                            : std_logic_vector(6 downto 0)  := (others => '0');
00867   signal pktcnt4                            : std_logic_vector(6 downto 0)  := (others => '0');
00868   signal pktcnt5                            : std_logic_vector(6 downto 0)  := (others => '0');
00869   signal ctor_debug                         : std_logic_vector(22 downto 0) := (others => '0');
00870 
00871   constant pattern     : std_logic_vector(127 downto 0) := x"f0f0f0f0_f0f0f0f0_f0f0f0f0_f0f0f0f0";
00872   constant c_colwinl   : std_logic_vector(5 downto 0)   := conv_std_logic_vector(36, 6);
00873   constant c_colwinh   : std_logic_vector(5 downto 0)   := conv_std_logic_vector(40, 6);
00874   constant c_colwinlw  : std_logic_vector(5 downto 0)   := conv_std_logic_vector(28, 6);
00875   constant c_colwinhw  : std_logic_vector(5 downto 0)   := conv_std_logic_vector(58, 6);
00876   constant c_colwinlo1 : std_logic_vector(5 downto 0)   := conv_std_logic_vector(4, 6);
00877   constant c_colwinho1 : std_logic_vector(5 downto 0)   := conv_std_logic_vector(8, 6);
00878   constant c_colwinlo2 : std_logic_vector(5 downto 0)   := conv_std_logic_vector(4, 6);
00879   constant c_colwinho2 : std_logic_vector(5 downto 0)   := conv_std_logic_vector(8, 6);
00880 
00881 
00882   for algo_a : delta_t_ac_top use entity
00883     work.delta_t_ac_top(one_to_one);
00884   for algo_b : delta_t_ac_top use entity
00885     work.delta_t_ac_top(two_to_two);
00886   for algo_c : delta_t_ac_top use entity
00887     work.delta_t_ac_top(single);
00888   for algo_d : delta_t_ac_top use entity
00889     work.delta_t_ac_top(double);
00890 
00891 
00892   attribute fsm_encoding               : string;
00893   attribute fsm_encoding of ems        : signal is "gray";
00894 
00895   attribute safe_implementation        : string;
00896   attribute safe_implementation of ems : signal is "yes";
00897 
00898 --*************************************************************************
00899 --                              main code
00900 --*************************************************************************
00901 begin
00902 
00903   OR_CH1      <= '0';
00904   OR_CH2      <= '0';
00905   GP_ERR_FLAG <= '0';
00906   GOTO_RD     <= '0';
00907 
00908 -------------------------------------------------------------------------------
00909 --                           RocketIOs & Edge Detection
00910 -------------------------------------------------------------------------------
00911 
00912   RIOS_READY  <= rios_ready_i;
00913   CAL_DONE    <= rios_work;
00914   en_edge_det <= arp_done;
00915 
00916 
00917 
00918 
00919 
00920   daq : rios_all
00921     port map
00922     (
00923       BCLK                  => BCLK,
00924       BCLK4X               => BCLK4X_P,
00925       BCLK2X                => BCLK2X_P,
00926       RIOCLK_1              => RIOCLK_1,
00927       RIOCLK_2             => RIOCLK_2,
00928       EN                   => en_edge_det,
00929       RESET                => RESET,
00930       SEP_RESET            => rio_reset_i,
00931       CALIBRATE_RIOS       => CALIBRATE_RIOS,
00932       RIOS_READY           => rios_ready_i,
00933       LOCK_OUT              => LOCK_OUT,
00934       DONE                 => rios_work,
00935       CHECK                => CHECK,
00936       RXN_C_IE             => RXN_C_IE,
00937       RXP_C_IE             => RXP_C_IE,
00938       TXN_C_IE             => TXN_C_IE,
00939       TXP_C_IE             => TXP_C_IE,
00940       RXN_C_AH             => RXN_C_AH,
00941       RXP_C_AH             => RXP_C_AH,
00942       TXN_C_AH             => TXN_C_AH,
00943       TXP_C_AH             => TXP_C_AH,
00944       RXN_A_WM             => RXN_A_WM,
00945       RXP_A_WM             => RXP_A_WM,
00946       TXN_A_WM             => TXN_A_WM,
00947       TXP_A_WM             => TXP_A_WM,
00948       RXN_A_HH             => RXN_A_HH,
00949       RXP_A_HH             => RXP_A_HH,
00950       TXN_A_HH             => TXN_A_HH,
00951       TXP_A_HH             => TXP_A_HH,
00952       CAL_IRENA            => cal_irena_i,
00953       CAL_EWA              => cal_ewa_i,
00954       CAL_ANDREJ           => cal_andrej_i,
00955       CAL_HEINZ            => cal_heinz_i,
00956       CAL_MARKO            => cal_marko_i,
00957       CAL_WILLIAM          => cal_william_i,
00958       CAL_HARRIS           => cal_harris_i,
00959       CAL_HELMUT           => cal_helmut_i,
00960       MASK_IRENA           => input_en_status_rio (1),
00961       MASK_EWA             => input_en_status_rio (0),
00962       MASK_ANDREJ          => input_en_status_rio (3),
00963       MASK_HEINZ           => input_en_status_rio (2),
00964       MASK_MARKO           => input_en_status_rio (5),
00965       MASK_WILLIAM         => input_en_status_rio (4),
00966       MASK_HARRIS          => input_en_status_rio (7),
00967       MASK_HELMUT          => input_en_status_rio (6),
00968       RX_LOCK1              => rxl1,
00969       RX_LOCK2             => rxl2,
00970       RX_LOCK3             => rxl3,
00971       RX_LOCK4             => rxl4,
00972       RX_LOCK5             => rxl5,
00973       RX_LOCK6             => rxl6,
00974       RX_LOCK7             => rxl7,
00975       RX_LOCK8             => rxl8,
00976       TX_LOCK1             => txl1,
00977       TX_LOCK2             => txl2,
00978       TX_LOCK3             => txl3,
00979       TX_LOCK4             => txl4,
00980       TX_LOCK5             => txl5,
00981       TX_LOCK6             => txl6,
00982       TX_LOCK7             => txl7,
00983       TX_LOCK8             => txl8,
00984       RX_READY1            => rxr1,
00985       RX_READY2            => rxr2,
00986       RX_READY3            => rxr3,
00987       RX_READY4            => rxr4,
00988       RX_READY5            => rxr5,
00989       RX_READY6            => rxr6,
00990       RX_READY7            => rxr7,
00991       RX_READY8            => rxr8,
00992       TX_READY1            => txr1,
00993       TX_READY2            => txr2,
00994       TX_READY3            => txr3,
00995       TX_READY4            => txr4,
00996       TX_READY5            => txr5,
00997       TX_READY6            => txr6,
00998       TX_READY7            => txr7,
00999       TX_READY8            => txr8,
01000       MULT_IRENA           => mult_irena_i,
01001       MULT_EWA             => mult_ewa_i,
01002       MULT_ANDREJ          => mult_andrej_i,
01003       MULT_HEINZ           => mult_heinz_i,
01004       MULT_MARKO           => mult_marko_i,
01005       MULT_WILLIAM         => mult_william_i,
01006       MULT_HARRIS          => mult_harris_i,
01007       MULT_HELMUT          => mult_helmut_i,
01008       PROC_DATA            => proc_data_ii,
01009       RAW_DATA             => raw_data_ii,
01010       ADJUST_TIME_IRENA    => adj_time1_i,
01011       ADJUST_TIME_EWA      => adj_time0_i,
01012       ADJUST_TIME_ANDREJ   => adj_time3_i,
01013       ADJUST_TIME_HEINZ    => adj_time2_i,
01014       ADJUST_TIME_MARKO    => adj_time5_i,
01015       ADJUST_TIME_WILLIAM  => adj_time4_i,
01016       ADJUST_TIME_HARRIS   => adj_time7_i,
01017       ADJUST_TIME_HELMUT   => adj_time6_i,
01018       ADJUST_TIME_IRENA2   => adj_time12_i,
01019       ADJUST_TIME_EWA2     => adj_time02_i,
01020       ADJUST_TIME_ANDREJ2  => adj_time32_i,
01021       ADJUST_TIME_HEINZ2   => adj_time22_i,
01022       ADJUST_TIME_MARKO2   => adj_time52_i,
01023       ADJUST_TIME_WILLIAM2 => adj_time42_i,
01024       ADJUST_TIME_HARRIS2  => adj_time72_i,
01025       ADJUST_TIME_HELMUT2  => adj_time62_i,
01026       COARSE_TIME_IRENA    => coarse1_i,
01027       COARSE_TIME_EWA      => coarse0_i,
01028       COARSE_TIME_ANDREJ   => coarse3_i,
01029       COARSE_TIME_HEINZ    => coarse2_i,
01030       COARSE_TIME_MARKO    => coarse5_i,
01031       COARSE_TIME_WILLIAM  => coarse4_i,
01032       COARSE_TIME_HARRIS   => coarse7_i,
01033       COARSE_TIME_HELMUT   => coarse6_i
01034       );
01035 
01036   rio_rx_locks <= rxl8 & rxl7 & rxl6 & rxl5 &
01037                   rxl4 & rxl3 & rxl2 & rxl1;
01038   rio_tx_locks <= txl8 & txl7 & txl6 & txl5 &
01039                   txl4 & txl3 & txl2 & txl1;
01040   rio_rx_rdys <= rxr8 & rxr7 & rxr6 & rxr5 &
01041                  rxr4 & rxr3 & rxr2 & rxr1;
01042   rio_tx_rdys <= txr8 & txr7 & txr6 & txr5 &
01043                  txr4 & txr3 & txr2 & txr1;
01044 
01045   mask_vec_gen : for M in 7 downto 0 generate
01046     input_en_status(M) <= input_en_status_rio(M) and mask_i(M);
01047 
01048     edge_fal_det : edge_fal
01049       port map (
01050         CLK   => BCLK2X_P,
01051         A     => input_en_status_rio(M),
01052         PULSE => rio_trip(M)
01053         );
01054 
01055   end generate mask_vec_gen;
01056 
01057   input_en_status_b <= input_en_status(0) and input_en_status(1) and
01058                        input_en_status(2) and input_en_status(3) and
01059                        input_en_status(4) and input_en_status(5) and
01060                        input_en_status(6) and input_en_status(7);
01061 
01062   cal_irena_i   <= rio_trip(1);
01063   cal_ewa_i     <= rio_trip(0);
01064   cal_andrej_i  <= rio_trip(3);
01065   cal_heinz_i   <= rio_trip(2);
01066   cal_marko_i   <= rio_trip(5);
01067   cal_william_i <= rio_trip(4);
01068   cal_harris_i  <= rio_trip(7);
01069   cal_helmut_i  <= rio_trip(6);
01070 
01071   -- map MASK to outside (using internal names!)
01072   MASK_IRENA   <= input_en_status(1);
01073   MASK_EWA     <= input_en_status(0);
01074   MASK_ANDREJ  <= input_en_status(3);
01075   MASK_HEINZ   <= input_en_status(2);
01076   MASK_MARKO   <= input_en_status(5);
01077   MASK_WILLIAM <= input_en_status(4);
01078   MASK_HARRIS  <= input_en_status(7);
01079   MASK_HELMUT  <= input_en_status(6);
01080 
01081   mask_err_n_i  <= "11111111";  --* no channels masked for error checking
01082   RIOERR_TYPE   <= rioerr_type_i;
01083   en_riomonitor <= CAPTURE and (not kMask_RioCheck);
01084   rioerr_type_i <= (others => '0');
01085   RIOERR        <= '0';
01086 
01087 -------------------------------------------------------------------------------
01088 --                             Pattern Generation
01089 -------------------------------------------------------------------------------
01090 
01091   --* switch to filling with buffer
01092   en_fill <= CAPTURE and pat_fill;
01093 
01094 
01095   raw_data_gen : raw_data_emul
01096     generic map (
01097       CONF => "10101010")
01098     port map (
01099       CLK   => BCLK,
01100       RESET => mem_reset ,
01101       EN    => en_fill ,
01102       CH1   => raw_data_i_emu(31 downto 0),
01103       CH2   => raw_data_i_emu(63 downto 32),
01104       CH3   => raw_data_i_emu(95 downto 64),
01105       CH4   => raw_data_i_emu(127 downto 96),
01106       CH5   => raw_data_i_emu(159 downto 128),
01107       CH6   => raw_data_i_emu(191 downto 160),
01108       CH7   => raw_data_i_emu(223 downto 192),
01109       CH8   => raw_data_i_emu(255 downto 224)
01110       );
01111 
01112 
01113   proc_data_gen : proc_data_emul
01114     port map (
01115       CLK   => BCLK,
01116       RESET => mem_reset ,
01117       EN    => en_fill ,
01118       CH1   => proc_data_i_emu(191 downto 168),
01119       CH2   => proc_data_i_emu(167 downto 144),
01120       CH3   => proc_data_i_emu(143 downto 120),
01121       CH4   => proc_data_i_emu(119 downto 96),
01122       CH5   => proc_data_i_emu(95 downto 72),
01123       CH6   => proc_data_i_emu(71 downto 48),
01124       CH7   => proc_data_i_emu(47 downto 24),
01125       CH8   => proc_data_i_emu(23 downto 0)
01126       );
01127 
01128   --* mux data to memories
01129   proc_data_i <= proc_data_i_emu when pat_fill = '1' else proc_data_ii;
01130   raw_data_i  <= raw_data_i_emu  when pat_fill = '1' else raw_data_ii;
01131   algo_data   <= proc_data_ii    when pat_fill = '0' else (others => '0');
01132   data_src    <= x"ff" when pat_fill = '0' else x"00";
01133 
01134 -------------------------------------------------------------------------------
01135 --                      Time Windows & Coincidences
01136 -------------------------------------------------------------------------------
01137 
01138 
01139   algo_a : delta_t_ac_top
01140     port map
01141     (
01142       CLK           => BCLK,
01143       UPPER_BOUND_A => colwinh(5 downto 0),  --* full acceptancy range
01144       LOWER_BOUND_A => colwinl(5 downto 0),
01145       UPPER_BOUND_C => colwinh(5 downto 0),
01146       LOWER_BOUND_C => colwinl(5 downto 0),
01147       IRENA1        => irena1_ii,
01148       EWA1          => ewa1_ii,
01149       HEINZ1        => heinz1_ii,
01150       ANDREJ1       => andrej1_ii,
01151       MARKO1        => marko1_ii,
01152       WILLIAM1      => william1_ii,
01153       HARRIS1       => harris1_ii,
01154       HELMUT1       => helmut1_ii,
01155       IRENA2        => irena2_ii,
01156       EWA2          => ewa2_ii,
01157       HEINZ2        => heinz2_ii,
01158       ANDREJ2       => andrej2_ii,
01159       MARKO2        => marko2_ii,
01160       WILLIAM2      => william2_ii,
01161       HARRIS2       => harris2_ii,
01162       HELMUT2       => helmut2_ii,
01163       S_IRENA1      => sirena1_ii,
01164       S_EWA1        => sewa1_ii,
01165       S_ANDREJ1     => sandrej1_ii,
01166       S_HEINZ1      => sheinz1_ii,
01167       S_MARKO1      => smarko1_ii,
01168       S_WILLIAM1    => swilliam1_ii,
01169       S_HARRIS1     => sharris1_ii,
01170       S_HELMUT1     => shelmut1_ii,
01171       S_IRENA2      => sirena2_ii,
01172       S_EWA2        => sewa2_ii,
01173       S_ANDREJ2     => sandrej2_ii,
01174       S_HEINZ2      => sheinz2_ii,
01175       S_MARKO2      => smarko2_ii,
01176       S_WILLIAM2    => swilliam2_ii,
01177       S_HARRIS2     => sharris2_ii,
01178       S_HELMUT2     => shelmut2_ii,
01179       VLD           => delta_vld_a,
01180       DELTA_TOUT    => delta_t_a_i
01181       );
01182 
01183 
01184   algo_b : delta_t_ac_top
01185     port map
01186     (
01187       CLK           => BCLK,
01188       UPPER_BOUND_A => colwinh(5 downto 0),  --* full acceptancy range
01189       LOWER_BOUND_A => colwinl(5 downto 0),
01190       UPPER_BOUND_C => colwinh(5 downto 0),
01191       LOWER_BOUND_C => colwinl(5 downto 0),
01192       IRENA1        => irena1_ii,
01193       EWA1          => ewa1_ii,
01194       HEINZ1        => heinz1_ii,
01195       ANDREJ1       => andrej1_ii,
01196       MARKO1        => marko1_ii,
01197       WILLIAM1      => william1_ii,
01198       HARRIS1       => harris1_ii,
01199       HELMUT1       => helmut1_ii,
01200       IRENA2        => irena2_ii,
01201       EWA2          => ewa2_ii,
01202       HEINZ2        => heinz2_ii,
01203       ANDREJ2       => andrej2_ii,
01204       MARKO2        => marko2_ii,
01205       WILLIAM2      => william2_ii,
01206       HARRIS2       => harris2_ii,
01207       HELMUT2       => helmut2_ii,
01208       S_IRENA1      => sirena1_ii,
01209       S_EWA1        => sewa1_ii,
01210       S_ANDREJ1     => sandrej1_ii,
01211       S_HEINZ1      => sheinz1_ii,
01212       S_MARKO1      => smarko1_ii,
01213       S_WILLIAM1    => swilliam1_ii,
01214       S_HARRIS1     => sharris1_ii,
01215       S_HELMUT1     => shelmut1_ii,
01216       S_IRENA2      => sirena2_ii,
01217       S_EWA2        => sewa2_ii,
01218       S_ANDREJ2     => sandrej2_ii,
01219       S_HEINZ2      => sheinz2_ii,
01220       S_MARKO2      => smarko2_ii,
01221       S_WILLIAM2    => swilliam2_ii,
01222       S_HARRIS2     => sharris2_ii,
01223       S_HELMUT2     => shelmut2_ii,
01224       VLD           => delta_vld_b,
01225       DELTA_TOUT    => delta_t_b_i
01226       );
01227 
01228 
01229   algo_c : delta_t_ac_top
01230     port map
01231     (
01232       CLK           => BCLK,
01233       UPPER_BOUND_A => colwinh(5 downto 0),  --* full acceptancy range
01234       LOWER_BOUND_A => colwinl(5 downto 0),
01235       UPPER_BOUND_C => colwinh(5 downto 0),
01236       LOWER_BOUND_C => colwinl(5 downto 0),
01237       IRENA1        => irena1_ii,
01238       EWA1          => ewa1_ii,
01239       HEINZ1        => heinz1_ii,
01240       ANDREJ1       => andrej1_ii,
01241       MARKO1        => marko1_ii,
01242       WILLIAM1      => william1_ii,
01243       HARRIS1       => harris1_ii,
01244       HELMUT1       => helmut1_ii,
01245       IRENA2        => irena2_ii,
01246       EWA2          => ewa2_ii,
01247       HEINZ2        => heinz2_ii,
01248       ANDREJ2       => andrej2_ii,
01249       MARKO2        => marko2_ii,
01250       WILLIAM2      => william2_ii,
01251       HARRIS2       => harris2_ii,
01252       HELMUT2       => helmut2_ii,
01253       S_IRENA1      => sirena1_ii,
01254       S_EWA1        => sewa1_ii,
01255       S_ANDREJ1     => sandrej1_ii,
01256       S_HEINZ1      => sheinz1_ii,
01257       S_MARKO1      => smarko1_ii,
01258       S_WILLIAM1    => swilliam1_ii,
01259       S_HARRIS1     => sharris1_ii,
01260       S_HELMUT1     => shelmut1_ii,
01261       S_IRENA2      => sirena2_ii,
01262       S_EWA2        => sewa2_ii,
01263       S_ANDREJ2     => sandrej2_ii,
01264       S_HEINZ2      => sheinz2_ii,
01265       S_MARKO2      => smarko2_ii,
01266       S_WILLIAM2    => swilliam2_ii,
01267       S_HARRIS2     => sharris2_ii,
01268       S_HELMUT2     => shelmut2_ii,
01269       VLD           => delta_vld_c,
01270       DELTA_TOUT    => delta_t_c_i
01271       );
01272 
01273 
01274   algo_d : delta_t_ac_top
01275     port map
01276     (
01277       CLK           => BCLK,
01278       UPPER_BOUND_A => colwinh(5 downto 0),  --* full acceptancy range
01279       LOWER_BOUND_A => colwinl(5 downto 0),
01280       UPPER_BOUND_C => colwinh(5 downto 0),
01281       LOWER_BOUND_C => colwinl(5 downto 0),
01282       IRENA1        => irena1_ii,
01283       EWA1          => ewa1_ii,
01284       HEINZ1        => heinz1_ii,
01285       ANDREJ1       => andrej1_ii,
01286       MARKO1        => marko1_ii,
01287       WILLIAM1      => william1_ii,
01288       HARRIS1       => harris1_ii,
01289       HELMUT1       => helmut1_ii,
01290       S_IRENA1      => sirena1_ii,
01291       S_EWA1        => sewa1_ii,
01292       S_ANDREJ1     => sandrej1_ii,
01293       S_HEINZ1      => sheinz1_ii,
01294       S_MARKO1      => smarko1_ii,
01295       S_WILLIAM1    => swilliam1_ii,
01296       S_HARRIS1     => sharris1_ii,
01297       S_HELMUT1     => shelmut1_ii,
01298       IRENA2        => irena2_ii,
01299       EWA2          => ewa2_ii,
01300       HEINZ2        => heinz2_ii,
01301       ANDREJ2       => andrej2_ii,
01302       MARKO2        => marko2_ii,
01303       WILLIAM2      => william2_ii,
01304       HARRIS2       => harris2_ii,
01305       HELMUT2       => helmut2_ii,
01306       S_IRENA2      => sirena2_ii,
01307       S_EWA2        => sewa2_ii,
01308       S_ANDREJ2     => sandrej2_ii,
01309       S_HEINZ2      => sheinz2_ii,
01310       S_MARKO2      => smarko2_ii,
01311       S_WILLIAM2    => swilliam2_ii,
01312       S_HARRIS2     => sharris2_ii,
01313       S_HELMUT2     => shelmut2_ii,
01314       VLD           => delta_vld_d,
01315       DELTA_TOUT    => delta_t_d_i
01316       );
01317 
01318 
01319   use_TWcoin : if kUseTimeWin = true generate
01320 
01321     irena1_i   <= "00" & algo_data(190 downto 185);
01322     irena2_i   <= "00" & algo_data(178 downto 173);
01323     ewa1_i     <= "00" & algo_data(166 downto 161);
01324     ewa2_i     <= "00" & algo_data(154 downto 149);
01325     andrej1_i  <= "00" & algo_data(142 downto 137);
01326     andrej2_i  <= "00" & algo_data(130 downto 125);
01327     heinz1_i   <= "00" & algo_data(118 downto 113);
01328     heinz2_i   <= "00" & algo_data(106 downto 101);
01329     marko1_i   <= "00" & algo_data(94 downto 89);
01330     marko2_i   <= "00" & algo_data(82 downto 77);
01331     william1_i <= "00" & algo_data(70 downto 65);
01332     william2_i <= "00" & algo_data(58 downto 53);
01333     harris1_i  <= "00" & algo_data(46 downto 41);
01334     harris2_i  <= "00" & algo_data(34 downto 29);
01335     helmut1_i  <= "00" & algo_data(22 downto 17);
01336     helmut2_i  <= "00" & algo_data(10 downto 5);
01337 
01338     sirena1_i   <= algo_data(191);
01339     sirena2_i   <= algo_data(179);
01340     sewa1_i     <= algo_data(167);
01341     sewa2_i     <= algo_data(155);
01342     sandrej1_i  <= algo_data(143);
01343     sandrej2_i  <= algo_data(131);
01344     sheinz1_i   <= algo_data(119);
01345     sheinz2_i   <= algo_data(107);
01346     smarko1_i   <= algo_data(95);
01347     smarko2_i   <= algo_data(83);
01348     swilliam1_i <= algo_data(71);
01349     swilliam2_i <= algo_data(59);
01350     sharris1_i  <= algo_data(47);
01351     sharris2_i  <= algo_data(35);
01352     shelmut1_i  <= algo_data(23);
01353     shelmut2_i  <= algo_data(11);
01354 
01355     intime_cuts : intime
01356       port map
01357       (
01358         CLK           => BCLK,
01359         UPPER_BOUND_A => colwinh(5 downto 0),
01360         LOWER_BOUND_A => colwinl(5 downto 0),
01361         UPPER_BOUND_C => colwinh(5 downto 0),
01362         LOWER_BOUND_C => colwinl(5 downto 0),
01363         IRENA1        => irena1_i,
01364         EWA1          => ewa1_i,
01365         HEINZ1        => heinz1_i,
01366         ANDREJ1       => andrej1_i,
01367         MARKO1        => marko1_i,
01368         WILLIAM1      => william1_i,
01369         HARRIS1       => harris1_i,
01370         HELMUT1       => helmut1_i,
01371         IRENA2        => irena2_i,
01372         EWA2          => ewa2_i,
01373         HEINZ2        => heinz2_i,
01374         ANDREJ2       => andrej2_i,
01375         MARKO2        => marko2_i,
01376         WILLIAM2      => william2_i,
01377         HARRIS2       => harris2_i,
01378         HELMUT2       => helmut2_i,
01379         S_IRENA1      => sirena1_i,
01380         S_EWA1        => sewa1_i,
01381         S_HEINZ1      => sheinz1_i,
01382         S_ANDREJ1     => sandrej1_i,
01383         S_MARKO1      => smarko1_i,
01384         S_WILLIAM1    => swilliam1_i,
01385         S_HARRIS1     => sharris1_i,
01386         S_HELMUT1     => shelmut1_i,
01387         S_IRENA2      => sirena2_i,
01388         S_EWA2        => sewa2_i,
01389         S_HEINZ2      => sheinz2_i,
01390         S_ANDREJ2     => sandrej2_i,
01391         S_MARKO2      => smarko2_i,
01392         S_WILLIAM2    => swilliam2_i,
01393         S_HARRIS2     => sharris2_i,
01394         S_HELMUT2     => shelmut2_i,
01395         IRENA1_O      => irena1_ii,
01396         EWA1_O        => ewa1_ii,
01397         HEINZ1_O      => heinz1_ii,
01398         ANDREJ1_O     => andrej1_ii,
01399         MARKO1_O      => marko1_ii,
01400         WILLIAM1_O    => william1_ii,
01401         HARRIS1_O     => harris1_ii,
01402         HELMUT1_O     => helmut1_ii,
01403         IRENA2_O      => irena2_ii,
01404         EWA2_O        => ewa2_ii,
01405         HEINZ2_O      => heinz2_ii,
01406         ANDREJ2_O     => andrej2_ii,
01407         MARKO2_O      => marko2_ii,
01408         WILLIAM2_O    => william2_ii,
01409         HARRIS2_O     => harris2_ii,
01410         HELMUT2_O     => helmut2_ii,
01411         S_IRENA1_O    => sirena1_ii,
01412         S_EWA1_O      => sewa1_ii,
01413         S_HEINZ1_O    => sheinz1_ii,
01414         S_ANDREJ1_O   => sandrej1_ii,
01415         S_MARKO1_O    => smarko1_ii,
01416         S_WILLIAM1_O  => swilliam1_ii,
01417         S_HARRIS1_O   => sharris1_ii,
01418         S_HELMUT1_O   => shelmut1_ii,
01419         S_IRENA2_O    => sirena2_ii,
01420         S_EWA2_O      => sewa2_ii,
01421         S_HEINZ2_O    => sheinz2_ii,
01422         S_ANDREJ2_O   => sandrej2_ii,
01423         S_MARKO2_O    => smarko2_ii,
01424         S_WILLIAM2_O  => swilliam2_ii,
01425         S_HARRIS2_O   => sharris2_ii,
01426         S_HELMUT2_O   => shelmut2_ii
01427         );
01428 
01429     delta_vld2_a <= delta_vld_a when rising_edge(BCLK);
01430     delta_vld2_b <= delta_vld_b when rising_edge(BCLK);
01431     delta_vld2_c <= delta_vld_c when rising_edge(BCLK);
01432     delta_vld2_d <= delta_vld_d when rising_edge(BCLK);
01433     
01434   end generate use_TWcoin;
01435 
01436   -- \details no time windows
01437   noTWcoin : if kUseTimeWin = false generate
01438     
01439     irena1_i     <= (others => '0');
01440     irena2_i     <= (others => '0');
01441     ewa1_i       <= (others => '0');
01442     ewa2_i       <= (others => '0');
01443     andrej1_i    <= (others => '0');
01444     andrej2_i    <= (others => '0');
01445     heinz1_i     <= (others => '0');
01446     heinz2_i     <= (others => '0');
01447     marko1_i     <= (others => '0');
01448     marko2_i     <= (others => '0');
01449     william1_i   <= (others => '0');
01450     william2_i   <= (others => '0');
01451     harris1_i    <= (others => '0');
01452     harris2_i    <= (others => '0');
01453     helmut1_i    <= (others => '0');
01454     helmut2_i    <= (others => '0');
01455     delta_vld2_a <= '0';
01456     delta_vld2_b <= '0';
01457     delta_vld2_c <= '0';
01458     delta_vld2_d <= '0';
01459     
01460   end generate noTWcoin;
01461 
01462 -------------------------------------------------------------------------------
01463 --                              Statistics
01464 -------------------------------------------------------------------------------
01465 
01466   rate_block <= '1' when RESET = '1' else
01467                 '1' when MAIN_FSM_ST = "00000001" or MAIN_FSM_ST = "00000011" or
01468                 MAIN_FSM_ST = "00000010" or MAIN_FSM_ST = "00000111" or
01469                 MAIN_FSM_ST = "00000100" or MAIN_FSM_ST = "00000000" or
01470                 arp_done = '0' else
01471                 '0';
01472 
01473 
01474   count_coins : process (BCLK)
01475   begin  -- process count_coins
01476     if BCLK'event and BCLK = '1' then   -- rising clock edge
01477       if (RESET or rate_reset_i or rate_block) = '1' then
01478         cnt_coin <= (others => '0');
01479       elsif delta_vld_a = '1' then
01480         cnt_coin <= cnt_coin + 1;
01481       else
01482         cnt_coin <= cnt_coin;
01483       end if;
01484     end if;
01485   end process count_coins;
01486 
01487 
01488   count_backa : process (BCLK)
01489   begin  -- process count_backa
01490     if BCLK'event and BCLK = '1' then   -- rising clock edge
01491       if (RESET or rate_reset_i or rate_block) = '1' then
01492         cnt_backa <= (others => '0');
01493       elsif delta_vld_backa = '1' then
01494         cnt_backa <= cnt_backa + 1;
01495       else
01496         cnt_backa <= cnt_backa;
01497       end if;
01498     end if;
01499   end process count_backa;
01500 
01501 
01502   count_backc : process (BCLK)
01503   begin  -- process count_backc
01504     if BCLK'event and BCLK = '1' then   -- rising clock edge
01505       if (RESET or rate_reset_i or rate_block) = '1' then
01506         cnt_backc <= (others => '0');
01507       elsif delta_vld_backc = '1' then
01508         cnt_backc <= cnt_backc + 1;
01509       else
01510         cnt_backc <= cnt_backc;
01511       end if;
01512     end if;
01513   end process count_backc;
01514 
01515 
01516   count_ch1 : process (BCLK)
01517   begin
01518     if BCLK'event and BCLK = '1' then   -- rising clock edge
01519       if (RESET or rate_reset_i or rate_block or rio_trip(0)) = '1' then
01520         cnt_ch1 <= (others => '0');
01521       else
01522         if input_en_status(0) = '1' then
01523           cnt_ch1 <= cnt_ch1 + proc_data_ii(191) + proc_data_ii(179);
01524         end if;
01525       end if;
01526     end if;
01527   end process count_ch1;
01528 
01529 
01530   count_ch2 : process (BCLK)
01531   begin
01532     if BCLK'event and BCLK = '1' then   -- rising clock edge
01533       if (RESET or rate_reset_i or rate_block or rio_trip(1)) = '1' then
01534         cnt_ch2 <= (others => '0');
01535       else
01536         if input_en_status(1) = '1' then
01537           cnt_ch2 <= cnt_ch2 + proc_data_ii(167) + proc_data_ii(155);
01538         end if;
01539       end if;
01540     end if;
01541   end process count_ch2;
01542 
01543 
01544   count_ch3 : process (BCLK)
01545   begin
01546     if BCLK'event and BCLK = '1' then   -- rising clock edge
01547       if (RESET or rate_reset_i or rate_block or rio_trip(2)) = '1' then
01548         cnt_ch3 <= (others => '0');
01549       else
01550         if input_en_status(2) = '1' then
01551           cnt_ch3 <= cnt_ch3 + proc_data_ii(143) + proc_data_ii(131);
01552         end if;
01553       end if;
01554     end if;
01555   end process count_ch3;
01556 
01557 
01558   count_ch4 : process (BCLK)
01559   begin
01560     if BCLK'event and BCLK = '1' then   -- rising clock edge
01561       if (RESET or rate_reset_i or rate_block or rio_trip(3)) = '1' then
01562         cnt_ch4 <= (others => '0');
01563       else
01564         if input_en_status(3) = '1' then
01565           cnt_ch4 <= cnt_ch4 + proc_data_ii(119) + proc_data_ii(107);
01566         end if;
01567       end if;
01568     end if;
01569   end process count_ch4;
01570 
01571 
01572   count_ch5 : process (BCLK)
01573   begin
01574     if BCLK'event and BCLK = '1' then   -- rising clock edge
01575       if (RESET or rate_reset_i or rate_block or rio_trip(4)) = '1' then
01576         cnt_ch5 <= (others => '0');
01577       else
01578         if input_en_status(4) = '1' then
01579           cnt_ch5 <= cnt_ch5 + proc_data_ii(95) + proc_data_ii(83);
01580         end if;
01581       end if;
01582     end if;
01583   end process count_ch5;
01584 
01585 
01586   count_ch6 : process (BCLK)
01587   begin
01588     if BCLK'event and BCLK = '1' then   -- rising clock edge
01589       if (RESET or rate_reset_i or rate_block or rio_trip(5)) = '1' then
01590         cnt_ch6 <= (others => '0');
01591       else
01592         if input_en_status(5) = '1' then
01593           cnt_ch6 <= cnt_ch6 + proc_data_ii(71) + proc_data_ii(59);
01594         end if;
01595       end if;
01596     end if;
01597   end process count_ch6;
01598 
01599 
01600   count_ch7 : process (BCLK)
01601   begin
01602     if BCLK'event and BCLK = '1' then   -- rising clock edge
01603       if (RESET or rate_reset_i or rate_block or rio_trip(6)) = '1' then
01604         cnt_ch7 <= (others => '0');
01605       else
01606         if input_en_status(6) = '1' then
01607           cnt_ch7 <= cnt_ch7 + proc_data_ii(47) + proc_data_ii(35);
01608         end if;
01609       end if;
01610     end if;
01611   end process count_ch7;
01612 
01613 
01614   count_ch8 : process (BCLK)
01615   begin
01616     if BCLK'event and BCLK = '1' then   -- rising clock edge
01617       if (RESET or rate_reset_i or rate_block or rio_trip(7)) = '1' then
01618         cnt_ch8 <= (others => '0');
01619       else
01620         if input_en_status(7) = '1' then
01621           cnt_ch8 <= cnt_ch8 + proc_data_ii(23) + proc_data_ii(11);
01622         end if;
01623       end if;
01624     end if;
01625   end process count_ch8;
01626 
01627 -------------------------------------------------------------------------------
01628 --                      Readout FSM & Control Signals
01629 -------------------------------------------------------------------------------          
01630 
01631   mem_reset_short   <= RESET or raw_trans_complete or stop_pc_i;  --* reset memory address counters when data dump done
01632   trans_complete    <= raw_trans_complete or stop_pc_i;  --* end of dump flag
01633   TRIGGER_INHIBIT_N <= arp_done;  -- some safety measures so we dont send before completing the ARPs
01634   read_out_i        <= READ_OUT and arp_done;
01635 
01636 
01637   mem_reset_extend : extend_test
01638     generic map (
01639       LEN => 5 )
01640     port map
01641     (
01642       CLK  => REFCLK_P ,
01643       RES  => RESET,
01644       ENDM => open,
01645       A    => mem_reset_short,
01646       Y    => mem_reset
01647       );
01648 
01649 
01650   complete_extend : extend_test
01651     generic map (
01652       LEN => 3 )
01653     port map
01654     (
01655       CLK  => REFCLK_P ,
01656       RES  => RESET,
01657       ENDM => open,
01658       A    => trans_complete,
01659       Y    => READ_DONE
01660       );
01661 
01662   rw_proc_i   <= read_out_i;
01663   rw_raw_i    <= read_out_i;
01664   en_proc     <= not empty_proc when rw_proc_i = '0' else en_rd_proc;  --* enable for memories & their counters
01665   en_raw      <= not empty_raw  when rw_raw_i = '0' else en_rd_raw;
01666   en_cnt_proc <= en_proc        when over_proc_i = '0' else rw_proc_i and en_proc;
01667   en_cnt_raw  <= en_raw         when over_raw_i = '0' else rw_raw_i and en_raw;
01668 
01669 
01670 
01671 
01672 
01673 
01674   sw_to_err : process (REFCLK_P, RESET)
01675   begin  -- process sw_to_err
01676     if RESET = '1' then                 -- asynchronous reset (active high)
01677       swtoerr_ff <= '0';
01678     elsif REFCLK_P'event and REFCLK_P = '1' then  -- rising clock edge
01679       if SEND_ERR_MSG = '1' then
01680         swtoerr_ff <= '1';
01681       else
01682         swtoerr_ff <= '0';
01683       end if;
01684       if pktdone = '1' then
01685         swtoerr_ff <= '0';
01686       end if;
01687     end if;
01688   end process sw_to_err;
01689 
01690 
01691   readout_controller_fsm : process(REFCLK_P)
01692   begin
01693     if REFCLK_P'event and REFCLK_P = '1' then
01694       if RESET = '1' then
01695         cs          <= r_idle;
01696         start_rdout <= '0';
01697       else
01698         case cs is
01699           when r_idle =>
01700             if read_out_i = '1' then
01701               if kUseDDR = true then
01702                 cs <= r_proc;
01703               else
01704                 cs <= r_raw;
01705               end if;
01706               start_rdout <= '1';
01707             else
01708               cs          <= r_idle;
01709               start_rdout <= '0';
01710             end if;
01711           when r_proc =>
01712             if swtoerr_ff = '1' then
01713               cs <= r_err;
01714             else
01715               start_rdout <= '0';
01716               if proc_trans_complete = '1' then
01717                 cs <= r_raw;
01718               else
01719                 cs <= r_proc;
01720               end if;
01721             end if;
01722           when r_raw =>
01723             if swtoerr_ff = '1' then
01724               cs <= r_err;
01725             else
01726               start_rdout <= '0';
01727               if raw_trans_complete = '1' then
01728                 cs <= r_idle;
01729               else
01730                 cs <= r_raw;
01731               end if;
01732             end if;
01733           when r_err =>
01734             if err_msg_complete = '1' then
01735               cs <= r_idle;
01736             else
01737               cs <= r_err;
01738             end if;
01739           when others =>
01740             start_rdout <= '0';
01741             cs          <= r_err;
01742         end case;
01743       end if;
01744     end if;
01745   end process readout_controller_fsm;
01746 
01747 
01748   shift_clear_ddr2 : process(REFCLK_P)
01749   begin
01750     if REFCLK_P'event and REFCLK_P = '1' then
01751       clr_ddr2   <= clr_shift2(4);
01752       clr_shift2 <= clr_shift2(3 downto 0) & mem_reset;
01753     end if;
01754   end process shift_clear_ddr2;
01755 
01756   shift_clear_ddr : process(BCLK4X_P)
01757   begin
01758     if BCLK4X_P'event and BCLK4X_P = '1' then
01759       clr_ddr   <= clr_shift(4);
01760       clr_shift <= clr_shift(3 downto 0) & mem_reset;
01761     end if;
01762   end process shift_clear_ddr;
01763 
01764 -------------------------------------------------------------------------------
01765 --                              DDR
01766 -------------------------------------------------------------------------------          
01767 
01768 
01769   useDDR : if kUseDDR = true generate
01770 
01771     --* issue right amount of read command bursts per udp-packet
01772 
01773     readout_controller_proc : process(BCLK4X_P)
01774       variable cnt_br_proc : integer range 0 to 31 := 0;
01775     begin
01776       if BCLK4X_P'event and BCLK4X_P = '1' then
01777         if mem_reset = '1' then
01778           en_rd_proc      <= '0';
01779           cnt_br_proc     := 0;
01780           pkt_rddone_proc <= '0';
01781         else
01782           pkt_rddone_proc <= '0';
01783           if cs = r_proc and en_mem = '1' then
01784             if start_pkt = '1' then
01785               cnt_br_proc := 0;
01786             elsif cnt_br_proc < 21 then
01787 --* count "empty" bursts, we need 6 rd-bursts, 1 burst = 4 clk cycles => cnt_br
01788 --* = 21 during first cycle of 6 empty burst
01789               if burstind_proc = '1' then
01790                 cnt_br_proc := cnt_br_proc + 1;
01791               else
01792                 cnt_br_proc := cnt_br_proc;
01793               end if;
01794               en_rd_proc <= '1';
01795             else
01796               if cnt_br_proc = 21 then
01797                 pkt_rddone_proc <= '1';
01798                 cnt_br_proc     := cnt_br_proc + 1;
01799               else
01800                 cnt_br_proc := cnt_br_proc;
01801                 en_rd_proc  <= '0';
01802               end if;
01803             end if;
01804           else
01805             cnt_br_proc := 0;
01806             en_rd_proc  <= '0';
01807           end if;
01808         end if;
01809       end if;
01810     end process readout_controller_proc;
01811 
01812 
01813     proc_buffer : ddr_data_buffer
01814       port map
01815       (
01816         CLK_A    => DDRCLK,
01817         CLK_B    => BCLK,
01818         RESET    => mem_reset,
01819         WEN      => CAPTURE,
01820         REN      => fetch_proc ,
01821         EMPTY    => empty_proc,
01822         DATA_IN  => proc_data_i,
01823         DATA_OUT => proc_data_ddr
01824         );
01825 
01826 
01827     proc_memory : ram_user_backend
01828       port map
01829       (
01830         cntrl0_DDR_DQ    => cntrl0_DDR_DQ,
01831         cntrl0_DDR_A     => cntrl0_DDR_A,
01832         cntrl0_DDR_BA    => cntrl0_DDR_BA,
01833         cntrl0_DDR_CKE   => cntrl0_DDR_CKE,
01834         cntrl0_DDR_CS_N  => cntrl0_DDR_CS_N,
01835         cntrl0_DDR_RAS_N => cntrl0_DDR_RAS_N,
01836         cntrl0_DDR_CAS_N => cntrl0_DDR_CAS_N,
01837         cntrl0_DDR_WE_N  => cntrl0_DDR_WE_N,
01838         cntrl0_DDR_DM    => cntrl0_DDR_DM,
01839         cntrl0_DDR_DQS   => cntrl0_DDR_DQS,
01840         cntrl0_DDR_CK    => cntrl0_DDR_CK,
01841         cntrl0_DDR_CK_N  => cntrl0_DDR_CK_N,
01842         SYSCLK_P         => DDRCLK,
01843         SYSCLK_N         => '0',
01844         CLK200_P         => REFCLK_P,
01845         CLK200_N         => '0',
01846         SYS_RESET_IN     => RESET,
01847         ADDR_RES         => mem_reset,
01848         R_W              => rw_proc_i,
01849         LED_CONTR        => open,
01850         LED_R            => open,
01851         EN               => en_proc,
01852         HALT             => fetch_proc,
01853         RDBURST_END      => burstind_proc,
01854         VALID_OUT        => proc_vld,
01855         DATA_IN          => proc_data_ddr,
01856         READ_DATA_OUT    => proc_data_eth_i
01857         );
01858 
01859     --* reset for ddr access counter
01860     proc_cnt_reset <= (proc_trans_complete and (not rw_proc_i)) or mem_reset;
01861 
01862 
01863     countddrreads : cnt_ddr_rd
01864       port map
01865       (
01866         RESET => proc_cnt_reset,
01867         CLK   => BCLK4X_P,
01868         EN    => en_cnt_proc ,
01869         DONE  => proc_trans_complete
01870         );
01871 
01872 
01873     overflow_flag_proc : process (BCLK4X_P, mem_reset)
01874     begin  -- process overflow_flag_raw
01875       if mem_reset = '1' then           -- asynchronous reset (active high)
01876         over_proc_i <= '0';
01877       elsif BCLK4X_P'event and BCLK4X_P = '1' then  -- rising clock edge
01878         if rw_proc_i = '0' and proc_trans_complete = '1' then
01879           over_proc_i <= '1';
01880         end if;
01881       end if;
01882     end process overflow_flag_proc;
01883 
01884     ethbufres_proc_i <= mem_reset;      -- or ethbufres_proc;
01885 
01886 
01887     ddreth_buf : ddr_eth_buf
01888       port map
01889       (
01890         CLK_WR   => DDRCLK,
01891         CLK_RD   => emac_clk_buf,
01892         RES      => ethbufres_proc_i,
01893         RD       => fetch_proc_eth,
01894         WR       => wr_buf_proc,
01895         DATA_IN  => proc_data_eth_i,
01896         DATA_OUT => proc_byte
01897         );
01898 
01899     pkt_rddone_proc1 <= pkt_rddone_proc when rising_edge(DDRCLK);
01900     wr_buf_proc_i    <= wr_buf_proc     when rising_edge(DDRCLK);
01901 
01902 
01903     ddr_udp_chksum_1 : ddr_chksum_cal
01904       port map(
01905         CLK        => DDRCLK ,
01906         RESET      => mem_reset,
01907         EN         => wr_buf_proc_i,
01908         DATA_IN    => proc_data_eth_i ,
01909         WRITE_DONE => pkt_rddone_proc1 ,
01910         CAL_COMPL  => open,
01911         READ_DATA  => get_proc_chksum ,
01912         DATA_OUT   => proc_chksum_1
01913         );
01914 
01915     proc_chksum_2 <= (others => '0');
01916 
01917 
01918     ddr_clr_extend : extend_test
01919       generic map (
01920         LEN => 47 )
01921       port map
01922       (
01923         CLK   => BCLK4X_P,
01924         RES   => RESET ,
01925         ENDM  => ethbufres_proc,
01926         A     => clr_ddr ,
01927         Y    => clear_proc 
01928         ); 
01929 
01930   end generate useDDR;
01931 
01932 
01933   noDDR : if kUseDDR = false generate
01934     
01935     proc_byte <= zero_byte;
01936     dq : for I in 31 downto 0 generate
01937 
01938       IOBUF_inst : IOBUF
01939         port map (
01940           O   => open ,                   -- Buffer output
01941           IO  => cntrl0_DDR_DQ(I),  -- Buffer inout port (connect directly to top-level port)
01942           I   => '0' ,                    -- Buffer input
01943           T  => '1'                     -- 3-state enable input 
01944           );
01945     end generate dq;
01946     dqs : for I in 3 downto 0 generate
01947 
01948       IOBUF_inst2 : IOBUF
01949         port map (
01950           O   => open ,                   -- Buffer output
01951           IO  => cntrl0_DDR_DQS(I),  -- Buffer inout port (connect directly to top-level port)
01952           I   => '0' ,                    -- Buffer input
01953           T  => '1'                     -- 3-state enable input 
01954           );
01955     end generate dqs;
01956     a : for I in 12 downto 0 generate
01957 
01958       OBUF_inst : OBUF
01959         port map (
01960           O => cntrl0_DDR_A(I),         -- Buffer output
01961           I => '0'                      -- Buffer input
01962           );
01963     end generate a;
01964     ba : for I in 1 downto 0 generate
01965 
01966       OBUF_inst2 : OBUF
01967         port map (
01968           O => cntrl0_DDR_BA(I),        -- Buffer output
01969           I => '0'                      -- Buffer input
01970           );
01971     end generate ba;
01972 
01973     OBUF_inst3 : OBUF
01974       port map (
01975         O => cntrl0_DDR_CKE,            -- Buffer output
01976         I => '0'                        -- Buffer input
01977         );
01978 
01979     OBUF_inst4 : OBUF
01980       port map (
01981         O => cntrl0_DDR_CS_N,           -- Buffer output
01982         I => '0'                        -- Buffer input
01983         );
01984 
01985     OBUF_inst5 : OBUF
01986       port map (
01987         O => cntrl0_DDR_RAS_N,          -- Buffer output
01988         I => '0'                        -- Buffer input
01989         );
01990 
01991     OBUF_inst6 : OBUF
01992       port map (
01993         O => cntrl0_DDR_CAS_N,          -- Buffer output
01994         I => '0'                        -- Buffer input
01995         );
01996 
01997     OBUF_inst7 : OBUF
01998       port map (
01999         O => cntrl0_DDR_WE_N,           -- Buffer output
02000         I => '0'                        -- Buffer input
02001         );
02002 
02003     dm : for I in 3 downto 0 generate
02004 
02005       OBUF_inst8 : OBUF
02006         port map (
02007           O => cntrl0_DDR_DM(I),        -- Buffer output
02008           I => '0'                      -- Buffer input
02009           );
02010     end generate dm;
02011 
02012     OBUF_inst9 : OBUF
02013       port map (
02014         O => cntrl0_DDR_CK,             -- Buffer output
02015         I => '0'                        -- Buffer input
02016         );
02017 
02018     OBUF_inst10 : OBUF
02019       port map (
02020         O => cntrl0_DDR_CK_N,           -- Buffer output
02021         I => '0'                        -- Buffer input
02022         );
02023 
02024   end generate noDDR;
02025 
02026 -------------------------------------------------------------------------------
02027 --                              DDR2
02028 -------------------------------------------------------------------------------      
02029 
02030 
02031   readout_controller_raw : process(REFCLK_P)
02032     variable cnt_br_raw : integer range 0 to 15 := 0;
02033   begin
02034     if REFCLK_P'event and REFCLK_P = '1' then
02035       if mem_reset = '1' then
02036         en_rd_raw      <= '0';
02037         cnt_br_raw     := 0;
02038         pkt_rddone_raw <= '0';
02039       else
02040         pkt_rddone_raw <= '0';
02041         if cs = r_raw and en_mem = '1' then
02042           if start_pkt = '1' then
02043             cnt_br_raw := 0;
02044           elsif cnt_br_raw < 9 then
02045             if burstind_raw = '1' then
02046 --* count "empty" bursts, we need 3 rd-bursts, 1 burst = 4 clk cycles => cnt_br
02047 --* = 9 during first cycle of 3 empty burst
02048               cnt_br_raw := cnt_br_raw + 1;
02049             else
02050               cnt_br_raw := cnt_br_raw;
02051             end if;
02052             en_rd_raw <= '1';
02053           else
02054             if cnt_br_raw = 9 then
02055               pkt_rddone_raw <= '1';
02056               cnt_br_raw     := cnt_br_raw + 1;
02057             else
02058               cnt_br_raw := cnt_br_raw;
02059               en_rd_raw  <= '0';
02060             end if;
02061           end if;
02062         end if;
02063       end if;
02064     end if;
02065   end process readout_controller_raw;
02066 
02067 
02068   --DDR2CLK_BUF : BUFG port map (O => ddr2_clk, I => REFCLK_P);
02069   ddr2_clk <= REFCLK_P;
02070 
02071 
02072   raw_buffer : ddr2_data_buffer
02073     port map
02074     (
02075       CLKA     => REFCLK_P ,
02076       CLKB     => BCLK2X_P ,
02077       RESET    => mem_reset ,
02078       WEN      => CAPTURE ,
02079       REN      => fetch_raw ,
02080       EMPTY    => empty_raw ,
02081       DATA_IN  => raw_data_i,
02082       DATA_OUT => raw_data_ddr 
02083       );
02084 
02085 
02086   raw_memory : ddr2_usr_be
02087     port map
02088     (
02089       cntrl0_DDR2_DQ      => cntrl0_DDR2_DQ,
02090       cntrl0_DDR2_DQS     => cntrl0_DDR2_DQS,
02091       cntrl0_DDR2_DQS_N   => cntrl0_DDR2_DQS_N,
02092       cntrl0_DDR2_A       => cntrl0_DDR2_A,
02093       cntrl0_DDR2_BA      => cntrl0_DDR2_BA,
02094       cntrl0_DDR2_RAS_N   => cntrl0_DDR2_RAS_N,
02095       cntrl0_DDR2_CAS_N   => cntrl0_DDR2_CAS_N,
02096       cntrl0_DDR2_WE_N    => cntrl0_DDR2_WE_N,
02097       cntrl0_DDR2_RESET_N => cntrl0_DDR2_RESET_N,
02098       cntrl0_DDR2_CS_N    => cntrl0_DDR2_CS_N,
02099       cntrl0_DDR2_ODT     => cntrl0_DDR2_ODT,
02100       cntrl0_DDR2_CKE     => cntrl0_DDR2_CKE,
02101       cntrl0_DDR2_DM      => cntrl0_DDR2_DM,
02102       cntrl0_DDR2_CK      => cntrl0_DDR2_CK,
02103       cntrl0_DDR2_CK_N    => cntrl0_DDR2_CK_N,
02104       COMP_OUT1           => open,
02105       COMP_OUT2           => open,
02106       LED_CONTR           => open,
02107       LED_R               => open,
02108       SYSCLK              => ddr2_clk,
02109       CLK_SLOW            => BCLK,
02110       RESET_IN            => RESET,
02111       ADDR_RES            => mem_reset,
02112       EN                  => en_raw,
02113       R_W                 => rw_raw_i,
02114       FETCH               => fetch_raw,
02115       VALID_OUT           => raw_vld,
02116       RDBURST_END         => burstind_raw,
02117       DATA_IN             => raw_data_ddr,
02118       DATA_OUT            => raw_data_eth_i
02119       );        
02120 
02121   --* reset for ddr2 access counter
02122   raw_cnt_reset <= (raw_trans_complete and (not rw_raw_i)) or mem_reset;
02123 
02124 
02125   countddr2reads : cnt_ddr2_rd
02126     port map
02127     (
02128       RESET => raw_cnt_reset,
02129       CLK   => REFCLK_P ,
02130       EN    => en_cnt_raw,
02131       DONE  => raw_trans_complete
02132       );
02133 
02134 
02135   overflow_flag_raw : process (REFCLK_P, mem_reset)
02136   begin  -- process overflow_flag_raw
02137     if mem_reset = '1' then             -- asynchronous reset (active high)
02138       over_raw_i <= '0';
02139     elsif REFCLK_P'event and REFCLK_P = '1' then  -- rising clock edge
02140       if rw_raw_i = '0' and raw_trans_complete = '1' then
02141         over_raw_i <= '1';
02142       end if;
02143     end if;
02144   end process overflow_flag_raw;
02145 
02146   ethbufres_raw_i <= mem_reset or ethbufres_raw;
02147 
02148 
02149   ddr2_eth_buf : eth_buf
02150     port map
02151     (
02152       CLK_WR   => REFCLK_P,
02153       CLK_RD   => emac_clk_buf ,
02154       RES      => ethbufres_raw_i,
02155       RD       => fetch_raw_eth,
02156       WR       => wr_buf_raw ,
02157       DATA_IN  => raw_data_eth_i,
02158       DATA_OUT => raw_byte
02159       );
02160 
02161   pkt_rddone_raw1 <= pkt_rddone_raw when rising_edge(REFCLK_P);
02162   wr_buf_raw_i    <= wr_buf_raw     when rising_edge(REFCLK_P);
02163 
02164 
02165   ddr2_udp_chksum_1 : ddr2_chksum_cal
02166     port map(
02167       CLK         => REFCLK_P,
02168       RESET      => mem_reset,
02169       EN         => wr_buf_raw_i,
02170       DATA_IN    => raw_data_eth_i_1,
02171       WRITE_DONE => pkt_rddone_raw1,
02172       CAL_COMPL  => open,
02173       READ_DATA  => get_raw_chksum,
02174       DATA_OUT   => raw_chksum_1
02175       );
02176 
02177   raw_chksum_2 <= (others => '0');
02178 
02179 
02180   ddr2_clr_extend : extend_test
02181     generic map (
02182       LEN => 23 )
02183     port map
02184     (
02185       CLK  => REFCLK_P ,
02186       RES  => RESET,
02187       ENDM => ethbufres_raw,
02188       A    => clr_ddr2 ,
02189       Y    => clear_raw
02190       );
02191 
02192 -------------------------------------------------------------------------------
02193 --                              EMAC 
02194 -------------------------------------------------------------------------------
02195 
02196 --* FSM to handle status msg & other msgs
02197 
02198   clk_hz_sync : edge
02199     port map (
02200       CLK   => EMAC_CLK ,
02201       A     => CLK_HZ ,
02202       PULSE => second
02203       );
02204 
02205 
02206   set_second_active : process (EMAC_CLK, RESET)
02207   begin  -- process set_second_active
02208     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02209       if RESET = '1' then
02210         second_active <= '0';
02211       else
02212         if arp_done = '1' then          --* start only after arp ann is done
02213           if stat_msg_done = '1' then
02214             second_active <= '0';
02215           elsif (second or get_stats) = '1' then
02216             second_active <= '1';
02217           end if;
02218         end if;
02219       end if;
02220     end if;
02221   end process set_second_active;
02222 
02223 
02224   set_tdaq_active : process (EMAC_CLK, RESET)
02225   begin  -- process set_second_active
02226     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02227       if RESET = '1' then
02228         tdaq_active <= '0';
02229       else
02230         if arp_done = '1' then          --* start only after arp ann is done
02231           if tdaq_msg_done = '1' then
02232             tdaq_active <= '0';
02233           elsif send_tdaq_status = '1' then
02234             tdaq_active <= '1';
02235           end if;
02236         end if;
02237       end if;
02238     end if;
02239   end process set_tdaq_active;
02240 
02241 
02242   emac_manager : process (EMAC_CLK, RESET)
02243   begin  -- process emac_manager
02244     if RESET = '1' then                 -- asynchronous reset (active high)
02245       ems             <= e_idle;
02246       en_mem          <= '0';
02247       en_stat_mac_set <= '0';
02248       assemb_stat     <= '0';
02249       en_tdaq_mac_set <= '0';
02250       assemb_tdaq     <= '0';
02251       start_nxt_st    <= '0';
02252     elsif EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02253       en_mem          <= '0';
02254       en_stat_mac_set <= '0';
02255       assemb_stat     <= '0';
02256       en_tdaq_mac_set <= '0';
02257       assemb_tdaq     <= '0';
02258       start_nxt_st    <= '0';
02259 
02260       case ems is
02261         
02262         when e_idle =>
02263           if second_active = '1' then
02264             ems <= e_fillstat;
02265           elsif tdaq_active = '1' then
02266             ems <= e_filltdaq;
02267           elsif read_out_i = '1' then
02268             ems <= e_dump;
02269           end if;
02270 
02271         when e_dump =>
02272           en_mem <= '1';
02273           if (second_active and pktdone_ff) = '1' then
02274             ems <= e_fillstat;
02275           elsif (tdaq_active and pktdone_ff) = '1' then
02276             ems <= e_filltdaq;
02277           end if;
02278 
02279         when e_fillstat =>
02280           assemb_stat <= '1';
02281           if stat_asm_done_i = '1' then
02282             assemb_stat     <= '0';
02283             en_stat_mac_set <= '1';
02284             ems             <= e_stat;
02285           end if;
02286 
02287         when e_stat =>
02288           if stat_msg_done = '1' then
02289             if read_out_i = '1' then
02290               ems          <= e_dump;
02291               start_nxt_st <= '1';
02292             else
02293               ems <= e_idle;
02294             end if;
02295           else
02296             ems <= e_stat;
02297           end if;
02298 
02299         when e_filltdaq =>
02300           assemb_tdaq <= '1';
02301           if tdaq_asm_done_i = '1' then
02302             assemb_tdaq     <= '0';
02303             en_tdaq_mac_set <= '1';
02304             ems             <= e_tdaq;
02305           end if;
02306 
02307         when e_tdaq =>
02308           if tdaq_msg_done = '1' then
02309             if read_out_i = '1' then
02310               ems          <= e_dump;
02311               start_nxt_st <= '1';
02312             else
02313               ems <= e_idle;
02314             end if;
02315           else
02316             ems <= e_tdaq;
02317           end if;
02318           
02319         when others => null;
02320       end case;
02321     end if;
02322   end process emac_manager;
02323 
02324 --* multiplex enables from EMAC to different memories
02325   fetch_raw_eth   <= get_eth_byte when cs = r_raw and en_mem = '1' else '0';
02326   fetch_proc_eth  <= get_eth_byte when cs = r_proc and en_mem = '1' else '0';
02327   fetch_stat_eth  <= get_eth_byte when ems = e_stat and en_mem = '0' else '0';
02328   fetch_tdaq_eth  <= get_eth_byte when ems = e_tdaq and en_mem = '0' else '0';
02329   get_raw_chksum  <= get_chksum   when cs = r_raw and en_mem = '1' else '0';
02330   get_proc_chksum <= get_chksum   when cs = r_proc and en_mem = '1' else '0';
02331   get_stat_chksum <= get_chksum   when ems = e_stat and en_mem = '0' else '0';
02332   get_tdaq_chksum <= get_chksum   when ems = e_tdaq and en_mem = '0' else '0';
02333 
02334 --* set datatype ID
02335   datatype_i <= '1' when cs = r_raw else '0';
02336 
02337 --* if transfer is complete and a burst isn't finished (ie more rd cmds are issued
02338 --* to RAM) don't wait for data from RAM but write pattern to buffer; but
02339 --* situation may not arise => unreliable endmarker !!!
02340   wr_buf_raw <= en_rd_raw when (raw_trans_complete and read_out_i) = '1' else
02341                 raw_vld when read_out_i = '1' else
02342                 clear_raw;
02343   wr_buf_proc <= en_rd_proc when (proc_trans_complete and read_out_i) = '1' else
02344                  proc_vld when read_out_i = '1' else
02345                  clear_proc;
02346 
02347   --* multiplex data to EMAC      
02348   eth_byte <= raw_byte when cs = r_raw and en_mem = '1' else
02349               proc_byte when cs = r_proc and en_mem = '1' else
02350               stat_byte when ems = e_stat else
02351               tdaq_byte when ems = e_tdaq else
02352               zero_byte;
02353   --* multiplex checksum to EMAC  
02354   chksum_1 <= raw_chksum_1 when cs = r_raw and en_mem = '1' else
02355               proc_chksum_1 when cs = r_proc and en_mem = '1' else
02356               stat_chksum   when ems = e_stat and en_mem = '0' else
02357               tdaq_chksum   when ems = e_tdaq and en_mem = '0' else
02358               zero_byte & zero_byte;
02359   chksum_2 <= raw_chksum_2 when cs = r_raw and en_mem = '1' else
02360               proc_chksum_2 when cs = r_proc and en_mem = '1' else
02361               zero_byte & zero_byte;
02362 
02363 
02364   start_extend : extend_test
02365     generic map (
02366       LEN => 5 )
02367     port map
02368     (
02369       CLK  => REFCLK_P ,
02370       RES  => RESET,
02371       ENDM => open,
02372       A    => start_rdout,
02373       Y    => start_rdout_ext
02374       );
02375 
02376   emac_clk_buf <= EMAC_CLK;
02377   --* enable for EMAC
02378   eth_en_i     <= read_out_i;
02379   --* start next packet after ack & FSM is in dump mode or after dcs/tdaq packet is done and we're still in dump mode
02380   start_nxt    <= (ack_vld_ff and read_out_i) and (en_mem or start_nxt_st) when rising_edge(EMAC_CLK);
02381   --* start next pkt at beginning of dump, next dump pkt
02382   start_pkt    <= start_rdout_ext or start_nxt;
02383   --* increment pkt number when starting next dump packet
02384   inc_pktnr    <= start_pkt                                                when rising_edge(EMAC_CLK);
02385 
02386 
02387   pktdone_extend : extend_test
02388     generic map (
02389       LEN => 3 )
02390     port map
02391     (
02392       CLK  => EMAC_CLK ,
02393       RES  => RESET,
02394       ENDM => open,
02395       A    => pktdone ,
02396       Y    => pktdone_long 
02397       );
02398 
02399 
02400   pktdone_rsff : process (EMAC_CLK)
02401   begin  -- process pktdone_rsff
02402     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02403       if RESET = '1' then
02404         pktdone_ff <= '0';
02405       else
02406         if (assemb_tdaq or assemb_stat) = '1' then
02407           pktdone_ff <= '0';
02408         elsif pktdone = '1' then
02409           pktdone_ff <= '1';
02410         end if;
02411       end if;
02412     end if;
02413   end process pktdone_rsff;
02414 
02415 
02416   ackvld_rsff : process (EMAC_CLK)
02417   begin  -- process ackvld_rsff
02418     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02419       if RESET = '1' then
02420         ack_vld_ff <= '0';
02421       else
02422         if start_pkt = '1' then
02423           ack_vld_ff <= '0';
02424         elsif ack_vld = '1' then
02425           ack_vld_ff <= '1';
02426         end if;
02427       end if;
02428     end if;
02429   end process ackvld_rsff;
02430 
02431   stat_msg_done <= pktdone_long when ems = e_stat else '0';
02432   tdaq_msg_done <= pktdone_long when ems = e_tdaq else '0';
02433 
02434 
02435   start_pkt_rsff : process (EMAC_CLK)
02436   begin  -- process start_pkt_rsff
02437     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02438       if RESET = '1' then
02439         start_pkt_ff <= '0';
02440       else
02441         if pktdone = '1' then
02442           start_pkt_ff <= '0';
02443         elsif start_pkt = '1' then
02444           start_pkt_ff <= '1';
02445         end if;
02446       end if;
02447     end if;
02448   end process start_pkt_rsff;
02449 
02450 
02451   stat_pkt_rsff : process (EMAC_CLK)
02452   begin  -- process stat_pkt_rsff
02453     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02454       if RESET = '1' then
02455         en_stat_mac <= '0';
02456       else
02457         if stat_msg_rd_done = '1' then
02458           en_stat_mac <= '0';
02459         elsif en_stat_mac_set = '1' then
02460           en_stat_mac <= '1';
02461         end if;
02462       end if;
02463     end if;
02464   end process stat_pkt_rsff;
02465 
02466 
02467   tdaq_pkt_rsff : process (EMAC_CLK)
02468   begin  -- process stat_pkt_rsff
02469     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02470       if RESET = '1' then
02471         en_tdaq_mac <= '0';
02472       else
02473         if tdaq_msg_rd_done = '1' then
02474           en_tdaq_mac <= '0';
02475         elsif en_tdaq_mac_set = '1' then
02476           en_tdaq_mac <= '1';
02477         end if;
02478       end if;
02479     end if;
02480   end process tdaq_pkt_rsff;
02481 
02482 
02483   eth : ethernet_top
02484     port map
02485     (
02486       RESET           => RESET,
02487       PKT_CNT_RST     => mem_reset,
02488       CYCLE           => '0',
02489       INC_PKTCNT      => inc_pktnr,
02490       ARP_ANN         => arp_i,
02491       RD_READY        => rd_rdy_i,
02492       RD_OVER         => rd_ovr_i,
02493       STATUS_PKT      => en_stat_mac,
02494       TDAQ_STATUS_PKT => en_tdaq_mac,
02495       START           => start_pkt_ff,
02496       SEND_PKT_SE     => '0',
02497       ETH_EN          => eth_en_i,
02498       DATATYPE        => datatype_i,
02499       BYTE_IN         => eth_byte,
02500       GET_BYTE        => get_eth_byte,
02501       GET_UDPCHK      => get_chksum,
02502       UDPCHK_IN_1     => chksum_1,
02503       UDPCHK_IN_2     => chksum_2,
02504       PKT_DONE        => pktdone,
02505       CHK_DONE        => open,
02506       SYSCLK          => EMAC_CLK,
02507       gmii_rx_clk     => GMII_RX_CLK,
02508       gmii_rx_dv      => GMII_RX_DV,
02509       gmii_rx_er      => GMII_RX_ER,
02510       gmii_rxd        => GMII_RXD,
02511       mii_tx_clk      => MII_TX_CLK,
02512       gmii_tx_en      => GMII_TX_EN,
02513       gmii_tx_er      => GMII_TX_ER,
02514       gmii_txd        => GMII_TXD,
02515       MDC_0           => MDC_0,
02516       mdio            => MDIO,
02517       phy_rst_n       => PHY_RST_N,
02518       RXDATA          => pc_cmd,
02519       RXVLD           => pc_cmdvld,
02520       PACKET_NR       => eth_debug,
02521       DATA_TYPE       => pc_datatype,
02522       LOCK            => mac_lock_i,
02523       CONTR_LED       => open
02524       );
02525 
02526   MAC_LOCK <= mac_lock_i;
02527 
02528 
02529   rd_rdy_sync : edge
02530     port map (
02531       CLK   => EMAC_CLK ,
02532       A     => READ_READY,
02533       PULSE => rd_rdy_i
02534       );
02535 
02536 
02537   READ_OVER_extend : extend_test
02538     generic map (
02539       LEN => 5 )
02540     port map
02541     (
02542       CLK  => REFCLK_P ,
02543       RES  => RESET,
02544       ENDM => open,
02545       A    => READ_OVER,
02546       Y    => rd_ovr 
02547       );
02548 
02549 
02550   rd_ovr_sync : edge
02551     port map (
02552       CLK   => EMAC_CLK ,
02553       A     => rd_ovr ,
02554       PULSE => rd_ovr_i
02555       );
02556 
02557 
02558   start : process(CLK_HZ, RESET)
02559     variable cnt : integer range 0 to 7 := 0;
02560   begin
02561     if RESET = '1' then
02562       cnt    := 0;
02563       arp_ii <= '0';
02564     elsif CLK_HZ'event and CLK_HZ = '1' then
02565       if mac_lock_i = '1' then
02566         if cnt > 5 then
02567           cnt := cnt;
02568         else
02569           cnt := cnt + 1;
02570         end if;
02571         if cnt = 5 then
02572           arp_ii <= '1';
02573         else
02574           arp_ii <= '0';
02575         end if;
02576       end if;
02577     end if;
02578   end process start;
02579 
02580 
02581   en_arp : process(EMAC_CLK, RESET)
02582     variable cnt : integer range 0 to 31 := 0;
02583   begin
02584     if EMAC_CLK'event and EMAC_CLK = '1' then
02585       if RESET = '1' then
02586         cnt      := 0;
02587         arp_i    <= '0';
02588         arp_done <= '0';
02589       else
02590         if arp_ii = '1' then
02591           if cnt > 15 then
02592             cnt := cnt;
02593           else
02594             cnt := cnt + 1;
02595           end if;
02596           if cnt <= 15 and cnt > 5 then
02597             arp_i <= '1';
02598           else
02599             arp_i <= '0';
02600           end if;
02601         else
02602           arp_i <= '0';
02603         end if;
02604         if cnt > 5 then
02605           arp_done <= '1';
02606         end if;
02607       end if;
02608     end if;
02609   end process en_arp;
02610 
02611 
02612   PC_decoder : command_decoder
02613     port map (
02614       CLOCK_IN            => EMAC_CLK,
02615       RESET               => RESET,
02616       ADDRESS_IN          => pc_datatype,
02617       DATA_IN             => pc_cmd,
02618       DATA_VALID_IN       => pc_cmdvld,
02619       MODE                => mode_i,
02620       FPGA_RESET          => res_pc_i,
02621       RIO_RESET           => rio_reset_ii,
02622       BUFFER_DUMP_START   => trig_pc_i,
02623       BUFFER_DUMP_STOP    => stop_pc_i,
02624       S_LINK_START        => sl_trig_pc,
02625       S_LINK_END          => end_slink_i,
02626       S_LINK_PAUSE        => sl_pause,
02627       FILL_BUFFER         => fill_buf_i,
02628       START_OF_RUN        => start_run_i,
02629       POST_MORTEM         => FORCE_PM,
02630       ADJ_TIME_0          => adj_time0i,
02631       ADJ_TIME_1          => adj_time1i,
02632       ADJ_TIME_2          => adj_time2i,
02633       ADJ_TIME_3          => adj_time3i,
02634       ADJ_TIME_4          => adj_time4i,
02635       ADJ_TIME_5          => adj_time5i,
02636       ADJ_TIME_6          => adj_time6i,
02637       ADJ_TIME_7          => adj_time7i,
02638       ADJ_TIME_PULSE      => en_adj_time,
02639       NUMBER_OF_BUNCHES   => numbunch_ii,
02640       ECR_COUNT           => ecr_load_i,
02641       L1A_COUNT           => l1a_load_i,
02642       DSS_ABORT           => dss_ab_i,
02643       DSS_WARNING         => dss_w_i,
02644       BEAM_PERMIT         => b_perm_i,
02645       INJECTION_PERMIT    => i_perm_i,
02646       CTP_PATTERN         => ctp_load_i,
02647       PARAMETERS_I_PULSE  => param_en_vec,
02648       RUN_NUMBER          => run_num_ii,
02649       RUN_NUMBER_PULSE    => run_num_en,
02650       EVENT_TYPE          => ev_type_ii,
02651       EVENT_TYPE_PULSE    => ev_type_en ,
02652       BUSY_EXTERNAL       => busy_ext_rs,
02653       SOURCE_ID           => srcid_ii,
02654       SOURCE_ID_PULSE     => srcid_en,
02655       ALGO_SELECT         => algosel_ii,
02656       ALGO_SELECT_PULSE   => algosel_en,
02657       PACKET_ACK          => ack_ok_simple,
02658       RESET_COUNTERS      => rate_reset,
02659       GET_STATUS          => get_stats,
02660       RESERVED            => open,
02661       INPUT_MASK          => mask_ii ,
02662       INPUT_MASK_PULSE    => mask_en,
02663       PACKET_OK           => ack_ok,
02664       PACKET_ERROR        => ack_err,
02665       PACKET_MISSED       => ack_miss,
02666       FPGA_ID             => fpgaid_ii,
02667       FPGA_ID_PULSE       => fpgaid_en,
02668       READ_TDAQ_STATUS    => send_tdaq_status,
02669       BUSY_EXTERNAL_CLR   => busy_clr,
02670       LVL1_ACCEPT         => open,
02671       LVL1_ACCEPT_PULSE   => open,
02672       FORMAT_VER          => format_ver_ii,
02673       FORMAT_VER_PULSE    => format_ver_en,
02674       L1TT                => tty_ii,
02675       L1TT_PULSE          => tty_en,
02676       ORBIT_COUNTER       => orbit_load_ii,
02677       ORBIT_COUNTER_PULSE => orbit_load_en,
02678       INHIBIT_DELAY       => inhib_del_ii,
02679       INHIBIT_DELAY_PULSE => inhib_del_en,
02680       TRIGGER_DELAY       => trig_del_ii,
02681       TRIGGER_DELAY_PULSE => trig_del_en,
02682       LATENCY             => latency_ii,
02683       LATENCY_PULSE       => latency_en,
02684       FORCE_BCR           => force_bcr_i,
02685       FORCE_ECR           => force_ecr_i,
02686       FORCE_LVL1          => l1a_force_i,
02687       COARSE_DELAY_0      => coarse0_ii,
02688       COARSE_DELAY_1      => coarse1_ii,
02689       COARSE_DELAY_2      => coarse2_ii,
02690       COARSE_DELAY_3      => coarse3_ii,
02691       COARSE_DELAY_4      => coarse4_ii,
02692       COARSE_DELAY_5      => coarse5_ii,
02693       COARSE_DELAY_6      => coarse6_ii,
02694       COARSE_DELAY_7      => coarse7_ii,
02695       COARSE_DELAY_PULSE  => coarse_en,
02696       TTY_SOURCE          => tty_src_ii,
02697       TTY_SOURCE_PULSE    => tty_src_en,
02698       DSSW_SOURCE         => dssw_src_ii,
02699       DSSW_SOURCE_PULSE   => dssw_src_en,
02700       DSSA_SOURCE         => dssa_src_ii,
02701       DSSA_SOURCE_PULSE   => dssa_src_en,
02702       CIBI_SOURCE         => cibi_src_ii,
02703       CIBI_SOURCE_PULSE   => cibi_src_en,
02704       CIBB_SOURCE         => cibb_src_ii,
02705       CIBB_SOURCE_PULSE   => cibb_src_en,
02706       CTP_SOURCE          => ctp_src_ii,
02707       CTP_SOURCE_PULSE    => ctp_src_en,
02708       ACK_DSSW            => ackw_ii,
02709       ACK_DSSA            => acka_ii,
02710       ACK_CIBI            => acki_ii,
02711       ACK_CIBB            => ackb_ii,
02712       CUT_COIN_L          => colwinl_i,
02713       CUT_COIN_H          => colwinh_i,
02714       CUT_WIDE_L          => colwinlw_i,
02715       CUT_WIDE_H          => colwinhw_i,
02716       CUT_OUTA_L          => colwinlo1_i,
02717       CUT_OUTA_H          => colwinho1_i,
02718       CUT_OUTC_L          => colwinlo2_i,
02719       CUT_OUTC_H          => colwinho2_i,
02720       CUT_VLD             => cuts_en_i
02721       );
02722 
02723   ack_vld <= ack_ok or ack_err or ack_ok_simple;  -- stupid implementation, accept all replies
02724 
02725 
02726   busy_ext_latch : process (EMAC_CLK, RESET)
02727   begin  -- process busy_ext_latch
02728     if EMAC_CLK'event and EMAC_CLK = '1' then  -- rising clock edge
02729       if RESET = '1' then               -- synchronous reset (active high)
02730         busy_ext <= '1';
02731       else
02732         if busy_clr = '1' then
02733           busy_ext <= '0';
02734         elsif busy_ext_rs = '1' then
02735           busy_ext <= '1';
02736         end if;
02737       end if;
02738     end if;
02739   end process busy_ext_latch;
02740 
02741 
02742   toggle_data_generation : process (EMAC_CLK, RESET)
02743   begin  -- process
02744     if EMAC_CLK'event and EMAC_CLK = '1' then
02745       if RESET = '1' then
02746         pat_fill <= '0';
02747       else
02748         if fill_buf_i = '1' then
02749           pat_fill <= not pat_fill;
02750         end if;
02751       end if;
02752     end if;
02753   end process;
02754 
02755 --* forward signals to main FSM
02756   STOP_PC   <= stop_pc_i;
02757   TRIG_PC   <= trig_pc_i;
02758   MODE      <= mode_i;
02759 --* set values only with enable
02760   ctp_src_i <= ctp_src_ii when ctp_src_en = '1' else
02761                '0' when RESET = '1' else
02762                ctp_src_i;
02763   tty_src_i <= tty_src_ii when tty_src_en = '1' else
02764                '0' when RESET = '1' else
02765                tty_src_i;
02766   dssw_src_i <= dssw_src_ii when dssw_src_en = '1' else
02767                 '0' when RESET = '1' else
02768                 dssw_src_i;
02769   dssa_src_i <= dssa_src_ii when dssa_src_en = '1' else
02770                 '0' when RESET = '1' else
02771                 dssa_src_i;
02772   cibi_src_i <= cibi_src_ii when cibi_src_en = '1' else
02773                 '0' when RESET = '1' else
02774                 cibi_src_i;
02775   cibb_src_i <= cibb_src_ii when cibb_src_en = '1' else
02776                 '0' when RESET = '1' else
02777                 cibb_src_i;
02778   tty_i <= tty_ii when tty_en = '1' else
02779            (others => '0') when RESET = '1' else
02780            tty_i;
02781   numbunch_i <= conv_std_logic_vector(numbunch_ii, 7) when param_en_vec(0) = '1' else
02782                 "0000001" when RESET = '1' else
02783                 numbunch_i;
02784   coarse0_i <= coarse0_ii when coarse_en(0) = '1' else
02785                (others => '0') when RESET = '1' else
02786                coarse0_i;
02787   coarse1_i <= coarse1_ii when coarse_en(1) = '1' else
02788                (others => '0') when RESET = '1' else
02789                coarse1_i;
02790   coarse2_i <= coarse2_ii when coarse_en(2) = '1' else
02791                (others => '0') when RESET = '1' else
02792                coarse2_i;
02793   coarse3_i <= coarse3_ii when coarse_en(3) = '1' else
02794                (others => '0') when RESET = '1' else
02795                coarse3_i;
02796   coarse4_i <= coarse4_ii when coarse_en(4) = '1' else
02797                (others => '0') when RESET = '1' else
02798                coarse4_i;
02799   coarse5_i <= coarse5_ii when coarse_en(5) = '1' else
02800                (others => '0') when RESET = '1' else
02801                coarse5_i;
02802   coarse6_i <= coarse6_ii when coarse_en(6) = '1' else
02803                (others => '0') when RESET = '1' else
02804                coarse6_i;
02805   coarse7_i <= coarse7_ii when coarse_en(7) = '1' else
02806                (others => '0') when RESET = '1' else
02807                coarse7_i;
02808   colwinl <= colwinl_i when cuts_en_i(0) = '1' else
02809              "00" & c_colwinl when RESET = '1' else
02810              colwinl;
02811   colwinh <= colwinh_i when cuts_en_i(1) = '1' else
02812              "00" & c_colwinh when RESET = '1' else
02813              colwinh;
02814   colwinlw <= colwinlw_i when cuts_en_i(2) = '1' else
02815               "00" & c_colwinlw when RESET = '1' else
02816               colwinlw;
02817   colwinhw <= colwinhw_i when cuts_en_i(3) = '1' else
02818               "00" & c_colwinhw when RESET = '1' else
02819               colwinhw;
02820   colwinlo1 <= colwinlo1_i when cuts_en_i(4) = '1' else
02821                "00" & c_colwinlo1 when RESET = '1' else
02822                colwinlo1;
02823   colwinho1 <= colwinho1_i when cuts_en_i(5) = '1' else
02824                "00" & c_colwinho1 when RESET = '1' else
02825                colwinho1;
02826   colwinlo2 <= colwinlo2_i when cuts_en_i(6) = '1' else
02827                "00" & c_colwinlo2 when RESET = '1' else
02828                colwinlo2;
02829   colwinho2 <= colwinho2_i when cuts_en_i(7) = '1' else
02830                "00" & c_colwinho2 when RESET = '1' else
02831                colwinho2;
02832   mask_i <= mask_ii when mask_en = '1' else
02833             (others => '1') when RESET = '1' else  -- default to 1 !!!
02834             mask_i;
02835   fpgaid_i <= fpgaid_ii when fpgaid_en = '1' else
02836               (others => '0') when RESET = '1' else
02837               fpgaid_i;
02838   format_ver_i <= format_ver_ii when format_ver_en = '1' else
02839                   (others => '0') when RESET = '1' else
02840                   format_ver_i;
02841   orbit_load_i <= orbit_load_ii when orbit_load_en = '1' else
02842                   (others => '0') when RESET = '1' else
02843                   orbit_load_i;
02844   srcid_i <= gnd_vec & srcid_ii when srcid_en = '1' else
02845              (others => '0') when RESET = '1' else
02846              srcid_i;
02847   trig_del_i <= trig_del_ii when trig_del_en = '1' else
02848                 (others => '0') when RESET = '1' else
02849                 trig_del_i;
02850   inhib_del_i <= inhib_del_ii when inhib_del_en = '1' else
02851                  (others => '0') when RESET = '1' else
02852                  inhib_del_i;
02853   latency_i <= latency_ii when latency_en = '1' else
02854                (others => '0') when RESET = '1' else
02855                latency_i;
02856   algosel_i <= algosel_ii when algosel_en = '1' else
02857                (others => '0') when RESET = '1' else
02858                algosel_i;
02859   run_num_i <= run_num_ii when run_num_en = '1' else
02860                (others => '0') when RESET = '1' else
02861                run_num_i;
02862   ev_type_i <= ev_type_ii when ev_type_en = '1' else
02863                (others => '0') when RESET = '1' else
02864                ev_type_i;
02865   adj_time0 <= 0 when RESET = '1' else
02866                adj_time0i when en_adj_time(0) = '1' else
02867                adj_time0;
02868   adj_time0_i  <= 32 when adj_time0 >= 32 else adj_time0;
02869   adj_time02_i <= 0  when adj_time0 <= 32 else adj_time0 - 32;
02870   adj_time1    <= 0  when RESET = '1' else
02871                   adj_time1i when en_adj_time(1) = '1' else
02872                   adj_time1;
02873   adj_time1_i  <= 32 when adj_time1 >= 32 else adj_time1;
02874   adj_time12_i <= 0  when adj_time1 <= 32 else adj_time1 - 32;
02875   adj_time2    <= 0  when RESET = '1' else
02876                   adj_time2i when en_adj_time(2) = '1' else
02877                   adj_time2;
02878   adj_time2_i  <= 32 when adj_time2 >= 32 else adj_time2;
02879   adj_time22_i <= 0  when adj_time2 <= 32 else adj_time2 - 32;
02880   adj_time3    <= 0  when RESET = '1' else
02881                   adj_time3i when en_adj_time(3) = '1' else
02882                   adj_time3;
02883   adj_time3_i  <= 32 when adj_time3 >= 32 else adj_time3;
02884   adj_time32_i <= 0  when adj_time3 <= 32 else adj_time3 - 32;
02885   adj_time4    <= 0  when RESET = '1' else
02886                   adj_time4i when en_adj_time(4) = '1' else
02887                   adj_time4;
02888   adj_time4_i  <= 32 when adj_time4 >= 32 else adj_time4;
02889   adj_time42_i <= 0  when adj_time4 <= 32 else adj_time4 - 32;
02890   adj_time5    <= 0  when RESET = '1' else
02891                   adj_time5i when en_adj_time(5) = '1' else
02892                   adj_time5;
02893   adj_time5_i  <= 32 when adj_time5 >= 32 else adj_time5;
02894   adj_time52_i <= 0  when adj_time5 <= 32 else adj_time5 - 32;
02895   adj_time6    <= 0  when RESET = '1' else
02896                   adj_time6i when en_adj_time(6) = '1' else
02897                   adj_time6;
02898   adj_time6_i  <= 32 when adj_time6 >= 32 else adj_time6;
02899   adj_time62_i <= 0  when adj_time6 <= 32 else adj_time6 - 32;
02900   adj_time7    <= 0  when RESET = '1' else
02901                   adj_time7i when en_adj_time(7) = '1' else
02902                   adj_time7;
02903   adj_time7_i  <= 32 when adj_time7 >= 32 else adj_time7;
02904   adj_time72_i <= 0  when adj_time7 <= 32 else adj_time7 - 32;
02905 
02906 
02907   sl_end_force_extend : extend_test
02908     generic map (
02909       LEN => 4 )
02910     port map
02911     (
02912       CLK  => EMAC_CLK ,
02913       RES  => RESET,
02914       ENDM => open,
02915       A    => end_slink_i,
02916       Y    => end_slink
02917       );
02918 
02919 
02920   l1a_force_extend : extend_test
02921     generic map (
02922       LEN => 4 )
02923     port map
02924     (
02925       CLK  => EMAC_CLK ,
02926       RES  => RESET,
02927       ENDM => open,
02928       A    => l1a_force_i,
02929       Y    => l1a_force_ii
02930       );
02931 
02932 
02933   l1a_force_sync : edge
02934     port map (
02935       CLK   => BCLK,
02936       A     => l1a_force_ii ,
02937       PULSE => l1a_force 
02938       );
02939 
02940 
02941   ackw_extend : extend_test
02942     generic map (
02943       LEN => 4 )
02944     port map
02945     (
02946       CLK  => EMAC_CLK ,
02947       RES  => RESET,
02948       ENDM => open,
02949       A    => ackw_ii ,
02950       Y    => ackw
02951       );
02952 
02953 
02954   acka_extend : extend_test
02955     generic map (
02956       LEN => 4 )
02957     port map
02958     (
02959       CLK  => EMAC_CLK ,
02960       RES  => RESET,
02961       ENDM => open,
02962       A    => acka_ii ,
02963       Y    => acka
02964       );
02965 
02966 
02967   acki_extend : extend_test
02968     generic map (
02969       LEN => 4 )
02970     port map
02971     (
02972       CLK  => EMAC_CLK ,
02973       RES  => RESET,
02974       ENDM => open,
02975       A    => acki_ii ,
02976       Y    => acki
02977       );
02978 
02979 
02980   ackb_extend : extend_test
02981     generic map (
02982       LEN => 4 )
02983     port map
02984     (
02985       CLK  => EMAC_CLK ,
02986       RES  => RESET,
02987       ENDM => open,
02988       A    => ackb_ii ,
02989       Y    => ackb
02990       );
02991 
02992 
02993   start_run_extend : extend_test
02994     generic map (
02995       LEN => 4 )
02996     port map
02997     (
02998       CLK  => EMAC_CLK ,
02999       RES  => RESET,
03000       ENDM => open,
03001       A    => start_run_i,
03002       Y    => start_run_ii
03003       );
03004 
03005 
03006   start_run_sync : edge
03007     port map (
03008       CLK   => BCLK,
03009       A     => start_run_ii ,
03010       PULSE => start_run 
03011       );
03012 
03013 
03014   reset_extend : extend_test
03015     generic map (
03016       LEN => 4 )
03017     port map
03018     (
03019       CLK  => EMAC_CLK ,
03020       RES  => RESET,
03021       ENDM => open,
03022       A    => res_pc_i ,
03023       Y     => RES_PC 
03024       );
03025 
03026 
03027   rate_reset_extend : extend_test
03028     generic map (
03029       LEN => 4 )
03030     port map
03031     (
03032       CLK  => EMAC_CLK ,
03033       RES  => RESET,
03034       ENDM => open,
03035       A    => rate_reset,
03036       Y    => rate_reset_i
03037       );
03038 
03039   rio_res_ext : for S in 7 downto 0 generate
03040 
03041 
03042     rio_reset_extend : extend_test
03043       generic map (
03044         LEN => 4 )
03045       port map
03046       (
03047         CLK   => EMAC_CLK,
03048         RES   => RESET ,
03049         ENDM => open ,
03050         A    => rio_reset_ii(S),
03051         Y    => rio_reset_i(S)
03052         );
03053 
03054   end generate rio_res_ext;
03055 
03056 -------------------------------------------------------------------------------
03057 --                           Error Encoding
03058 -------------------------------------------------------------------------------
03059 
03060   err_code <= x"00" when RESET = '1' else
03061               x"01" when rios_work = '0' else
03062               x"02" when mac_lock_i = '0' else
03063               x"03" when rod_status_i = '0' else
03064               x"04" when MAIN_FSM_ST = "00000100" else
03065               x"05" when sata_ok_i = '0' else
03066               x"06" when fpgaid_i = x"00" else
03067               x"07" when input_en_status_b = '0' else
03068               x"00";
03069 
03070   dcs_errflag <= '0' when RESET = '1' else
03071                  '0' when err_code = x"00" else
03072                  '1';
03073 
03074 -------------------------------------------------------------------------------
03075 --                       DCS status msg collector
03076 -------------------------------------------------------------------------------
03077 
03078   fill_enstatus_vec : for K in 7 downto 0 generate
03079     input_en_status_byte7(K) <= input_en_status(7);
03080     input_en_status_byte6(K) <= input_en_status(6);
03081     input_en_status_byte5(K) <= input_en_status(5);
03082     input_en_status_byte4(K) <= input_en_status(4);
03083     input_en_status_byte3(K) <= input_en_status(3);
03084     input_en_status_byte2(K) <= input_en_status(2);
03085     input_en_status_byte1(K) <= input_en_status(1);
03086     input_en_status_byte0(K) <= input_en_status(0);
03087   end generate fill_enstatus_vec;
03088 
03089 
03090   dcs_bufr : BUFR
03091     port map
03092     (
03093       O   => ctor_clk,
03094       I   => EMAC_CLK,
03095       CLR => '0' ,
03096       CE  => '1' 
03097       );
03098 
03099   make_status_bytes : for Q in 7 downto 0 generate
03100     dss_a_iv(Q)  <= dss_a_i;
03101     dss_wa_iv(Q) <= dss_wa_i;
03102     inj_p_iv(Q)  <= inj_p_i;
03103     bem_p_iv(Q)  <= bem_p_i;
03104     lf_fullv(Q)  <= lf_full;
03105     lf_emptyv(Q) <= lf_empty;
03106     l1a_dispv(Q) <= L1A_DISP;
03107   end generate make_status_bytes;
03108 
03109 
03110   dcs_msg_ctor : status_collector
03111     port map (
03112       DEBUG                         => open,
03113       EMAC_CLK                      => ctor_clk,
03114       RATES_CLK                     => BCLK,
03115       STATUS_CLK                    => REFCLK_P,
03116       RIO_CLK                       => BCLK4X_P,
03117       RESET                         => RESET,
03118       START                         => assemb_stat,
03119       FETCH_BYTE                    => fetch_stat_eth,
03120       FETCH_CHKSUM                  => get_stat_chksum,
03121       ERROR_FLAG                    => dcs_errflag,
03122       EXT_CLK_DET                   => XT_CLK_DET,
03123       RIO_DAQ                       => rios_work,
03124       RIO_SATA                      => sata_ok_i,
03125       MODE                          => mode_i ,
03126       DCM_STATUS                    => mac_lock_i ,
03127       ROD_STATUS                    => rod_status_i,
03128       FPGA_ID                       => fpgaid_i,
03129       MAIN_FSM                      => MAIN_FSM_ST,
03130       DSS_CIBU_STATUS(31 downto 24) => dss_wa_iv,
03131       DSS_CIBU_STATUS(23 downto 16) => dss_a_iv,
03132       DSS_CIBU_STATUS(15 downto 8)  => inj_p_iv,
03133       DSS_CIBU_STATUS(7 downto 0)   => bem_p_iv,
03134       ERROR_CODE(31 downto 8)       => x"000000",
03135       ERROR_CODE(7 downto 0)        => err_code,
03136       INPUT_STATUS(63 downto 56)    => input_en_status_byte0,
03137       INPUT_STATUS(55 downto 48)    => input_en_status_byte1,
03138       INPUT_STATUS(47 downto 40)    => input_en_status_byte2,
03139       INPUT_STATUS(39 downto 32)    => input_en_status_byte3,
03140       INPUT_STATUS(31 downto 24)    => input_en_status_byte4,
03141       INPUT_STATUS(23 downto 16)    => input_en_status_byte5,
03142       INPUT_STATUS(15 downto 8)     => input_en_status_byte6,
03143       INPUT_STATUS(7 downto 0)      => input_en_status_byte7,
03144       TDAQ_PARAMS(159 downto 128)   => run_num_i,
03145       TDAQ_PARAMS(127 downto 120)   => busy_vec,
03146       TDAQ_PARAMS(119 downto 112)   => busy_ext_vec,
03147       TDAQ_PARAMS(111 downto 80)    => srcid_i,
03148       TDAQ_PARAMS(79 downto 48)     => orbid_i,
03149       TDAQ_PARAMS(47 downto 16)     => ev_type_i,
03150       TDAQ_PARAMS(15 downto 8)      => lf_fullv,
03151       TDAQ_PARAMS(7 downto 0)       => lf_emptyv,
03152       HITRATE_CH1                   => cnt_ch1,
03153       HITRATE_CH2                   => cnt_ch2,
03154       HITRATE_CH3                   => cnt_ch3,
03155       HITRATE_CH4                   => cnt_ch4,
03156       HITRATE_CH5                   => cnt_ch5,
03157       HITRATE_CH6                   => cnt_ch6,
03158       HITRATE_CH7                   => cnt_ch7,
03159       HITRATE_CH8                   => cnt_ch8,
03160       HITRATE_A_CH1(31 downto 24)   => fine_del_stdl_0,
03161       HITRATE_A_CH1(23 downto 16)   => fine_del_stdl_1,
03162       HITRATE_A_CH1(15 downto 8)    => fine_del_stdl_2,
03163       HITRATE_A_CH1(7 downto 0)     => fine_del_stdl_3,
03164       HITRATE_A_CH2(31 downto 24)   => fine_del_stdl_4,
03165       HITRATE_A_CH2(23 downto 16)   => fine_del_stdl_5,
03166       HITRATE_A_CH2(15 downto 8)    => fine_del_stdl_6,
03167       HITRATE_A_CH2(7 downto 0)     => fine_del_stdl_7,
03168       HITRATE_A_CH3(31 downto 24)   => coarse0_i,
03169       HITRATE_A_CH3(23 downto 16)   => coarse1_i,
03170       HITRATE_A_CH3(15 downto 8)    => coarse2_i,
03171       HITRATE_A_CH3(7 downto 0)     => coarse3_i,
03172       HITRATE_A_CH4(31 downto 24)   => coarse4_i,
03173       HITRATE_A_CH4(23 downto 16)   => coarse5_i,
03174       HITRATE_A_CH4(15 downto 8)    => coarse6_i,
03175       HITRATE_A_CH4(7 downto 0)     => coarse7_i,
03176       HITRATE_A_CH5(31 downto 24)   => inhib_del_i,
03177       HITRATE_A_CH5(23 downto 16)   => trig_del_i,
03178       HITRATE_A_CH5(15 downto 8)    => latency_i,
03179       HITRATE_A_CH5(7 downto 0)     => ctp_sel,
03180       HITRATE_A_CH6(31 downto 24)   => tty_sel,
03181       HITRATE_A_CH6(23 downto 16)   => dssa_sel,
03182       HITRATE_A_CH6(15 downto 8)    => dssw_sel,
03183       HITRATE_A_CH6(7 downto 0)     => cibi_sel,
03184       HITRATE_A_CH7(31 downto 24)   => cibb_sel,
03185       HITRATE_A_CH7(23 downto 17)   => "0000000",
03186       HITRATE_A_CH7(16)             => ctp_out (9),
03187       HITRATE_A_CH7(15 downto 8)    => ctp_out(8 downto 1),
03188       HITRATE_A_CH7(7 downto 1)     => "0000000",
03189       HITRATE_A_CH7(0)              => ctp_load (9),
03190       HITRATE_A_CH8(31 downto 24)   => ctp_load(8 downto 1),
03191       HITRATE_A_CH8(23 downto 16)   => rio_rx_locks,
03192       HITRATE_A_CH8(15 downto 8)    => rio_tx_locks,
03193       HITRATE_A_CH8(7 downto 0)     => rio_rx_rdys,
03194       HITRATE_B_CH1(31 downto 24)   => rio_tx_rdys,
03195       HITRATE_B_CH1(23)             => '0' ,
03196       HITRATE_B_CH1(22 downto 16)   => numbunch_i,
03197       HITRATE_B_CH1(15 downto 8)    => l1a_dispv,
03198       HITRATE_B_CH1(7 downto 0)     => x"00",
03199       ALGO_STATE                    => x"00000000",
03200       HITRATE_C_CH1                 => cnt_coin,
03201       HITRATE_C_CH2                 => cnt_backa,
03202       HITRATE_C_CH3                 => cnt_backc,
03203       HITRATE_C_CH4(31 downto 24)   => colwinl,
03204       HITRATE_C_CH4(23 downto 16)   => colwinh,
03205       HITRATE_C_CH4(15 downto 8)    => colwinlw,
03206       HITRATE_C_CH4(7 downto 0)     => colwinhw,
03207       HITRATE_C_CH5(31 downto 24)   => colwinlo1,
03208       HITRATE_C_CH5(23 downto 16)   => colwinho1,
03209       HITRATE_C_CH5(15 downto 8)    => colwinlo2,
03210       HITRATE_C_CH5(7 downto 0)     => colwinho2,
03211       HITRATE_C_CH6                 => trig_rate_AttC,
03212       HITRATE_C_CH7                 => trig_rate_AttA,
03213       HITRATE_C_CH8                 => trig_rate_Mult3pC,
03214       HITRATE_D_CH1                 => trig_rate_Mult2C,
03215       HITRATE_D_CH2                 => trig_rate_Mult1C,
03216       HITRATE_D_CH3                 => trig_rate_Mult3pA,
03217       HITRATE_D_CH4                 => trig_rate_Mult2A,
03218       HITRATE_D_CH5                 => trig_rate_Mult1A,
03219       HITRATE_D_CH6                 => trig_rate_Wide,
03220       HITRATE_D_CH7                 => trig_rate_CtoA,
03221       HITRATE_D_CH8                 => trig_rate_AtoC,
03222       ASM_DONE                      => stat_asm_done_i,
03223       TRANS_DONE                    => stat_msg_rd_done,
03224       CHKSUM_OUT                    => stat_chksum,
03225       DATA_OUT                      => stat_byte
03226       );
03227 
03228 -------------------------------------------------------------------------------
03229 --                              SLINK ROD
03230 -------------------------------------------------------------------------------
03231 
03232   --* reset Level-1 Buffer
03233   lvl1_buf_res   <= RESET or start_run;
03234   --* proc data without status bits
03235   proc_data_lvl1 <= proc_data_i(190 downto 180) & proc_data_i(178 downto 168) & proc_data_i(166 downto 156) &
03236                     proc_data_i(154 downto 144) & proc_data_i(142 downto 132) & proc_data_i(130 downto 120) &
03237                     proc_data_i(118 downto 108) & proc_data_i(106 downto 96) & proc_data_i(94 downto 84) &
03238                     proc_data_i(82 downto 72) & proc_data_i(70 downto 60) & proc_data_i(58 downto 48) &
03239                     proc_data_i(46 downto 36) & proc_data_i(34 downto 24) & proc_data_i(22 downto 12) &
03240                     proc_data_i(10 downto 0);
03241 
03242 
03243   TDAQ_LVL1_buf : lvl1_buf
03244     port map
03245     (
03246       RESET    => lvl1_buf_res ,
03247       CLKWR    => BCLK,
03248       CLKRD    => BCLK,
03249       DATA_IN  => proc_data_lvl1,
03250       DATA_OUT => data_rod,
03251       RD_BID   => l1a_bid,
03252       WR_BID   => bcid_i,
03253       VLD      => data_rod_vld ,
03254       NUM      => numbunch_i ,
03255       FINISH   => end_slink,
03256       all_READ => l1a_done,
03257       EN_B     => lvl1_buf_rden,
03258       PAUSE    => buf_pause ,
03259       WE       => '1' 
03260       );
03261 
03262 
03263   L1A_delay : bcm_signal_delay
03264     port map(
03265       CLK           => BCLK,
03266       SCLR          => RESET,
03267       delay_setting => trig_del_i,
03268       data_input    => L1A,
03269       data_output   => l1a_del
03270       );
03271 
03272 
03273   latency_bcr_delay : bcm_signal_delay
03274     port map(
03275       CLK           => BCLK,
03276       SCLR          => RESET,
03277       delay_setting => latency_i,
03278       data_input    => orbit_del,
03279       data_output   => bcr_latency
03280       );
03281 
03282 
03283   l1a_sync : edge
03284     port map (
03285       CLK   => BCLK,
03286       A     => l1a_del ,
03287       PULSE => l1a_i
03288       );
03289 
03290 
03291   bunch_counter : BID_cnt
03292     port map (
03293       BC    => BCLK,
03294       BCR   => bcr_latency,
03295       RESET => RESET,
03296       BID   => l1a_bid_in
03297       );
03298 
03299 
03300   Level_1_trigger_fifo : l1a_fifo
03301     port map (
03302       clk                 => BCLK,
03303       din(43 downto 12)  => evid_i ,
03304       din(11 downto 0)   => l1a_bid_in,
03305       rd_en               => lf_rden,
03306       srst               => lvl1_buf_res,
03307       wr_en              => lf_wren,
03308       dout(43 downto 12) => l1a_evid,
03309       dout(11 downto 0)  => l1a_bid,
03310       empty              => open,
03311       full               => open
03312       );
03313 
03314 
03315   empty_flag : process (BCLK, lvl1_buf_res)
03316   begin  -- process empty_flag
03317     if lvl1_buf_res = '1' then            -- asynchronous reset (active high)
03318       l1a_fifo_fill <= (others => '0');
03319       lf_empty      <= '1';
03320       lf_full       <= '0';
03321     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03322       if (lf_wren and lf_rden) = '1' then
03323         l1a_fifo_fill <= l1a_fifo_fill;
03324       elsif (lf_wren = '1' and l1a_fifo_fill /= 31) then
03325         l1a_fifo_fill <= l1a_fifo_fill + 1;
03326       elsif (lf_rden = '1' and l1a_fifo_fill /= 0) then
03327         l1a_fifo_fill <= l1a_fifo_fill - 1;
03328       end if;
03329       if (l1a_fifo_fill = 0 and lf_full = '0') then
03330         lf_empty <= '1';
03331       else
03332         lf_empty <= '0';
03333       end if;
03334       if lf_empty = '1' then
03335         lf_full <= '0';
03336       elsif l1a_fifo_fill >= 29 then
03337         lf_full <= '1';
03338       else
03339         lf_full <= '0';
03340       end if;
03341     end if;
03342   end process empty_flag;
03343 
03344   -- start S-Link read out
03345   fetch_int     <= '0' when RESET = '1' else (l1a_i or l1a_force or sl_trig_pc_i);
03346   lf_wren_ii    <= fetch_int  when lf_full = '0' else '0';
03347   lf_wren_i     <= lf_wren_ii when rising_edge(BCLK);
03348   lf_wren       <= lf_wren_i  when rising_edge(BCLK);
03349   lf_rden2      <= lf_rden    when rising_edge(BCLK);
03350   lvl1_buf_rden <= lf_rden2   when rising_edge(BCLK);
03351   buf_pause     <= busy_i or sl_pause_i;
03352 
03353 
03354   l1adone_latch : process (BCLK, RESET)
03355   begin  -- process donelatch
03356     if RESET = '1' then                   -- asynchronous reset (active high)
03357       next_l1a <= '1';
03358     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03359       if lf_rden = '1' then
03360         next_l1a <= '0';
03361       elsif get_next_l1a = '1' then
03362         next_l1a <= '1';
03363       end if;
03364     end if;
03365   end process l1adone_latch;
03366 
03367 
03368   l1adone_latch1 : process (BCLK, RESET)
03369   begin  -- process donelatch
03370     if RESET = '1' then                   -- asynchronous reset (active high)
03371       next_l1a1 <= '0';
03372     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03373       if l1a_done = '1' then
03374         next_l1a1 <= '1';
03375       elsif busy_i = '0' then
03376         next_l1a1 <= '0';
03377       end if;
03378     end if;
03379   end process l1adone_latch1;
03380 
03381 
03382   nllatches : process(BCLK)
03383   begin
03384     if BCLK'event and BCLK = '1' then
03385       nllatch1 <= next_l1a1;
03386       nllatch2 <= nllatch1;
03387     end if;
03388   end process nllatches;
03389 
03390   get_next_l1a <= nllatch2 and (not nllatch1);
03391 
03392 
03393   l1a_fifo_buffer_interface : process (BCLK, RESET)
03394     variable cs, ds : std_logic_vector(1 downto 0) := "00";
03395     variable push   : integer                      := 0;
03396   begin  -- process l1a_fifo_buffer_interface
03397     if RESET = '1' then                   -- asynchronous reset (active high)
03398       cs      := "00";
03399       lf_rden <= '0';
03400       push    := 0;
03401     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03402       cs      := ds;
03403       lf_rden <= '0';
03404       case cs is
03405         when "00" =>
03406           if lf_empty = '0' and busy_i = '0' then
03407             lf_rden <= '1';
03408             ds      := "01";
03409             push    := 0;
03410           end if;
03411         when "01" =>
03412           if (next_l1a = '1') and (push = 5) then
03413             ds := "00";
03414           end if;
03415           if push = 5 then
03416             push := push;
03417           else
03418             push := push+1;
03419           end if;
03420         when others => null;
03421       end case;
03422     end if;
03423   end process l1a_fifo_buffer_interface;
03424 
03425 
03426   rod_command_extend1 : extend_test
03427     generic map (
03428       LEN => 4 )
03429     port map
03430     (
03431       CLK  => EMAC_CLK ,
03432       RES  => RESET,
03433       ENDM => open,
03434       A    => sl_trig_pc,
03435       Y    => sl_trig_pc_ii
03436       );
03437 
03438 
03439   rod_command_sync1 : edge
03440     port map (
03441       CLK   => BCLK,
03442       A     => sl_trig_pc_ii,
03443       PULSE => sl_trig_pc_i
03444       );
03445 
03446 
03447   rod_command_extend2 : extend_test
03448     generic map (
03449       LEN => 4 )
03450     port map
03451     (
03452       CLK  => EMAC_CLK ,
03453       RES  => RESET,
03454       ENDM => open,
03455       A    => sl_pause ,
03456       Y    => sl_pause_ii
03457       );
03458 
03459 
03460   rod_command_sync2 : edge
03461     port map (
03462       CLK   => BCLK,
03463       A     => sl_pause_ii,
03464       PULSE => sl_pause_i
03465       );
03466 
03467   -- ROD Busy
03468   fill_busy_vec : for J in 7 downto 0 generate
03469     busy_vec(J) <= busy_ext or lf_full;
03470   end generate fill_busy_vec;
03471   fill_busy_ext_vec : for J in 7 downto 0 generate
03472     busy_ext_vec(J) <= busy_ext;
03473   end generate fill_busy_ext_vec;
03474 
03475   busy_extend : extend_test
03476     generic map (
03477       LEN => 8 )
03478     port map
03479     (
03480       CLK  => BCLK,
03481       RES  => RESET,
03482       ENDM => open,
03483       A    => busy_vec (0),
03484       Y    => BUSY
03485       );
03486 
03487   ctp_tty_i <= (others => '0') when RESET = '1' else
03488                x"000000" & tty_i when tty_src_i = '1' else
03489                x"000000" & TRIGGER_TYPE;
03490 
03491   sl_ldown_i <= '1' when RESET = '1' else SL_LDOWN;
03492   fill_ldown_vec : for J in 7 downto 0 generate
03493     sl_ldown_vec(J) <= not sl_ldown_i;
03494   end generate fill_ldown_vec;
03495   sl_lff_i <= '1' when RESET = '1' else SL_LFF;
03496   fill_lff_vec : for J in 7 downto 0 generate
03497     sl_lff_vec(J) <= not sl_lff_i;
03498   end generate fill_lff_vec;
03499 
03500 
03501   rod : bcm_rod
03502     port map (
03503       CLK                     => BCLK,
03504       CLK_2X                  => BCLK2X_P,
03505       SCLR                    => RESET,
03506       rod_format_version      => format_ver_i,
03507       rod_source_ID           => srcid_i ,
03508       rod_run_number          => run_num_i,
03509       rod_CTP_trigger_type    => ctp_tty_i,
03510       rod_detector_event_type => ev_type_i,
03511       data_input              => data_rod,
03512       data_lvl1id             => l1a_evid,
03513       data_input_valid        => data_rod_vld,
03514       data_input_busy         => busy_i,
03515       data_input_endoffrag    => l1a_done,
03516       hola_LFF                => sl_lff_i,
03517       hola_LDOWN              => sl_ldown_i,
03518       hola_LRL                => SL_LRL,
03519       hola_CLK                => SL_UCLK,
03520       hola_UD                 => SL_UD_i,
03521       hola_URESET             => SL_URESET,
03522       hola_UTEST              => SL_UTEST ,
03523       hola_UCTRL              => SL_UCTRL,
03524       hola_UWEN               => SL_UWEN_i,
03525       hola_UDW                => SL_UDW
03526       );
03527 
03528   SL_UD   <= SL_UD_i;
03529   SL_UWEN <= SL_UWEN_i;
03530 
03531   rod_status_i <= '0' when RESET = '1' else
03532                   sl_lff_i and sl_ldown_i;
03533   bcid_long       <= gnd_vec_long(31 downto 12) & bcid_i;
03534   fine_del_stdl_0 <= conv_std_logic_vector(adj_time0, 8);
03535   fine_del_stdl_1 <= conv_std_logic_vector(adj_time1, 8);
03536   fine_del_stdl_2 <= conv_std_logic_vector(adj_time2, 8);
03537   fine_del_stdl_3 <= conv_std_logic_vector(adj_time3, 8);
03538   fine_del_stdl_4 <= conv_std_logic_vector(adj_time4, 8);
03539   fine_del_stdl_5 <= conv_std_logic_vector(adj_time5, 8);
03540   fine_del_stdl_6 <= conv_std_logic_vector(adj_time6, 8);
03541   fine_del_stdl_7 <= conv_std_logic_vector(adj_time7, 8);
03542   ctp_sel         <= x"ff" when ctp_src_i = '1' else x"00";
03543   tty_sel         <= x"ff" when tty_src_i = '1' else x"00";
03544   dssw_sel        <= x"ff" when dssw_src_i = '1' else x"00";
03545   dssa_sel        <= x"ff" when dssa_src_i = '1' else x"00";
03546   cibi_sel        <= x"ff" when cibi_src_i = '1' else x"00";
03547   cibb_sel        <= x"ff" when cibb_src_i = '1' else x"00";
03548 
03549   tdaq_msg_ctor : tdaq_collector
03550     port map (
03551       EMAC_CLK                   => EMAC_CLK,
03552       ROD_CLK                     => BCLK,
03553       STATUS_CLK                  => REFCLK_P,
03554       RIO_CLK                    => BCLK4X_P,
03555       RESET                       => RESET,
03556       START                       => assemb_tdaq,
03557       FETCH_BYTE                  => fetch_tdaq_eth,
03558       FETCH_CHKSUM               => get_tdaq_chksum,
03559       FPGA_ID                     => fpgaid_i,
03560       ERROR_CODE                  => err_code,
03561       INPUT_STATUS(63 downto 56) => input_en_status_byte7,
03562       INPUT_STATUS(55 downto 48) => input_en_status_byte6,
03563       INPUT_STATUS(47 downto 40) => input_en_status_byte5,
03564       INPUT_STATUS(39 downto 32) => input_en_status_byte4,
03565       INPUT_STATUS(31 downto 24) => input_en_status_byte3,
03566       INPUT_STATUS(23 downto 16) => input_en_status_byte2,
03567       INPUT_STATUS(15 downto 8)  => input_en_status_byte1,
03568       INPUT_STATUS(7 downto 0)   => input_en_status_byte0,
03569       DATA_SRC                   => data_src,
03570       COARSE_DELAY1              => coarse0_i,
03571       COARSE_DELAY2              => coarse1_i,
03572       COARSE_DELAY3              => coarse2_i,
03573       COARSE_DELAY4              => coarse3_i,
03574       COARSE_DELAY5              => coarse4_i,
03575       COARSE_DELAY6              => coarse5_i,
03576       COARSE_DELAY7              => coarse6_i,
03577       COARSE_DELAY8              => coarse7_i,
03578       FINE_DELAY1                => fine_del_stdl_0,
03579       FINE_DELAY2                => fine_del_stdl_1,
03580       FINE_DELAY3                => fine_del_stdl_2,
03581       FINE_DELAY4                => fine_del_stdl_3,
03582       FINE_DELAY5                => fine_del_stdl_4,
03583       FINE_DELAY6                 => fine_del_stdl_5,
03584       FINE_DELAY7                => fine_del_stdl_6,
03585       FINE_DELAY8                => fine_del_stdl_7,
03586       BUSY                        => busy_vec,
03587       BUSY_EXT                   => busy_ext_vec,
03588       SLINK_FULL                  => sl_lff_vec,
03589       SLINK_DOWN                 => sl_ldown_vec,
03590       L1A                        => L1A_DISP,
03591       L1A_FIFO_FULL              => lf_full,
03592       L1A_FIFO_EMPTY             => lf_empty,
03593       TRIGGER_DELAY              => trig_del_i,
03594       EXT_EVENT_ID               => evid_i,
03595       ORBIT_ID                   => orbid_i,
03596       INHIBIT_DELAY              => inhib_del_i,
03597       BCID                        => bcid_long,
03598       DETECTOR_EVENT_TYPE        => ev_type_i,
03599       SOURCE_ID                  => srcid_i,
03600       FORMAT_V                    => format_ver_i,
03601       RUN_NUMBER                 => run_num_i,
03602       TRIGGER_TYPE               => ctp_tty_i(7 downto 0),
03603       CTP_OUT                    => ctp_out,
03604       CTP_FORCE                  => ctp_load_i,
03605       CTP_SEL                    => ctp_sel,
03606       TTY_SEL                    => tty_sel,
03607       DSSA_SEL                    => dssa_sel,
03608       DSSW_SEL                    => dssw_sel,
03609       CIBI_SEL                    => cibi_sel,
03610       CIBB_SEL                    => cibb_sel,
03611       DSS_WARNING                 => dss_wa_i,
03612       DSS_ABORT                  => dss_a_i,
03613       INJ_PERM                    => inj_p_i,
03614       BEAM_PERM                  => bem_p_i,
03615       NUM_BUNCH(7)               => '0' ,
03616       NUM_BUNCH(6 downto 0)      => numbunch_i ,
03617       RX_LOCK                    => rio_rx_locks,
03618       TX_LOCK                    => rio_tx_locks,
03619       RX_READY                   => rio_rx_rdys,
03620       TX_READY                    => rio_tx_rdys,
03621       LATENCY                    => latency_i,
03622       CUT_COIN_L                 => colwinl,
03623       CUT_COIN_H                 => colwinh,
03624       CUT_WIDE_L                 => colwinlw,
03625       CUT_WIDE_H                 => colwinhw,
03626       CUT_OUTA_L                 => colwinlo1 ,
03627       CUT_OUTA_H                 => colwinho1,
03628       CUT_OUTC_L                 => colwinlo2,
03629       CUT_OUTC_H                 => colwinho2,
03630       TRATE_AttC                 => trig_rate_AttC,
03631       TRATE_AttA                  => trig_rate_AttA,
03632       TRATE_Mult3pC              => trig_rate_Mult3pC,
03633       TRATE_Mult2C               => trig_rate_Mult2C,
03634       TRATE_Mult1C               => trig_rate_Mult1C,
03635       TRATE_Mult3pA              => trig_rate_Mult3pA,
03636       TRATE_Mult2A               => trig_rate_Mult2A,
03637       TRATE_Mult1A               => trig_rate_Mult1A,
03638       TRATE_Wide                  => trig_rate_Wide,
03639       TRATE_CtoA                 => trig_rate_CtoA,
03640       TRATE_AtoC                  => trig_rate_AtoC,
03641       TRANS_DONE                  => tdaq_msg_rd_done,
03642       ASM_DONE                   => tdaq_asm_done_i,
03643       CHKSUM_OUT                 => tdaq_chksum,
03644       DATA_OUT                   => tdaq_byte
03645       );
03646 
03647 -------------------------------------------------------------------------------
03648 --                              TTC Interface
03649 -------------------------------------------------------------------------------
03650 
03651 
03652   command_extend11 : extend_test
03653     generic map (
03654       LEN => 4 )
03655     port map
03656     (
03657       CLK  => EMAC_CLK ,
03658       RES  => RESET,
03659       ENDM => open,
03660       A    => param_en_vec(2),
03661       Y    => set_l1a_load_i
03662       );
03663 
03664 
03665   l1a_cmd_extend : for P in 23 downto 0 generate
03666     command_extend_ecr : extend_test
03667       generic map (
03668         LEN => 4 )
03669       port map
03670       (
03671         CLK   => EMAC_CLK,
03672         RES   => RESET ,
03673         ENDM => open ,
03674         A     => l1a_load_i (P),
03675         Y    => l1a_load_ii(P)
03676         );
03677   end generate l1a_cmd_extend;
03678 
03679 
03680   command_extend21 : extend_test
03681     generic map (
03682       LEN => 4 )
03683     port map
03684     (
03685       CLK  => EMAC_CLK ,
03686       RES  => RESET,
03687       ENDM => open,
03688       A    => orbit_load_en,
03689       Y    => set_orbit
03690       );
03691 
03692 
03693   orb_cmd_extend : for R in 31 downto 0 generate
03694     command_extend_orb : extend_test
03695       generic map (
03696         LEN => 4 )
03697       port map
03698       (
03699         CLK   => EMAC_CLK,
03700         RES   => RESET ,
03701         ENDM => open ,
03702         A     => orbit_load_i (R),
03703         Y    => set_orbit_val(R)
03704         );
03705   end generate orb_cmd_extend;
03706 
03707 
03708   command_extend12 : extend_test
03709     generic map (
03710       LEN => 4 )
03711     port map
03712     (
03713       CLK  => EMAC_CLK ,
03714       RES  => RESET,
03715       ENDM => open,
03716       A    => param_en_vec(1),
03717       Y    => set_ecr_load_i
03718       );
03719 
03720 
03721   ecr_cmd_extend : for Q in 7 downto 0 generate
03722     command_extend_ecr : extend_test
03723       generic map (
03724         LEN => 4 )
03725       port map
03726       (
03727         CLK   => EMAC_CLK,
03728         RES   => RESET ,
03729         ENDM  => open ,
03730         A     => ecr_load_i (Q),
03731         Y     => ecr_load_ii(Q)
03732         );
03733   end generate ecr_cmd_extend;
03734 
03735 
03736   command_extend_bcr_force : extend_test
03737     generic map (
03738       LEN => 4 )
03739     port map
03740     (
03741       CLK  => EMAC_CLK ,
03742       RES  => RESET,
03743       ENDM => open,
03744       A    => force_bcr_i,
03745       Y    => bcr_force
03746       );
03747 
03748 
03749   command_extend_ecr_force : extend_test
03750     generic map (
03751       LEN => 4 )
03752     port map
03753     (
03754       CLK  => EMAC_CLK ,
03755       RES  => RESET,
03756       ENDM => open,
03757       A    => force_ecr_i,
03758       Y    => ecr_force
03759       );
03760 
03761 
03762   Orbit_delay : bcm_signal_delay
03763     port map(
03764       CLK           => BCLK,
03765       SCLR          => RESET,
03766       delay_setting => inhib_del_i,
03767       data_input    => ORBIT,
03768       data_output   => orbit_del
03769       );
03770 
03771   bcr_i   <= BCR or bcr_force;
03772   ecr_i   <= ECR or ecr_force;
03773   l1a_inc <= l1a_i or l1a_force;
03774 
03775 
03776   ltp_rcd : ltp_comm
03777     port map (
03778       BCLK          => BCLK,
03779       RESET         => RESET,
03780       ORBIT         => orbit_del,
03781       START_RUN     => start_run,
03782       BCR           => bcr_i,
03783       L1A           => l1a_inc,
03784       ECR           => ecr_i,
03785       ECR_LOAD_EN   => set_ecr_load_i,
03786       ECR_LOAD      => ecr_load_ii,
03787       L1A_LOAD_EN   => set_l1a_load_i,
03788       L1A_LOAD      => l1a_load_ii,
03789       ORBIT_LOAD_EN => set_orbit,
03790       ORBIT_LOAD    => set_orbit_val,
03791       EXT_EVID      => evid_i,
03792       BCID          => bcid_i,
03793       ORBITID       => orbid_i
03794       );
03795 
03796 -------------------------------------------------------------------------------
03797 --                                DSS
03798 -------------------------------------------------------------------------------
03799 
03800 
03801   command_extend6 : extend_test
03802     generic map (
03803       LEN => 4 )
03804     port map
03805     (
03806       CLK  => EMAC_CLK ,
03807       RES  => RESET,
03808       ENDM => open,
03809       A    => dss_ab_i ,
03810       Y    => dss_ab_ii
03811       );
03812 
03813 
03814   command_extend7 : extend_test
03815     generic map (
03816       LEN => 4 )
03817     port map
03818     (
03819       CLK  => EMAC_CLK ,
03820       RES  => RESET,
03821       ENDM => open,
03822       A    => dss_w_i ,
03823       Y    => dss_w_ii 
03824       );
03825 
03826 
03827   command_extend8 : extend_test
03828     generic map (
03829       LEN => 4 )
03830     port map
03831     (
03832       CLK  => EMAC_CLK ,
03833       RES  => RESET,
03834       ENDM => open,
03835       A    => param_en_vec(3),
03836       Y    => set_dss_ab_i
03837       );
03838 
03839 
03840   command_extend9 : extend_test
03841     generic map (
03842       LEN => 4 )
03843     port map
03844     (
03845       CLK  => EMAC_CLK ,
03846       RES  => RESET,
03847       ENDM => open,
03848       A    => param_en_vec(4),
03849       Y    => set_dss_w_i
03850       );
03851 
03852   dss_abort <= dss_ab_ii when dssa_src_i = '1' else
03853                '0' when (RESET or rate_block) = '1' else
03854                dss_alarm;
03855   set_dss_abort <= set_dss_ab_i when dssa_src_i = '1' else
03856                    '0' when (RESET or rate_block) = '1' else
03857                    '1';
03858   dss_warning <= dss_w_ii when dssw_src_i = '1' else
03859                  '0' when (RESET or rate_block) = '1' else
03860                  '0';                   -- fill with logic
03861   set_dss_warning <= set_dss_w_i when dssw_src_i = '1' else
03862                      '0' when (RESET or rate_block) = '1' else
03863                      '1';
03864   
03865   dss_alarm_latch : process (BCLK, RESET)
03866   begin  -- process beam_permit_latch
03867     if RESET = '1' then                   -- asynchronous reset (active high)
03868       dss_alarm <= '0';
03869     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03870       if acka = '1' then
03871         dss_alarm <= '0';
03872       elsif dump_beam = '1' then
03873         dss_alarm <= '1';
03874       end if;
03875     end if;
03876   end process dss_alarm_latch;
03877 
03878   DSS : dss_comm
03879     port map (
03880       CLK           => BCLK,
03881       RESET         => RESET,
03882       SET(1)        => dss_abort,
03883       SET(0)        => dss_warning,
03884       SET_EN(1)     => set_dss_abort,
03885       SET_EN(0)     => set_dss_warning,
03886       DSS_ABORT_1   => dss_ab1_i,
03887       DSS_ABORT_2   => dss_ab2_i,
03888       DSS_WARNING_1 => dss_wa1_i,
03889       DSS_WARNING_2 => dss_wa2_i 
03890       );
03891 
03892   DSS_ABORT_1   <= dss_ab1_i;                -- and sata_dssa;
03893   DSS_ABORT_2   <= dss_ab2_i;                -- and sata_dssa;
03894   DSS_WARNING_1 <= dss_wa1_i;                -- and sata_dssw;
03895   DSS_WARNING_2 <= dss_wa2_i;                -- and sata_dssw;
03896   dss_a_i       <= dss_ab1_i and dss_ab2_i;  -- and sata_dssa;
03897   dss_wa_i      <= dss_wa1_i and dss_wa2_i;  -- and sata_dssw;
03898 
03899 -------------------------------------------------------------------------------
03900 --                                CTP
03901 -------------------------------------------------------------------------------
03902 
03903 
03904   ctplogic : ctp_logic
03905     port map (
03906       CLK             => BCLK,
03907       UPPER_BOUND_A  => colwinho1(5 downto 0),  --! Time win upper side A, A to C
03908       LOWER_BOUND_A  => colwinlo1(5 downto 0),  --! Time win lower side A, A to C
03909       UPPER_BOUND_C  => colwinho2(5 downto 0),  --! Time win upper side C, A to C
03910       LOWER_BOUND_C  => colwinlo2(5 downto 0),  --! Time win lower side C, A to C
03911       UPPER_BOUND_A1 => colwinho2(5 downto 0),  --! Time win upper side A, C to A
03912       LOWER_BOUND_A1 => colwinlo2(5 downto 0),  --! Time win lower side A, C to A
03913       UPPER_BOUND_C1 => colwinho1(5 downto 0),  --! Time win upper side C, C to A
03914       LOWER_BOUND_C1 => colwinlo1(5 downto 0),  --! Time win lower side C, C to A
03915       UPPER_BOUND_AW => colwinhw(5 downto 0),   --! Time win upper side A, wide
03916       LOWER_BOUND_AW => colwinlw(5 downto 0),   --! Time win lower side A, wide
03917       UPPER_BOUND_CW => colwinhw(5 downto 0),   --! Time win upper side C, wide
03918       LOWER_BOUND_CW => colwinlw(5 downto 0),   --! Time win lower side C, wide
03919       IRENA1         => irena1_i,
03920       EWA1           => ewa1_i,
03921       HEINZ1         => heinz1_i,
03922       ANDREJ1        => andrej1_i,
03923       MARKO1         => marko1_i,
03924       WILLIAM1       => william1_i,
03925       HARRIS1        => harris1_i,
03926       HELMUT1        => helmut1_i,
03927       S_IRENA1       => algo_data(191),
03928       S_EWA1         => algo_data(167),
03929       S_ANDREJ1      => algo_data(143),
03930       S_HEINZ1       => algo_data(119),
03931       S_MARKO1       => algo_data(95),
03932       S_WILLIAM1     => algo_data(71),
03933       S_HARRIS1      => algo_data(47),
03934       S_HELMUT1      => algo_data(23),
03935       IRENA2         => irena2_i,
03936       EWA2           => ewa2_i,
03937       HEINZ2         => heinz2_i,
03938       ANDREJ2        => andrej2_i,
03939       MARKO2         => marko2_i,
03940       WILLIAM2       => william2_i,
03941       HARRIS2        => harris2_i,
03942       HELMUT2        => helmut2_i,
03943       S_IRENA2       => algo_data(179),
03944       S_EWA2         => algo_data(155),
03945       S_ANDREJ2      => algo_data(131),
03946       S_HEINZ2       => algo_data(107),
03947       S_MARKO2       => algo_data(83),
03948       S_WILLIAM2     => algo_data(59),
03949       S_HARRIS2      => algo_data (35),
03950       S_HELMUT2      => algo_data (11),
03951       CTP_OUT        => ctp_int
03952       );
03953 
03954   delta_vld_backa <= ctp_int(2);
03955   delta_vld_backc <= ctp_int(1);
03956 
03957 
03958   command_extend1 : extend_test
03959     generic map (
03960       LEN => 4 )
03961     port map
03962     (
03963       CLK  => EMAC_CLK ,
03964       RES  => RESET,
03965       ENDM => open,
03966       A    => param_en_vec (7),
03967       Y    => set_ctp_i
03968       );
03969 
03970   ctp_load <= ctp_load_i when ctp_src_i = '1' else
03971               (others => '0') when RESET = '1' else
03972               ctp_int;
03973   set_ctp <= set_ctp_i when ctp_src_i = '1' else
03974              '0' when (RESET or rate_block) = '1' else
03975              '1';
03976 
03977 
03978   CTP_intf : ctp_comm
03979     port map (
03980       CLK     => BCLK,
03981       RESET   => RESET,
03982       SET_EN  => set_ctp,
03983       SET_VAL => ctp_load,
03984       CTP_OUT => ctp_out
03985       );  
03986 
03987   CTP <= ctp_out;
03988 
03989 
03990   trigger_rate_1 : process (BCLK, RESET)
03991   begin  -- process trigger_rate_1
03992     if RESET = '1' then                   -- asynchronous reset (active high)
03993       trig_rate_AttC <= (others => '0');
03994     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
03995       if ctp_int(9) = '1' then
03996         trig_rate_AttC <= trig_rate_AttC + 1;
03997       end if;
03998     end if;
03999   end process trigger_rate_1;
04000 
04001 
04002   trigger_rate_2 : process (BCLK, RESET)
04003   begin  -- process trigger_rate_1
04004     if RESET = '1' then                   -- asynchronous reset (active high)
04005       trig_rate_AttA <= (others => '0');
04006     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04007       if ctp_int(8) = '1' then
04008         trig_rate_AttA <= trig_rate_AttA + 1;
04009       end if;
04010     end if;
04011   end process trigger_rate_2;
04012 
04013 
04014   trigger_rate_3 : process (BCLK, RESET)
04015   begin  -- process trigger_rate_1
04016     if RESET = '1' then                   -- asynchronous reset (active high)
04017       trig_rate_Wide <= (others => '0');
04018     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04019       if ctp_int(3) = '1' then
04020         trig_rate_Wide <= trig_rate_Wide + 1;
04021       end if;
04022     end if;
04023   end process trigger_rate_3;
04024 
04025 
04026   trigger_rate_4 : process (BCLK, RESET)
04027   begin  -- process trigger_rate_1
04028     if RESET = '1' then                   -- asynchronous reset (active high)
04029       trig_rate_CtoA <= (others => '0');
04030     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04031       if ctp_int(2) = '1' then
04032         trig_rate_CtoA <= trig_rate_CtoA + 1;
04033       end if;
04034     end if;
04035   end process trigger_rate_4;
04036 
04037 
04038   trigger_rate_5 : process (BCLK, RESET)
04039   begin  -- process trigger_rate_1
04040     if RESET = '1' then                   -- asynchronous reset (active high)
04041       trig_rate_AtoC <= (others => '0');
04042     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04043       if ctp_int(1) = '1' then
04044         trig_rate_AtoC <= trig_rate_AtoC + 1;
04045       end if;
04046     end if;
04047   end process trigger_rate_5;
04048 
04049 
04050   trigger_rate_6a : process (BCLK, RESET)
04051   begin  -- process trigger_rate_1
04052     if RESET = '1' then                   -- asynchronous reset (active high)
04053       trig_rate_Mult1A <= (others => '0');
04054     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04055       if (ctp_int(4) = '1') and (ctp_int(5) = '0') then
04056         trig_rate_Mult1A <= trig_rate_Mult1A + 1;
04057       end if;
04058     end if;
04059   end process trigger_rate_6a;
04060 
04061 
04062   trigger_rate_7a : process (BCLK, RESET)
04063   begin  -- process trigger_rate_1
04064     if RESET = '1' then                   -- asynchronous reset (active high)
04065       trig_rate_Mult2A <= (others => '0');
04066     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04067       if (ctp_int(4) = '0') and (ctp_int(5) = '1') then
04068         trig_rate_Mult2A <= trig_rate_Mult2A + 1;
04069       end if;
04070     end if;
04071   end process trigger_rate_7a;
04072 
04073 
04074   trigger_rate_8a : process (BCLK, RESET)
04075   begin  -- process trigger_rate_1
04076     if RESET = '1' then                   -- asynchronous reset (active high)
04077       trig_rate_Mult3pA <= (others => '0');
04078     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04079       if (ctp_int(4) = '1') and (ctp_int(5) = '1') then
04080         trig_rate_Mult3pA <= trig_rate_Mult3pA + 1;
04081       end if;
04082     end if;
04083   end process trigger_rate_8a;
04084 
04085 
04086   trigger_rate_6c : process (BCLK, RESET)
04087   begin  -- process trigger_rate_1
04088     if RESET = '1' then                   -- asynchronous reset (active high)
04089       trig_rate_Mult1C <= (others => '0');
04090     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04091       if (ctp_int(6) = '1') and (ctp_int(7) = '0') then
04092         trig_rate_Mult1C <= trig_rate_Mult1C + 1;
04093       end if;
04094     end if;
04095   end process trigger_rate_6c;
04096 
04097 
04098   trigger_rate_7c : process (BCLK, RESET)
04099   begin  -- process trigger_rate_1
04100     if RESET = '1' then                   -- asynchronous reset (active high)
04101       trig_rate_Mult2C <= (others => '0');
04102     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04103       if (ctp_int(6) = '0') and (ctp_int(7) = '1') then
04104         trig_rate_Mult2C <= trig_rate_Mult2C + 1;
04105       end if;
04106     end if;
04107   end process trigger_rate_7c;
04108 
04109 
04110   trigger_rate_8c : process (BCLK, RESET)
04111   begin  -- process trigger_rate_1
04112     if RESET = '1' then                   -- asynchronous reset (active high)
04113       trig_rate_Mult3pC <= (others => '0');
04114     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04115       if (ctp_int(6) = '1') and (ctp_int(7) = '1') then
04116         trig_rate_Mult3pC <= trig_rate_Mult3pC + 1;
04117       end if;
04118     end if;
04119   end process trigger_rate_8c;
04120 
04121 -------------------------------------------------------------------------------
04122 --                                CIBU
04123 -------------------------------------------------------------------------------
04124 
04125 
04126   command_extend2 : extend_test
04127     generic map (
04128       LEN => 4 )
04129     port map
04130     (
04131       CLK  => EMAC_CLK ,
04132       RES  => RESET,
04133       ENDM => open,
04134       A    => param_en_vec (6),
04135       Y    => set_i_perm
04136       );
04137 
04138 
04139   command_extend3 : extend_test
04140     generic map (
04141       LEN => 4 )
04142     port map
04143     (
04144       CLK  => EMAC_CLK ,
04145       RES  => RESET,
04146       ENDM => open,
04147       A    => param_en_vec(5),
04148       Y    => set_b_perm
04149       );
04150 
04151   injection_permit <= i_perm_i when cibi_src_i = '1' else
04152                       '1' when (RESET or rate_block) = '1' else
04153                       int_inj_permit;
04154   set_injection_permit <= set_i_perm when cibi_src_i = '1' else
04155                           '0' when (RESET or rate_block) = '1' else
04156                           '1';
04157   beam_permit <= b_perm_i when cibb_src_i = '1' else
04158                  '1' when (RESET or rate_block) = '1' else
04159                  int_beam_permit;
04160   set_beam_permit <= set_b_perm when cibb_src_i = '1' else
04161                      '0' when (RESET or rate_block) = '1' else
04162                      '1';
04163 
04164   beam_permit_latch : process (BCLK, RESET)
04165   begin  -- process beam_permit_latch
04166     if RESET = '1' then                   -- asynchronous reset (active high)
04167       int_beam_permit <= '1';
04168     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04169       if ackb = '1' then
04170         int_beam_permit <= '1';
04171       elsif dump_beam = '1' then
04172         int_beam_permit <= '0';
04173       end if;
04174     end if;
04175   end process beam_permit_latch;
04176 
04177   inj_permit_latch : process (BCLK, RESET)
04178   begin  -- process beam_permit_latch
04179     if RESET = '1' then                   -- asynchronous reset (active high)
04180       int_inj_permit <= '1';
04181     elsif BCLK'event and BCLK = '1' then  -- rising clock edge
04182       if acki = '1' then
04183         int_inj_permit <= '1';
04184       elsif dump_beam = '1' then
04185         int_inj_permit <= '0';
04186       end if;
04187     end if;
04188   end process inj_permit_latch;
04189 
04190 
04191   CIBU : cibu_comm
04192     port map (
04193       CLK               => BCLK,
04194       RESET             => RESET,
04195       INJ_PERM_SET_EN  => set_injection_permit ,
04196       INJ_PERM_SET     => injection_permit ,
04197       BEAM_PERM_SET_EN => set_beam_permit,
04198       BEAM_PERM_SET    => beam_permit,
04199       INJ_PERM_1       => inj_p1_i,
04200       INJ_PERM_2       => inj_p2_i,
04201       BEAM_PERM_1      => bem_p1_i,
04202       BEAM_PERM_2      => bem_p2_i
04203       );
04204 
04205   INJECT_PERM_1 <= inj_p1_i;               -- and sata_iperm;
04206   INJECT_PERM_2 <= inj_p2_i;               -- and sata_iperm;
04207   BEAM_PERM_1   <= bem_p1_i;               -- and sata_bperm;
04208   BEAM_PERM_2   <= bem_p2_i;               -- and sata_bperm;
04209   inj_p_i       <= inj_p1_i and inj_p2_i;  -- and sata_iperm;
04210   bem_p_i       <= bem_p1_i and bem_p2_i;  -- and sata_bperm;
04211 
04212   en_abort_contr <= not rate_block;
04213   conf1 : if kRODconf = "0" generate
04214     high_gain_i <= (proc_data_ii(167) or proc_data_ii(155)) &
04215                    (proc_data_ii(119) or proc_data_ii(107)) &
04216                    (proc_data_ii(71) or proc_data_ii(59)) &
04217                    (proc_data_ii(23) or proc_data_ii(11));
04218     low_gain_i <= (proc_data_ii(191) or proc_data_ii(179)) &
04219                   (proc_data_ii(143) or proc_data_ii(131)) &
04220                   (proc_data_ii(95) or proc_data_ii(83)) &
04221                   (proc_data_ii(47) or proc_data_ii(35));
04222   end generate conf1;
04223   conf2 : if kRODconf = "1" generate
04224     low_gain_i <= (proc_data_ii(167) or proc_data_ii(155)) &
04225                   (proc_data_ii(119) or proc_data_ii(107)) &
04226                   (proc_data_ii(71) or proc_data_ii(59)) &
04227                   (proc_data_ii(23) or proc_data_ii(11));
04228     high_gain_i <= (proc_data_ii(191) or proc_data_ii(179)) &
04229                    (proc_data_ii(143) or proc_data_ii(131)) &
04230                    (proc_data_ii(95) or proc_data_ii(83)) &
04231                    (proc_data_ii(47) or proc_data_ii(35));
04232   end generate conf2;
04233 
04234 
04235   abort_contr : abort_controller
04236     port map (
04237       CLK         => BCLK,
04238       RES         => RESET,
04239       WR_EN       => en_abort_contr,
04240       BCID        => bcid_i,
04241       HIGH_GAIN   => high_gain_i,
04242       LOW_GAIN    => low_gain_i,
04243       CHECK_EN    => '0',               --sata_data_vld_a,
04244       BCID_R      => x"000",            --sata_data_out_a(11 downto 0),
04245       HIGH_GAIN_R => "0000",            --sata_data_out_a(15 downto 12),
04246       LOW_GAIN_R  => "0000",            --sata_data_out_a(19 downto 16),
04247       ABORT       => dump_beam
04248       );
04249 
04250 -------------------------------------------------------------------------------
04251 --                                SATA
04252 -------------------------------------------------------------------------------
04253 
04254   sata_data_clk                <= not sata_data_clk when rising_edge(SATA_LOGIC_CLK);
04255   sata_data_in_b(11 downto 0)  <= bcid_i;
04256   sata_data_in_b(15 downto 12) <= high_gain_i;
04257   sata_data_in_b(19 downto 16) <= low_gain_i;
04258   sata_data_in_a               <= (others => '0');
04259 
04260 
04261   sata_wrapper : bridge
04262     port map(
04263       CLK_RIO_IN       => SATA_REF_CLK,
04264       CLK_DRP_IN       => CLK_50,
04265       CLK_SATA_IN      => SATA_LOGIC_CLK,
04266       USRCLK_STABLE_IN  => '1',
04267       CLK_DATA_IN       => sata_data_clk,
04268       RESET_A_IN       => RESET,
04269       RESET_B_IN       => RESET,
04270       RXP_SATA_IN      => RXP_SATA_IN ,
04271       RXN_SATA_IN      => RXN_SATA_IN,
04272       TXP_SATA_OUT     => TXP_SATA_OUT,
04273       TXN_SATA_OUT     => TXN_SATA_OUT,
04274       TX_A_READY       => open,         --sata_tx_a_ready_i,
04275       TX_B_READY       => sata_tx_b_ready_i ,
04276       RX_A_READY       => open,         --sata_rx_a_ready_i,
04277       RX_B_READY       => sata_rx_b_ready_i ,
04278       A_DATA_IN        => sata_data_in_a,
04279       B_DATA_IN        => sata_data_in_b,
04280       A_DATA_VALID_IN  => '0',
04281       B_DATA_VALID_IN  => '1',
04282       A_DATA_OUT       => sata_data_out_a ,
04283       B_DATA_OUT       => sata_data_out_b ,
04284       A_DATA_VALID_OUT => sata_data_vld_a,
04285       B_DATA_VALID_OUT => sata_data_vld_b,
04286       A_DATA_ERROR     => sata_error_a,
04287       B_DATA_ERROR     => sata_error_b,
04288       A_LISTENING      => sata_listening_a ,
04289       B_LISTENING      => sata_listening_b ,
04290       A_PACKAGE_GOOD   => sata_package_good_a ,
04291       B_PACKAGE_GOOD   => sata_package_good_b ,
04292       A_PACKAGE_BAD    => sata_package_bad_a ,
04293       B_PACKAGE_BAD    => sata_package_bad_b ,
04294       c_scope          => open
04295       );
04296 
04297   SATA_OK           <= sata_ok_i;
04298   sata_tx_a_ready_i <= '1';             -- ch A currently unused, see BCM twiki
04299   sata_rx_a_ready_i <= '1';
04300   sata_present_true : if kSATA_con = true generate
04301     sata_ok_i <= sata_tx_a_ready_i and sata_rx_a_ready_i and  --* use when boards are connected
04302                  sata_tx_b_ready_i and sata_rx_b_ready_i;
04303   end generate sata_present_true;
04304   sata_present_false : if kSATA_con = false generate
04305     sata_ok_i <= '1';                   --* use when boards aren't connected   
04306   end generate sata_present_false;
04307 
04308 -------------------------------------------------------------------------------
04309 --                              Chipscope
04310 -------------------------------------------------------------------------------   
04311 
04312 
04313   chipscope : if kUseChipscope = true generate
04314 
04315 --* Usage: the ILA Cores can be placed at arbitrary places in the design (wherever
04316 --* needed for debugging purposes) but all 3 must always be instantiated and 
04317 --* connected to the ICON control port to pass the Map phase. Unused trig0 inputs
04318 --* must be connected to '0' to avoid optimization inside the ILA core by the
04319 --* Synthesis tool.
04320 
04321 
04322     chipscope_cntr : icon
04323       port map (
04324         control0 => control0_i,
04325         control1 => control1_i,
04326         control2 => control2_i
04327         );
04328 
04329 
04330     chipscope_probe1 : ila
04331       port map (
04332         control => control0_i,
04333         clk     => BCLK2X_P,
04334         trig0   => probe1_i
04335         );
04336 
04337     probe1_i <= gnd_vec_long(49 downto 0);
04338 
04339 
04340     chipscope_probe2 : ila
04341       port map (
04342         control => control1_i,
04343         clk     => BCLK2X_P,
04344         trig0   => probe2_i
04345         );
04346 
04347 --    probe2_i(49)           <= BCLK;
04348 --    probe2_i(48)           <= BCLK2X_P;
04349 --    probe2_i(47)           <= RESET;
04350 --    probe2_i(46)           <= busy_i;
04351 --    probe2_i(45)           <= busy_ext;
04352 --    probe2_i(44)           <= data_rod_vld;
04353 --    probe2_i(43)           <= l1a_i;
04354 --    probe2_i(42)           <= sl_trig_pc;
04355 --    probe2_i(41)           <= pc_cmdvld;
04356 --    probe2_i(40 downto 33) <= pc_cmd;
04357 --    probe2_i(32)           <= busy_ext_rs;
04358 --    probe2_i(31 downto 20) <= pc_datatype;
04359 --    probe2_i(7 downto 0)   <= fpgaid_i;
04360 --    probe2_i(8)            <= fpgaid_en;
04361 --    probe2_i(16 downto 9)  <= stat_byte;
04362 --    probe2_i(19 downto 17) <= "000";
04363     --probe2_i(31 downto 0)  <= SL_UD_i;
04364     --probe2_i(32)           <= SL_UWEN_i;
04365     probe2_i(49 downto 0) <= (others => '0');
04366 
04367 
04368     chipscope_probe3 : ila
04369       port map (
04370         control => control2_i,
04371         clk     => BCLK,
04372         trig0   => probe3_i
04373         );
04374 
04375     probe3_i(49)           <= lf_wren;
04376     probe3_i(48)           <= lf_rden;
04377     probe3_i(47 downto 36) <= l1a_bid_in;
04378     probe3_i(35 downto 24) <= l1a_bid;
04379     probe3_i(23)           <= data_rod_vld;
04380     probe3_i(22 downto 11) <= data_rod(191 downto 180);
04381     probe3_i(10)           <= lf_empty;
04382     probe3_i(9)            <= next_l1a;
04383     probe3_i(8)            <= get_next_l1a;
04384     probe3_i(7)            <= next_l1a1;
04385     probe3_i(6)            <= busy_i;
04386     probe3_i(5)            <= l1a_done;
04387     probe3_i(4)            <= lf_rden2;
04388     probe3_i(3 downto 0)   <= (others => '0');
04389 
04390   end generate chipscope;
04391 
04392 end rio2mem_arc;