ddr2_mem_data_path_iobs_0.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_data_path_iobs_0.vhd,v $
--*  $Revision: 1.3.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 21:55:52 $                              *


--*                                                            *
--**************************************************************
-------------------------------------------------------------------------------
-- Copyright (c) 2005 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
-------------------------------------------------------------------------------
--   ____  ____
--  /   /\/   /
-- /___/  \  / Vendor: Xilinx
-- \   \   \/ Version: 1.6
--  \   \ Application : MIG
--  /   / Filename: ddr2_mem_data_path_iobs_0.vhd
-- /___/   /\ Date Last Modified:  Wed Jun 1 2005
-- \   \  /  \Date Created: Mon May 2 2005
--  \___\/\___\
-- 
-- Device: Virtex-4
-- Design Name: DDR2_V4
-------------------------------------------------------------------------------


library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
library work;
use work.ddr2_mem_parameters_0.all;

library unisim;

use unisim.vcomponents.all;



entity ddr2_mem_data_path_iobs_0 is
  port (
    CLK             : in    std_logic;
    CLK90           : in    std_logic;
    CAL_CLK         : in    std_logic;
    RESET0          : in    std_logic;
    RESET90         : in    std_logic;
    dqs_idelay_inc  : in    std_logic_vector(ReadEnable-1 downto 0);
    dqs_idelay_ce   : in    std_logic_vector(ReadEnable-1 downto 0);
    dqs_idelay_rst  : in    std_logic_vector(ReadEnable-1 downto 0);
    dqs_rst         : in    std_logic;
    dqs_en          : in    std_logic;
    dqs_delayed     : out   std_logic_vector(data_strobe_width-1 downto 0);
    data_idelay_inc : in    std_logic_vector(ReadEnable-1 downto 0);
    data_idelay_ce  : in    std_logic_vector(ReadEnable-1 downto 0);
    data_idelay_rst : in    std_logic_vector(ReadEnable-1 downto 0);
    wr_data_rise    : in    std_logic_vector(data_width-1 downto 0);
    wr_data_fall    : in    std_logic_vector(data_width-1 downto 0);
    mask_data_rise  : in    std_logic_vector(data_mask_width-1 downto 0);
    mask_data_fall  : in    std_logic_vector(data_mask_width-1 downto 0);
    wr_en           : in    std_logic;
    DDR_DQ          : inout std_logic_vector(data_width-1 downto 0);
    DDR_DQS         : inout std_logic_vector(data_strobe_width-1 downto 0);
    DDR_DQS_L       : inout std_logic_vector(data_strobe_width-1 downto 0);
    DDR_DM          : out   std_logic_vector(data_mask_width-1 downto 0);
    rd_data_rise    : out   std_logic_vector(data_width-1 downto 0);
    rd_data_fall    : out   std_logic_vector(data_width-1 downto 0)
    );
end entity;



architecture arc_data_path_iobs of ddr2_mem_data_path_iobs_0 is


  component ddr2_mem_v4_dqs_iob
    port (
      CLK          : in    std_logic;
      CAL_CLK      : in    std_logic;
      RESET        : in    std_logic;
      DLYINC       : in    std_logic;
      DLYCE        : in    std_logic;
      DLYRST       : in    std_logic;
      CTRL_DQS_RST : in    std_logic;
      CTRL_DQS_EN  : in    std_logic;
      DDR_DQS      : inout std_logic;
      DDR_DQS_L    : inout std_logic;
      DQS_RISE     : out   std_logic
      );
  end component;


  component ddr2_mem_v4_dq_iob
    port (
      CLK             : in    std_logic;
      CLK90           : in    std_logic;
      CAL_CLK         : in    std_logic;
      RESET           : in    std_logic;
      DATA_DLYINC     : in    std_logic;
      DATA_DLYCE      : in    std_logic;
      DATA_DLYRST     : in    std_logic;
      WRITE_DATA_RISE : in    std_logic;
      WRITE_DATA_FALL : in    std_logic;
      CTRL_WREN       : in    std_logic;
      DDR_DQ          : inout std_logic;
      READ_DATA_RISE  : out   std_logic;
      READ_DATA_FALL  : out   std_logic
      );
  end component;


  component ddr2_mem_v4_dm_iob
    port (
      CLK90          : in  std_logic;
      MASK_DATA_RISE : in  std_logic;
      MASK_DATA_FALL : in  std_logic;
      DDR_DM         : out std_logic
      );
  end component;

begin


-- ////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
--// DQS instances
--////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


  v4_dqs_iob0 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(0),
      DLYCE        => dqs_idelay_ce(0),
      DLYRST       => dqs_idelay_rst(0),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(0),
      DDR_DQS_L    => DDR_DQS_L(0),
      DQS_RISE     => dqs_delayed(0)
      );


  v4_dqs_iob1 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(0),
      DLYCE        => dqs_idelay_ce(0),
      DLYRST       => dqs_idelay_rst(0),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(1),
      DDR_DQS_L    => DDR_DQS_L(1),
      DQS_RISE     => dqs_delayed(1)
      );


  v4_dqs_iob2 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(0),
      DLYCE        => dqs_idelay_ce(0),
      DLYRST       => dqs_idelay_rst(0),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(2),
      DDR_DQS_L    => DDR_DQS_L(2),
      DQS_RISE     => dqs_delayed(2)
      );


  v4_dqs_iob3 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(0),
      DLYCE        => dqs_idelay_ce(0),
      DLYRST       => dqs_idelay_rst(0),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(3),
      DDR_DQS_L    => DDR_DQS_L(3),
      DQS_RISE     => dqs_delayed(3)
      );


  v4_dqs_iob4 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(1),
      DLYCE        => dqs_idelay_ce(1),
      DLYRST       => dqs_idelay_rst(1),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(4),
      DDR_DQS_L    => DDR_DQS_L(4),
      DQS_RISE     => dqs_delayed(4)
      );


  v4_dqs_iob5 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(1),
      DLYCE        => dqs_idelay_ce(1),
      DLYRST       => dqs_idelay_rst(1),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(5),
      DDR_DQS_L    => DDR_DQS_L(5),
      DQS_RISE     => dqs_delayed(5)
      );


  v4_dqs_iob6 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(1),
      DLYCE        => dqs_idelay_ce(1),
      DLYRST       => dqs_idelay_rst(1),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(6),
      DDR_DQS_L    => DDR_DQS_L(6),
      DQS_RISE     => dqs_delayed(6)
      );


  v4_dqs_iob7 : ddr2_mem_v4_dqs_iob
    port map (
      CLK           => CLK,
      CAL_CLK      => CAL_CLK,
      RESET        => RESET0,
      DLYINC       => dqs_idelay_inc(1),
      DLYCE        => dqs_idelay_ce(1),
      DLYRST       => dqs_idelay_rst(1),
      CTRL_DQS_RST => dqs_rst,
      CTRL_DQS_EN  => dqs_en,
      DDR_DQS      => DDR_DQS(7),
      DDR_DQS_L    => DDR_DQS_L(7),
      DQS_RISE     => dqs_delayed(7)
      );

--///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
--//// DM instances
--///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


  v4_dm_iob0 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(0),
      MASK_DATA_FALL => mask_data_fall(0),
      DDR_DM         => DDR_DM(0)
      );


  v4_dm_iob1 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(1),
      MASK_DATA_FALL => mask_data_fall(1),
      DDR_DM         => DDR_DM(1)
      );


  v4_dm_iob2 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(2),
      MASK_DATA_FALL => mask_data_fall(2),
      DDR_DM         => DDR_DM(2)
      );


  v4_dm_iob3 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(3),
      MASK_DATA_FALL => mask_data_fall(3),
      DDR_DM         => DDR_DM(3)
      );


  v4_dm_iob4 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(4),
      MASK_DATA_FALL => mask_data_fall(4),
      DDR_DM         => DDR_DM(4)
      );


  v4_dm_iob5 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(5),
      MASK_DATA_FALL => mask_data_fall(5),
      DDR_DM         => DDR_DM(5)
      );


  v4_dm_iob6 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(6),
      MASK_DATA_FALL => mask_data_fall(6),
      DDR_DM         => DDR_DM(6)
      );


  v4_dm_iob7 : ddr2_mem_v4_dm_iob
    port map (
      CLK90           => CLK90,
      MASK_DATA_RISE => mask_data_rise(7),
      MASK_DATA_FALL => mask_data_fall(7),
      DDR_DM         => DDR_DM(7)
      );

--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
--//  DQ_IOB4 instances
--/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////


  v4_dq_iob_0 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(0),
      WRITE_DATA_FALL => wr_data_fall(0),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(0),
      READ_DATA_RISE  => rd_data_rise(0),
      READ_DATA_FALL  => rd_data_fall(0)
      );


  v4_dq_iob_1 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(1),
      WRITE_DATA_FALL => wr_data_fall(1),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(1),
      READ_DATA_RISE  => rd_data_rise(1),
      READ_DATA_FALL  => rd_data_fall(1)
      );


  v4_dq_iob_2 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(2),
      WRITE_DATA_FALL => wr_data_fall(2),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(2),
      READ_DATA_RISE  => rd_data_rise(2),
      READ_DATA_FALL  => rd_data_fall(2)
      );


  v4_dq_iob_3 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(3),
      WRITE_DATA_FALL => wr_data_fall(3),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(3),
      READ_DATA_RISE  => rd_data_rise(3),
      READ_DATA_FALL  => rd_data_fall(3)
      );


  v4_dq_iob_4 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(4),
      WRITE_DATA_FALL => wr_data_fall(4),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(4),
      READ_DATA_RISE  => rd_data_rise(4),
      READ_DATA_FALL  => rd_data_fall(4)
      );


  v4_dq_iob_5 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(5),
      WRITE_DATA_FALL => wr_data_fall(5),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(5),
      READ_DATA_RISE  => rd_data_rise(5),
      READ_DATA_FALL  => rd_data_fall(5)
      );


  v4_dq_iob_6 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(6),
      WRITE_DATA_FALL => wr_data_fall(6),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(6),
      READ_DATA_RISE  => rd_data_rise(6),
      READ_DATA_FALL  => rd_data_fall(6)
      );


  v4_dq_iob_7 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(7),
      WRITE_DATA_FALL => wr_data_fall(7),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(7),
      READ_DATA_RISE  => rd_data_rise(7),
      READ_DATA_FALL  => rd_data_fall(7)
      );


  v4_dq_iob_8 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(8),
      WRITE_DATA_FALL => wr_data_fall(8),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(8),
      READ_DATA_RISE  => rd_data_rise(8),
      READ_DATA_FALL  => rd_data_fall(8)
      );


  v4_dq_iob_9 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(9),
      WRITE_DATA_FALL => wr_data_fall(9),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(9),
      READ_DATA_RISE  => rd_data_rise(9),
      READ_DATA_FALL  => rd_data_fall(9)
      );


  v4_dq_iob_10 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(10),
      WRITE_DATA_FALL => wr_data_fall(10),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(10),
      READ_DATA_RISE  => rd_data_rise(10),
      READ_DATA_FALL  => rd_data_fall(10)
      );


  v4_dq_iob_11 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(11),
      WRITE_DATA_FALL => wr_data_fall(11),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(11),
      READ_DATA_RISE  => rd_data_rise(11),
      READ_DATA_FALL  => rd_data_fall(11)
      );


  v4_dq_iob_12 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(12),
      WRITE_DATA_FALL => wr_data_fall(12),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(12),
      READ_DATA_RISE  => rd_data_rise(12),
      READ_DATA_FALL  => rd_data_fall(12)
      );


  v4_dq_iob_13 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(13),
      WRITE_DATA_FALL => wr_data_fall(13),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(13),
      READ_DATA_RISE  => rd_data_rise(13),
      READ_DATA_FALL  => rd_data_fall(13)
      );


  v4_dq_iob_14 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(14),
      WRITE_DATA_FALL => wr_data_fall(14),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(14),
      READ_DATA_RISE  => rd_data_rise(14),
      READ_DATA_FALL  => rd_data_fall(14)
      );


  v4_dq_iob_15 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(15),
      WRITE_DATA_FALL => wr_data_fall(15),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(15),
      READ_DATA_RISE  => rd_data_rise(15),
      READ_DATA_FALL  => rd_data_fall(15)
      );


  v4_dq_iob_16 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(16),
      WRITE_DATA_FALL => wr_data_fall(16),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(16),
      READ_DATA_RISE  => rd_data_rise(16),
      READ_DATA_FALL  => rd_data_fall(16)
      );


  v4_dq_iob_17 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(17),
      WRITE_DATA_FALL => wr_data_fall(17),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(17),
      READ_DATA_RISE  => rd_data_rise(17),
      READ_DATA_FALL  => rd_data_fall(17)
      );


  v4_dq_iob_18 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(18),
      WRITE_DATA_FALL => wr_data_fall(18),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(18),
      READ_DATA_RISE  => rd_data_rise(18),
      READ_DATA_FALL  => rd_data_fall(18)
      );


  v4_dq_iob_19 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(19),
      WRITE_DATA_FALL => wr_data_fall(19),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(19),
      READ_DATA_RISE  => rd_data_rise(19),
      READ_DATA_FALL  => rd_data_fall(19)
      );


  v4_dq_iob_20 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(20),
      WRITE_DATA_FALL => wr_data_fall(20),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(20),
      READ_DATA_RISE  => rd_data_rise(20),
      READ_DATA_FALL  => rd_data_fall(20)
      );


  v4_dq_iob_21 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(21),
      WRITE_DATA_FALL => wr_data_fall(21),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(21),
      READ_DATA_RISE  => rd_data_rise(21),
      READ_DATA_FALL  => rd_data_fall(21)
      );


  v4_dq_iob_22 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(22),
      WRITE_DATA_FALL => wr_data_fall(22),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(22),
      READ_DATA_RISE  => rd_data_rise(22),
      READ_DATA_FALL  => rd_data_fall(22)
      );


  v4_dq_iob_23 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(23),
      WRITE_DATA_FALL => wr_data_fall(23),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(23),
      READ_DATA_RISE  => rd_data_rise(23),
      READ_DATA_FALL  => rd_data_fall(23)
      );


  v4_dq_iob_24 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(24),
      WRITE_DATA_FALL => wr_data_fall(24),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(24),
      READ_DATA_RISE  => rd_data_rise(24),
      READ_DATA_FALL  => rd_data_fall(24)
      );


  v4_dq_iob_25 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(25),
      WRITE_DATA_FALL => wr_data_fall(25),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(25),
      READ_DATA_RISE  => rd_data_rise(25),
      READ_DATA_FALL  => rd_data_fall(25)
      );


  v4_dq_iob_26 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(26),
      WRITE_DATA_FALL => wr_data_fall(26),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(26),
      READ_DATA_RISE  => rd_data_rise(26),
      READ_DATA_FALL  => rd_data_fall(26)
      );


  v4_dq_iob_27 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(27),
      WRITE_DATA_FALL => wr_data_fall(27),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(27),
      READ_DATA_RISE  => rd_data_rise(27),
      READ_DATA_FALL  => rd_data_fall(27)
      );


  v4_dq_iob_28 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(28),
      WRITE_DATA_FALL => wr_data_fall(28),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(28),
      READ_DATA_RISE  => rd_data_rise(28),
      READ_DATA_FALL  => rd_data_fall(28)
      );


  v4_dq_iob_29 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(29),
      WRITE_DATA_FALL => wr_data_fall(29),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(29),
      READ_DATA_RISE  => rd_data_rise(29),
      READ_DATA_FALL  => rd_data_fall(29)
      );


  v4_dq_iob_30 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce (0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(30),
      WRITE_DATA_FALL => wr_data_fall(30),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(30),
      READ_DATA_RISE  => rd_data_rise(30),
      READ_DATA_FALL  => rd_data_fall(30)
      );


  v4_dq_iob_31 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (0),
      DATA_DLYCE      => data_idelay_ce(0),
      DATA_DLYRST     => data_idelay_rst (0),
      WRITE_DATA_RISE => wr_data_rise(31),
      WRITE_DATA_FALL => wr_data_fall(31),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(31),
      READ_DATA_RISE  => rd_data_rise(31),
      READ_DATA_FALL  => rd_data_fall(31)
      );


  v4_dq_iob_32 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(32),
      WRITE_DATA_FALL => wr_data_fall(32),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(32),
      READ_DATA_RISE  => rd_data_rise(32),
      READ_DATA_FALL  => rd_data_fall(32)
      );


  v4_dq_iob_33 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(33),
      WRITE_DATA_FALL => wr_data_fall(33),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(33),
      READ_DATA_RISE  => rd_data_rise(33),
      READ_DATA_FALL  => rd_data_fall(33)
      );


  v4_dq_iob_34 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(34),
      WRITE_DATA_FALL => wr_data_fall(34),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(34),
      READ_DATA_RISE  => rd_data_rise(34),
      READ_DATA_FALL  => rd_data_fall(34)
      );


  v4_dq_iob_35 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(35),
      WRITE_DATA_FALL => wr_data_fall(35),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(35),
      READ_DATA_RISE  => rd_data_rise(35),
      READ_DATA_FALL  => rd_data_fall(35)
      );


  v4_dq_iob_36 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(36),
      WRITE_DATA_FALL => wr_data_fall(36),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(36),
      READ_DATA_RISE  => rd_data_rise(36),
      READ_DATA_FALL  => rd_data_fall(36)
      );


  v4_dq_iob_37 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(37),
      WRITE_DATA_FALL => wr_data_fall(37),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(37),
      READ_DATA_RISE  => rd_data_rise(37),
      READ_DATA_FALL  => rd_data_fall(37)
      );


  v4_dq_iob_38 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(38),
      WRITE_DATA_FALL => wr_data_fall(38),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(38),
      READ_DATA_RISE  => rd_data_rise(38),
      READ_DATA_FALL  => rd_data_fall(38)
      );


  v4_dq_iob_39 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(39),
      WRITE_DATA_FALL => wr_data_fall(39),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(39),
      READ_DATA_RISE  => rd_data_rise(39),
      READ_DATA_FALL  => rd_data_fall(39)
      );


  v4_dq_iob_40 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(40),
      WRITE_DATA_FALL => wr_data_fall(40),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(40),
      READ_DATA_RISE  => rd_data_rise(40),
      READ_DATA_FALL  => rd_data_fall(40)
      );


  v4_dq_iob_41 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(41),
      WRITE_DATA_FALL => wr_data_fall(41),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(41),
      READ_DATA_RISE  => rd_data_rise(41),
      READ_DATA_FALL  => rd_data_fall(41)
      );


  v4_dq_iob_42 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(42),
      WRITE_DATA_FALL => wr_data_fall(42),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(42),
      READ_DATA_RISE  => rd_data_rise(42),
      READ_DATA_FALL  => rd_data_fall(42)
      );


  v4_dq_iob_43 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(43),
      WRITE_DATA_FALL => wr_data_fall(43),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(43),
      READ_DATA_RISE  => rd_data_rise(43),
      READ_DATA_FALL  => rd_data_fall(43)
      );


  v4_dq_iob_44 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(44),
      WRITE_DATA_FALL => wr_data_fall(44),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(44),
      READ_DATA_RISE  => rd_data_rise(44),
      READ_DATA_FALL  => rd_data_fall(44)
      );


  v4_dq_iob_45 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(45),
      WRITE_DATA_FALL => wr_data_fall(45),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(45),
      READ_DATA_RISE  => rd_data_rise(45),
      READ_DATA_FALL  => rd_data_fall(45)
      );


  v4_dq_iob_46 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(46),
      WRITE_DATA_FALL => wr_data_fall(46),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(46),
      READ_DATA_RISE  => rd_data_rise(46),
      READ_DATA_FALL  => rd_data_fall(46)
      );


  v4_dq_iob_47 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce (1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(47),
      WRITE_DATA_FALL => wr_data_fall(47),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(47),
      READ_DATA_RISE  => rd_data_rise(47),
      READ_DATA_FALL  => rd_data_fall(47)
      );


  v4_dq_iob_48 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(48),
      WRITE_DATA_FALL => wr_data_fall(48),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(48),
      READ_DATA_RISE  => rd_data_rise(48),
      READ_DATA_FALL  => rd_data_fall(48)
      );


  v4_dq_iob_49 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(49),
      WRITE_DATA_FALL => wr_data_fall(49),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(49),
      READ_DATA_RISE  => rd_data_rise(49),
      READ_DATA_FALL  => rd_data_fall(49)
      );


  v4_dq_iob_50 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(50),
      WRITE_DATA_FALL => wr_data_fall(50),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(50),
      READ_DATA_RISE  => rd_data_rise(50),
      READ_DATA_FALL  => rd_data_fall(50)
      );


  v4_dq_iob_51 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(51),
      WRITE_DATA_FALL => wr_data_fall(51),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(51),
      READ_DATA_RISE  => rd_data_rise(51),
      READ_DATA_FALL  => rd_data_fall(51)
      );


  v4_dq_iob_52 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(52),
      WRITE_DATA_FALL => wr_data_fall(52),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(52),
      READ_DATA_RISE  => rd_data_rise(52),
      READ_DATA_FALL  => rd_data_fall(52)
      );


  v4_dq_iob_53 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(53),
      WRITE_DATA_FALL => wr_data_fall(53),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(53),
      READ_DATA_RISE  => rd_data_rise(53),
      READ_DATA_FALL  => rd_data_fall(53)
      );


  v4_dq_iob_54 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(54),
      WRITE_DATA_FALL => wr_data_fall(54),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(54),
      READ_DATA_RISE  => rd_data_rise(54),
      READ_DATA_FALL  => rd_data_fall(54)
      );


  v4_dq_iob_55 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(55),
      WRITE_DATA_FALL => wr_data_fall(55),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(55),
      READ_DATA_RISE  => rd_data_rise(55),
      READ_DATA_FALL  => rd_data_fall(55)
      );


  v4_dq_iob_56 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(56),
      WRITE_DATA_FALL => wr_data_fall(56),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(56),
      READ_DATA_RISE  => rd_data_rise(56),
      READ_DATA_FALL  => rd_data_fall(56)
      );


  v4_dq_iob_57 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(57),
      WRITE_DATA_FALL => wr_data_fall(57),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(57),
      READ_DATA_RISE  => rd_data_rise(57),
      READ_DATA_FALL  => rd_data_fall(57)
      );


  v4_dq_iob_58 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(58),
      WRITE_DATA_FALL => wr_data_fall(58),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(58),
      READ_DATA_RISE  => rd_data_rise(58),
      READ_DATA_FALL  => rd_data_fall(58)
      );


  v4_dq_iob_59 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(59),
      WRITE_DATA_FALL => wr_data_fall(59),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(59),
      READ_DATA_RISE  => rd_data_rise(59),
      READ_DATA_FALL  => rd_data_fall(59)
      );


  v4_dq_iob_60 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(60),
      WRITE_DATA_FALL => wr_data_fall(60),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(60),
      READ_DATA_RISE  => rd_data_rise(60),
      READ_DATA_FALL  => rd_data_fall(60)
      );


  v4_dq_iob_61 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(61),
      WRITE_DATA_FALL => wr_data_fall(61),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(61),
      READ_DATA_RISE  => rd_data_rise(61),
      READ_DATA_FALL  => rd_data_fall(61)
      );


  v4_dq_iob_62 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(62),
      WRITE_DATA_FALL => wr_data_fall(62),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(62),
      READ_DATA_RISE  => rd_data_rise(62),
      READ_DATA_FALL  => rd_data_fall(62)
      );


  v4_dq_iob_63 : ddr2_mem_v4_dq_iob
    port map (
      CLK             => CLK,
      CLK90           => CLK90,
      CAL_CLK         => CAL_CLK,
      RESET           => RESET90,
      DATA_DLYINC     => data_idelay_inc (1),
      DATA_DLYCE      => data_idelay_ce(1),
      DATA_DLYRST     => data_idelay_rst (1),
      WRITE_DATA_RISE => wr_data_rise(63),
      WRITE_DATA_FALL => wr_data_fall(63),
      CTRL_WREN       => wr_en,
      DDR_DQ          => DDR_DQ(63),
      READ_DATA_RISE  => rd_data_rise(63),
      READ_DATA_FALL  => rd_data_fall(63)
      );

end arc_data_path_iobs;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:03 2008 for BCM-AAA by  1.5.7.1-20081012