BCM-AAA: delta_t_ac_top.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/delta_t_ac_top.vhd,v $
00015 --*  $Revision: 1.9.2.12 $                                          *
00016 --*  $Name: dev $                                                 *
00017 --*  $Author: mniegl $                                         *
00018 --*  $Date: 2008/11/03 17:57:42 $                              *
00019 
00020 
00021 
00022 --*                                                            *
00023 --**************************************************************
00024 
00025 library ieee;
00026 
00027 use ieee.std_logic_1164.all;
00028 
00029 use ieee.std_logic_arith.all;
00030 
00031 use ieee.std_logic_unsigned.all;
00032 
00033 use ieee.numeric_std.all;
00034 
00035 library unisim;
00036 
00037 use unisim.vcomponents.all;
00038 library work;
00039 use work.daq_header.all;
00040 use work.main_components.all;
00041 
00042 
00043 
00044 
00045 
00046 
00047 
00048 
00049 
00050 
00051 
00052 entity delta_t_ac_top is
00053   port (
00054     CLK           : in  std_logic;
00055     UPPER_BOUND_A : in  std_logic_vector(5 downto 0) := "101110";
00056     LOWER_BOUND_A : in  std_logic_vector(5 downto 0) := "010000";
00057     UPPER_BOUND_C : in  std_logic_vector(5 downto 0) := "101110";
00058     LOWER_BOUND_C : in  std_logic_vector(5 downto 0) := "010000";
00059     IRENA1        : in  std_logic_vector (7 downto 0);
00060     EWA1          : in  std_logic_vector (7 downto 0);
00061     HEINZ1        : in  std_logic_vector (7 downto 0);
00062     ANDREJ1       : in  std_logic_vector (7 downto 0);
00063     MARKO1        : in  std_logic_vector (7 downto 0);
00064     WILLIAM1      : in  std_logic_vector (7 downto 0);
00065     HARRIS1       : in  std_logic_vector (7 downto 0);
00066     HELMUT1       : in  std_logic_vector (7 downto 0);
00067     IRENA2        : in  std_logic_vector (7 downto 0);
00068     EWA2          : in  std_logic_vector (7 downto 0);
00069     HEINZ2        : in  std_logic_vector (7 downto 0);
00070     ANDREJ2       : in  std_logic_vector (7 downto 0);
00071     MARKO2        : in  std_logic_vector (7 downto 0);
00072     WILLIAM2      : in  std_logic_vector (7 downto 0);
00073     HARRIS2       : in  std_logic_vector (7 downto 0);
00074     HELMUT2       : in  std_logic_vector (7 downto 0);
00075     S_IRENA1      : in  std_logic;
00076     S_EWA1        : in  std_logic;
00077     S_HEINZ1      : in  std_logic;
00078     S_ANDREJ1     : in  std_logic;
00079     S_MARKO1      : in  std_logic;
00080     S_WILLIAM1    : in  std_logic;
00081     S_HARRIS1     : in  std_logic;
00082     S_HELMUT1     : in  std_logic;
00083     S_IRENA2      : in  std_logic;
00084     S_EWA2        : in  std_logic;
00085     S_HEINZ2      : in  std_logic;
00086     S_ANDREJ2     : in  std_logic;
00087     S_MARKO2      : in  std_logic;
00088     S_WILLIAM2    : in  std_logic;
00089     S_HARRIS2     : in  std_logic;
00090     S_HELMUT2     : in  std_logic;
00091     VLD           : out std_logic;
00092     HITCH_11      : out std_logic_vector(2 downto 0);
00093     HITCH_12      : out std_logic_vector(2 downto 0);
00094     HITCH_21      : out std_logic_vector(2 downto 0);
00095     HITCH_22      : out std_logic_vector(2 downto 0);
00096     DELTA_TOUT    : out std_logic_vector (6 downto 0)
00097     );
00098 end delta_t_ac_top;
00099 
00100 -------------------------------------------------------------------------------
00101 --*************************** Body 1 *****************************
00102 -------------------------------------------------------------------------------
00103 
00104 
00105 
00106 
00107 
00108 
00109 
00110 
00111 architecture one_to_one of delta_t_ac_top is
00112 
00113 --*************************** Signal Declarations *****************************
00114   signal clk5x        : std_logic                    := '0';
00115   signal hit_irena1   : std_logic                    := '0';
00116   signal hit_ewa1     : std_logic                    := '0';
00117   signal hit_heinz1   : std_logic                    := '0';
00118   signal hit_andrej1  : std_logic                    := '0';
00119   signal hit_marko1   : std_logic                    := '0';
00120   signal hit_william1 : std_logic                    := '0';
00121   signal hit_harris1  : std_logic                    := '0';
00122   signal hit_helmut1  : std_logic                    := '0';
00123   signal hit_irena    : std_logic                    := '0';
00124   signal hit_ewa      : std_logic                    := '0';
00125   signal hit_heinz    : std_logic                    := '0';
00126   signal hit_andrej   : std_logic                    := '0';
00127   signal hit_marko    : std_logic                    := '0';
00128   signal hit_william  : std_logic                    := '0';
00129   signal hit_harris   : std_logic                    := '0';
00130   signal hit_helmut   : std_logic                    := '0';
00131   signal hit_irena2   : std_logic                    := '0';
00132   signal hit_ewa2     : std_logic                    := '0';
00133   signal hit_heinz2   : std_logic                    := '0';
00134   signal hit_andrej2  : std_logic                    := '0';
00135   signal hit_marko2   : std_logic                    := '0';
00136   signal hit_william2 : std_logic                    := '0';
00137   signal hit_harris2  : std_logic                    := '0';
00138   signal hit_helmut2  : std_logic                    := '0';
00139   signal coin_flag_i  : std_logic                    := '0';
00140   signal coin_flaga_i : std_logic                    := '0';
00141   signal coin_flagc_i : std_logic                    := '0';
00142   signal hitch11_i    : std_logic_vector(2 downto 0) := "000";
00143   signal hitch21_i    : std_logic_vector(2 downto 0) := "000";
00144   signal side_a_i     : std_logic_vector(5 downto 0) := (others => '0');
00145   signal side_c_i     : std_logic_vector(5 downto 0) := (others => '0');
00146   signal side_a1_i    : std_logic_vector(6 downto 0) := (others => '0');
00147   signal side_c1_i    : std_logic_vector(6 downto 0) := (others => '0');
00148   signal irena_int    : std_logic_vector(5 downto 0) := (others => '0');
00149   signal ewa_int      : std_logic_vector(5 downto 0) := (others => '0');
00150   signal heinz_int    : std_logic_vector(5 downto 0) := (others => '0');
00151   signal andrej_int   : std_logic_vector(5 downto 0) := (others => '0');
00152   signal marko_int    : std_logic_vector(5 downto 0) := (others => '0');
00153   signal william_int  : std_logic_vector(5 downto 0) := (others => '0');
00154   signal harris_int   : std_logic_vector(5 downto 0) := (others => '0');
00155   signal helmut_int   : std_logic_vector(5 downto 0) := (others => '0');
00156   signal irena1_i     : std_logic_vector(7 downto 0) := (others => '0');
00157   signal ewa1_i       : std_logic_vector(7 downto 0) := (others => '0');
00158   signal heinz1_i     : std_logic_vector(7 downto 0) := (others => '0');
00159   signal andrej1_i    : std_logic_vector(7 downto 0) := (others => '0');
00160   signal marko1_i     : std_logic_vector(7 downto 0) := (others => '0');
00161   signal william1_i   : std_logic_vector(7 downto 0) := (others => '0');
00162   signal harris1_i    : std_logic_vector(7 downto 0) := (others => '0');
00163   signal helmut1_i    : std_logic_vector(7 downto 0) := (others => '0');
00164   signal irena1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00165   signal ewa1_xy      : std_logic_vector(5 downto 0) := (others => '0');
00166   signal heinz1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00167   signal andrej1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00168   signal marko1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00169   signal william1_xy  : std_logic_vector(5 downto 0) := (others => '0');
00170   signal harris1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00171   signal helmut1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00172   signal irena2_i     : std_logic_vector(7 downto 0) := (others => '0');
00173   signal ewa2_i       : std_logic_vector(7 downto 0) := (others => '0');
00174   signal heinz2_i     : std_logic_vector(7 downto 0) := (others => '0');
00175   signal andrej2_i    : std_logic_vector(7 downto 0) := (others => '0');
00176   signal marko2_i     : std_logic_vector(7 downto 0) := (others => '0');
00177   signal william2_i   : std_logic_vector(7 downto 0) := (others => '0');
00178   signal harris2_i    : std_logic_vector(7 downto 0) := (others => '0');
00179   signal helmut2_i    : std_logic_vector(7 downto 0) := (others => '0');
00180   signal irena2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00181   signal ewa2_xy      : std_logic_vector(5 downto 0) := (others => '0');
00182   signal heinz2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00183   signal andrej2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00184   signal marko2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00185   signal william2_xy  : std_logic_vector(5 downto 0) := (others => '0');
00186   signal harris2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00187   signal helmut2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00188   signal result_i     : std_logic_vector(6 downto 0) := (others => '0');
00189 
00190 --************************** Component Declarations ***************************
00191 
00192   component ADDSUB48
00193     port(
00194       CLK    : in  std_logic;
00195       RST    : in  std_logic;
00196       C_IN   : in  std_logic_vector(6 downto 0);
00197       PC_IN  : in  std_logic_vector(6 downto 0);
00198       RESULT : out std_logic_vector(6 downto 0)
00199       );
00200   end component;
00201 
00202 
00203   component comparator4
00204     port(
00205       CLK : in  std_logic;
00206       SA  : in  std_logic;
00207       SB  : in  std_logic;
00208       SC  : in  std_logic;
00209       SD  : in  std_logic;
00210       A   : in  std_logic_vector(5 downto 0);
00211       B   : in  std_logic_vector(5 downto 0);
00212       C   : in  std_logic_vector(5 downto 0);
00213       D   : in  std_logic_vector(5 downto 0);
00214       SY  : out std_logic;
00215       Y   : out std_logic_vector(5 downto 0)
00216       );
00217   end component;
00218 
00219 --*************************************************************************
00220 --*                               main code
00221 --*************************************************************************
00222 begin
00223 
00224   clk5x <= CLK;
00225 
00226 
00227   select_for_each : process(clk5x)
00228   begin
00229     if clk5x'event and clk5x = '1' then
00230       
00231       hit_irena <= '1';
00232       if S_irena1 = '1' then
00233         irena_int <= irena1(5 downto 0);
00234       elsif S_irena2 = '1' then
00235         irena_int <= irena2(5 downto 0);
00236       else
00237         irena_int <= (others => '0');
00238         hit_irena <= '0';
00239       end if;
00240 
00241       hit_ewa <= '1';
00242       if S_ewa1 = '1' then
00243         ewa_int <= ewa1(5 downto 0);
00244       elsif S_ewa2 = '1' then
00245         ewa_int <= ewa2(5 downto 0);
00246       else
00247         ewa_int <= (others => '0');
00248         hit_ewa <= '0';
00249       end if;
00250 
00251       hit_heinz <= '1';
00252       if S_heinz1 = '1' then
00253         heinz_int <= heinz1(5 downto 0);
00254       elsif S_heinz2 = '1' then
00255         heinz_int <= heinz2(5 downto 0);
00256       else
00257         heinz_int <= (others => '0');
00258         hit_heinz <= '0';
00259       end if;
00260 
00261       hit_andrej <= '1';
00262       if S_andrej1 = '1' then
00263         andrej_int <= andrej1(5 downto 0);
00264       elsif S_andrej2 = '1' then
00265         andrej_int <= andrej2(5 downto 0);
00266       else
00267         andrej_int <= (others => '0');
00268         hit_andrej <= '0';
00269       end if;
00270 
00271       hit_marko <= '1';
00272       if S_marko1 = '1' then
00273         marko_int <= marko1(5 downto 0);
00274       elsif S_marko2 = '1' then
00275         marko_int <= marko2(5 downto 0);
00276       else
00277         marko_int <= (others => '0');
00278         hit_marko <= '0';
00279       end if;
00280 
00281       hit_william <= '1';
00282       if S_william1 = '1' then
00283         william_int <= william1(5 downto 0);
00284       elsif S_william2 = '1' then
00285         william_int <= william2(5 downto 0);
00286       else
00287         william_int <= (others => '0');
00288         hit_william <= '0';
00289       end if;
00290 
00291       hit_harris <= '1';
00292       if S_harris1 = '1' then
00293         harris_int <= harris1(5 downto 0);
00294       elsif S_harris2 = '1' then
00295         harris_int <= harris2(5 downto 0);
00296       else
00297         harris_int <= (others => '0');
00298         hit_harris <= '0';
00299       end if;
00300 
00301       hit_helmut <= '1';
00302       if S_helmut1 = '1' then
00303         helmut_int <= helmut1(5 downto 0);
00304       elsif S_helmut2 = '1' then
00305         helmut_int <= helmut2(5 downto 0);
00306       else
00307         helmut_int <= (others => '0');
00308         hit_helmut <= '0';
00309       end if;
00310       
00311     end if;
00312   end process;
00313 
00314   SideC : comparator4
00315     port map
00316     (
00317       CLK => clk5x,
00318       SA  => hit_irena,
00319       SB  => hit_ewa ,
00320       SC  => hit_heinz,
00321       SD  => hit_andrej,
00322       A   => irena_int,
00323       B   => ewa_int ,
00324       C   => heinz_int,
00325       D   => andrej_int,
00326       SY  => coin_flagc_i,
00327       Y   => side_c_i
00328       );
00329 
00330   SideA : comparator4
00331     port map
00332     (
00333       CLK => clk5x,
00334       SA  => hit_marko,
00335       SB  => hit_william,
00336       SC  => hit_harris,
00337       SD  => hit_helmut,
00338       A   => marko_int,
00339       B   => william_int,
00340       C   => harris_int,
00341       D   => helmut_int,
00342       SY  => coin_flaga_i,
00343       Y   => side_a_i
00344       );
00345 
00346   side_a1_i   <= '0' & side_a_i;
00347   side_c1_i   <= '0' & side_c_i;
00348   coin_flag_i <= coin_flaga_i and coin_flagc_i;
00349   hitch11_i   <= "000" when coin_flaga_i = '0' else
00350                  "001" when side_a_i = marko_int else
00351                  "010" when side_a_i = william_int else
00352                  "011" when side_a_i = harris_int else
00353                  "100" when side_a_i = helmut_int else
00354                  "000";
00355   hitch21_i <= "000" when coin_flagc_i = '0' else
00356                "001" when side_c_i = irena_int else
00357                "010" when side_c_i = ewa_int else
00358                "011" when side_c_i = heinz_int else
00359                "100" when side_c_i = andrej_int else
00360                "000";
00361 
00362   delta : ADDSUB48
00363     port map
00364     (
00365       CLK     => clk5x,
00366       RST     => '0' ,
00367       C_IN    => side_a1_i ,
00368       PC_IN  => side_c1_i ,
00369       RESULT  => result_i
00370       );
00371 
00372   DELTA_TOUT <= result_i;
00373   VLD        <= coin_flag_i when rising_edge(clk5x);
00374   HITCH_11   <= hitch11_i   when rising_edge(clk5x);
00375   HITCH_21   <= hitch21_i   when rising_edge(clk5x);
00376   HITCH_12   <= "000";
00377   HITCH_22   <= "000";
00378   
00379 end one_to_one;
00380 
00381 -------------------------------------------------------------------------------
00382 --*************************** Body 2 *****************************
00383 -------------------------------------------------------------------------------
00384 
00385 
00386 
00387 
00388 
00389 
00390 
00391 
00392 architecture two_to_two of delta_t_ac_top is
00393 
00394 --*************************** Signal Declarations *****************************
00395   signal cnt1, cnt2   : integer range 0 to 4         := 0;
00396   signal clk5x        : std_logic                    := '0';
00397   signal hit_irena1   : std_logic                    := '0';
00398   signal hit_ewa1     : std_logic                    := '0';
00399   signal hit_heinz1   : std_logic                    := '0';
00400   signal hit_andrej1  : std_logic                    := '0';
00401   signal hit_marko1   : std_logic                    := '0';
00402   signal hit_william1 : std_logic                    := '0';
00403   signal hit_harris1  : std_logic                    := '0';
00404   signal hit_helmut1  : std_logic                    := '0';
00405   signal hit_irena    : std_logic                    := '0';
00406   signal hit_ewa      : std_logic                    := '0';
00407   signal hit_heinz    : std_logic                    := '0';
00408   signal hit_andrej   : std_logic                    := '0';
00409   signal hit_marko    : std_logic                    := '0';
00410   signal hit_william  : std_logic                    := '0';
00411   signal hit_harris   : std_logic                    := '0';
00412   signal hit_helmut   : std_logic                    := '0';
00413   signal hit_irena2   : std_logic                    := '0';
00414   signal hit_ewa2     : std_logic                    := '0';
00415   signal hit_heinz2   : std_logic                    := '0';
00416   signal hit_andrej2  : std_logic                    := '0';
00417   signal hit_marko2   : std_logic                    := '0';
00418   signal hit_william2 : std_logic                    := '0';
00419   signal hit_harris2  : std_logic                    := '0';
00420   signal hit_helmut2  : std_logic                    := '0';
00421   signal coin_flag_i  : std_logic                    := '0';
00422   signal two1         : std_logic                    := '0';
00423   signal two2         : std_logic                    := '0';
00424   signal side_a_i     : std_logic_vector(5 downto 0) := (others => '0');
00425   signal side_c_i     : std_logic_vector(5 downto 0) := (others => '0');
00426   signal side_a1_i    : std_logic_vector(6 downto 0) := (others => '0');
00427   signal side_c1_i    : std_logic_vector(6 downto 0) := (others => '0');
00428   signal irena_int    : std_logic_vector(5 downto 0) := (others => '0');
00429   signal ewa_int      : std_logic_vector(5 downto 0) := (others => '0');
00430   signal heinz_int    : std_logic_vector(5 downto 0) := (others => '0');
00431   signal andrej_int   : std_logic_vector(5 downto 0) := (others => '0');
00432   signal marko_int    : std_logic_vector(5 downto 0) := (others => '0');
00433   signal william_int  : std_logic_vector(5 downto 0) := (others => '0');
00434   signal harris_int   : std_logic_vector(5 downto 0) := (others => '0');
00435   signal helmut_int   : std_logic_vector(5 downto 0) := (others => '0');
00436   signal irena1_i     : std_logic_vector(7 downto 0) := (others => '0');
00437   signal ewa1_i       : std_logic_vector(7 downto 0) := (others => '0');
00438   signal heinz1_i     : std_logic_vector(7 downto 0) := (others => '0');
00439   signal andrej1_i    : std_logic_vector(7 downto 0) := (others => '0');
00440   signal marko1_i     : std_logic_vector(7 downto 0) := (others => '0');
00441   signal william1_i   : std_logic_vector(7 downto 0) := (others => '0');
00442   signal harris1_i    : std_logic_vector(7 downto 0) := (others => '0');
00443   signal helmut1_i    : std_logic_vector(7 downto 0) := (others => '0');
00444   signal irena1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00445   signal ewa1_bc      : std_logic_vector(5 downto 0) := (others => '0');
00446   signal heinz1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00447   signal andrej1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00448   signal marko1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00449   signal william1_bc  : std_logic_vector(5 downto 0) := (others => '0');
00450   signal harris1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00451   signal helmut1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00452   signal irena1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00453   signal ewa1_xy      : std_logic_vector(5 downto 0) := (others => '0');
00454   signal heinz1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00455   signal andrej1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00456   signal marko1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00457   signal william1_xy  : std_logic_vector(5 downto 0) := (others => '0');
00458   signal harris1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00459   signal helmut1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00460   signal irena2_i     : std_logic_vector(7 downto 0) := (others => '0');
00461   signal ewa2_i       : std_logic_vector(7 downto 0) := (others => '0');
00462   signal heinz2_i     : std_logic_vector(7 downto 0) := (others => '0');
00463   signal andrej2_i    : std_logic_vector(7 downto 0) := (others => '0');
00464   signal marko2_i     : std_logic_vector(7 downto 0) := (others => '0');
00465   signal william2_i   : std_logic_vector(7 downto 0) := (others => '0');
00466   signal harris2_i    : std_logic_vector(7 downto 0) := (others => '0');
00467   signal helmut2_i    : std_logic_vector(7 downto 0) := (others => '0');
00468   signal irena2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00469   signal ewa2_bc      : std_logic_vector(5 downto 0) := (others => '0');
00470   signal heinz2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00471   signal andrej2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00472   signal marko2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00473   signal william2_bc  : std_logic_vector(5 downto 0) := (others => '0');
00474   signal harris2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00475   signal helmut2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00476   signal irena2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00477   signal ewa2_xy      : std_logic_vector(5 downto 0) := (others => '0');
00478   signal heinz2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00479   signal andrej2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00480   signal marko2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00481   signal william2_xy  : std_logic_vector(5 downto 0) := (others => '0');
00482   signal harris2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00483   signal helmut2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00484   signal result_i     : std_logic_vector(6 downto 0) := (others => '0');
00485   signal temp1, temp2 : std_logic_vector(3 downto 0) := (others => '0');
00486   
00487 begin  -- two_to_two
00488 
00489   clk5x      <= CLK;
00490   DELTA_TOUT <= (others => '0');
00491 
00492   hit_irena   <= S_irena1 or S_irena2;
00493   hit_ewa     <= S_ewa1 or S_ewa2;
00494   hit_andrej  <= S_andrej1 or S_andrej2;
00495   hit_heinz   <= S_heinz1 or S_heinz2;
00496   hit_helmut  <= S_helmut1 or S_helmut2;
00497   hit_harris  <= S_harris1 or S_harris2;
00498   hit_william <= S_william1 or S_william2;
00499   hit_marko   <= S_marko1 or S_marko2;
00500 
00501   temp1 <= hit_irena & hit_ewa & hit_andrej & hit_andrej;
00502   temp2 <= hit_marko & hit_william & hit_harris & hit_helmut;
00503   with temp1 select
00504     two1 <=
00505     '1' when "0011" | "0101" | "0110" | "1001" | "1010" | "1100",
00506     '0' when others;
00507   with temp2 select
00508     two2 <=
00509     '1' when "0011" | "0101" | "0110" | "1001" | "1010" | "1100",
00510     '0' when others;
00511 
00512   set_hit_flag : process (clk5x)
00513   begin  -- process set_hit_flag
00514     if clk5x'event and clk5x = '1' then  -- rising clock edge
00515       if (two1 and two2) = '1' then
00516         VLD <= '1';
00517       else
00518         VLD <= '0';
00519       end if;
00520     end if;
00521   end process set_hit_flag;
00522 
00523   HITCH_11 <= "000";
00524   HITCH_21 <= "000";
00525   HITCH_12 <= "000";
00526   HITCH_22 <= "000";
00527 
00528 end two_to_two;
00529 
00530 -------------------------------------------------------------------------------
00531 --*************************** Body 3 *****************************
00532 -------------------------------------------------------------------------------
00533 
00534 
00535 
00536 
00537 
00538 
00539 architecture single of delta_t_ac_top is
00540 
00541 --*************************** Signal Declarations *****************************
00542   signal clk5x        : std_logic                    := '0';
00543   signal hit_irena1   : std_logic                    := '0';
00544   signal hit_ewa1     : std_logic                    := '0';
00545   signal hit_heinz1   : std_logic                    := '0';
00546   signal hit_andrej1  : std_logic                    := '0';
00547   signal hit_marko1   : std_logic                    := '0';
00548   signal hit_william1 : std_logic                    := '0';
00549   signal hit_harris1  : std_logic                    := '0';
00550   signal hit_helmut1  : std_logic                    := '0';
00551   signal hit_irena    : std_logic                    := '0';
00552   signal hit_ewa      : std_logic                    := '0';
00553   signal hit_heinz    : std_logic                    := '0';
00554   signal hit_andrej   : std_logic                    := '0';
00555   signal hit_marko    : std_logic                    := '0';
00556   signal hit_william  : std_logic                    := '0';
00557   signal hit_harris   : std_logic                    := '0';
00558   signal hit_helmut   : std_logic                    := '0';
00559   signal hit_irena2   : std_logic                    := '0';
00560   signal hit_ewa2     : std_logic                    := '0';
00561   signal hit_heinz2   : std_logic                    := '0';
00562   signal hit_andrej2  : std_logic                    := '0';
00563   signal hit_marko2   : std_logic                    := '0';
00564   signal hit_william2 : std_logic                    := '0';
00565   signal hit_harris2  : std_logic                    := '0';
00566   signal hit_helmut2  : std_logic                    := '0';
00567   signal coin_flag_i  : std_logic                    := '0';
00568   signal hit_a, hit_b : std_logic                    := '0';
00569   signal side_a_i     : std_logic_vector(5 downto 0) := (others => '0');
00570   signal side_c_i     : std_logic_vector(5 downto 0) := (others => '0');
00571   signal side_a1_i    : std_logic_vector(6 downto 0) := (others => '0');
00572   signal side_c1_i    : std_logic_vector(6 downto 0) := (others => '0');
00573   signal irena_int    : std_logic_vector(5 downto 0) := (others => '0');
00574   signal ewa_int      : std_logic_vector(5 downto 0) := (others => '0');
00575   signal heinz_int    : std_logic_vector(5 downto 0) := (others => '0');
00576   signal andrej_int   : std_logic_vector(5 downto 0) := (others => '0');
00577   signal marko_int    : std_logic_vector(5 downto 0) := (others => '0');
00578   signal william_int  : std_logic_vector(5 downto 0) := (others => '0');
00579   signal harris_int   : std_logic_vector(5 downto 0) := (others => '0');
00580   signal helmut_int   : std_logic_vector(5 downto 0) := (others => '0');
00581   signal irena1_i     : std_logic_vector(7 downto 0) := (others => '0');
00582   signal ewa1_i       : std_logic_vector(7 downto 0) := (others => '0');
00583   signal heinz1_i     : std_logic_vector(7 downto 0) := (others => '0');
00584   signal andrej1_i    : std_logic_vector(7 downto 0) := (others => '0');
00585   signal marko1_i     : std_logic_vector(7 downto 0) := (others => '0');
00586   signal william1_i   : std_logic_vector(7 downto 0) := (others => '0');
00587   signal harris1_i    : std_logic_vector(7 downto 0) := (others => '0');
00588   signal helmut1_i    : std_logic_vector(7 downto 0) := (others => '0');
00589   signal irena1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00590   signal ewa1_bc      : std_logic_vector(5 downto 0) := (others => '0');
00591   signal heinz1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00592   signal andrej1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00593   signal marko1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00594   signal william1_bc  : std_logic_vector(5 downto 0) := (others => '0');
00595   signal harris1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00596   signal helmut1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00597   signal irena1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00598   signal ewa1_xy      : std_logic_vector(5 downto 0) := (others => '0');
00599   signal heinz1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00600   signal andrej1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00601   signal marko1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00602   signal william1_xy  : std_logic_vector(5 downto 0) := (others => '0');
00603   signal harris1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00604   signal helmut1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00605   signal irena2_i     : std_logic_vector(7 downto 0) := (others => '0');
00606   signal ewa2_i       : std_logic_vector(7 downto 0) := (others => '0');
00607   signal heinz2_i     : std_logic_vector(7 downto 0) := (others => '0');
00608   signal andrej2_i    : std_logic_vector(7 downto 0) := (others => '0');
00609   signal marko2_i     : std_logic_vector(7 downto 0) := (others => '0');
00610   signal william2_i   : std_logic_vector(7 downto 0) := (others => '0');
00611   signal harris2_i    : std_logic_vector(7 downto 0) := (others => '0');
00612   signal helmut2_i    : std_logic_vector(7 downto 0) := (others => '0');
00613   signal irena2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00614   signal ewa2_bc      : std_logic_vector(5 downto 0) := (others => '0');
00615   signal heinz2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00616   signal andrej2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00617   signal marko2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00618   signal william2_bc  : std_logic_vector(5 downto 0) := (others => '0');
00619   signal harris2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00620   signal helmut2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00621   signal irena2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00622   signal ewa2_xy      : std_logic_vector(5 downto 0) := (others => '0');
00623   signal heinz2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00624   signal andrej2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00625   signal marko2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00626   signal william2_xy  : std_logic_vector(5 downto 0) := (others => '0');
00627   signal harris2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00628   signal helmut2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00629   signal result_i     : std_logic_vector(6 downto 0) := (others => '0');
00630   
00631 begin  -- single
00632   
00633   clk5x      <= CLK;
00634   DELTA_TOUT <= (others => '0');
00635 
00636   hit_a <= S_irena2 or S_irena1 or S_ewa2 or S_ewa1 or
00637            S_andrej2 or S_andrej1 or S_heinz2 or S_heinz1 when rising_edge(clk5x);
00638   hit_b <= S_helmut2 or S_helmut1 or S_harris2 or S_harris1 or
00639            S_william2 or S_william1 or S_marko2 or S_marko1 when rising_edge(clk5x);
00640   VLD      <= hit_a or hit_b when rising_edge(clk5x);
00641   HITCH_11 <= "000";
00642   HITCH_21 <= "000";
00643   HITCH_12 <= "000";
00644   HITCH_22 <= "000";
00645 
00646 end single;
00647 
00648 -------------------------------------------------------------------------------
00649 --*************************** Body 4 *****************************
00650 -------------------------------------------------------------------------------
00651 
00652 
00653 
00654 
00655 
00656 
00657 architecture double of delta_t_ac_top is
00658 
00659 --*************************** Signal Declarations *****************************
00660   signal ones         : integer range 0 to 8         := 0;
00661   signal clk5x        : std_logic                    := '0';
00662   signal hit_irena1   : std_logic                    := '0';
00663   signal hit_ewa1     : std_logic                    := '0';
00664   signal hit_heinz1   : std_logic                    := '0';
00665   signal hit_andrej1  : std_logic                    := '0';
00666   signal hit_marko1   : std_logic                    := '0';
00667   signal hit_william1 : std_logic                    := '0';
00668   signal hit_harris1  : std_logic                    := '0';
00669   signal hit_helmut1  : std_logic                    := '0';
00670   signal hit_irena    : std_logic                    := '0';
00671   signal hit_ewa      : std_logic                    := '0';
00672   signal hit_heinz    : std_logic                    := '0';
00673   signal hit_andrej   : std_logic                    := '0';
00674   signal hit_marko    : std_logic                    := '0';
00675   signal hit_william  : std_logic                    := '0';
00676   signal hit_harris   : std_logic                    := '0';
00677   signal hit_helmut   : std_logic                    := '0';
00678   signal hit_irena2   : std_logic                    := '0';
00679   signal hit_ewa2     : std_logic                    := '0';
00680   signal hit_heinz2   : std_logic                    := '0';
00681   signal hit_andrej2  : std_logic                    := '0';
00682   signal hit_marko2   : std_logic                    := '0';
00683   signal hit_william2 : std_logic                    := '0';
00684   signal hit_harris2  : std_logic                    := '0';
00685   signal hit_helmut2  : std_logic                    := '0';
00686   signal coin_flag_i  : std_logic                    := '0';
00687   signal one1         : std_logic                    := '0';
00688   signal one2         : std_logic                    := '0';
00689   signal two1         : std_logic                    := '0';
00690   signal two2         : std_logic                    := '0';
00691   signal side_a_i     : std_logic_vector(5 downto 0) := (others => '0');
00692   signal side_c_i     : std_logic_vector(5 downto 0) := (others => '0');
00693   signal side_a1_i    : std_logic_vector(6 downto 0) := (others => '0');
00694   signal side_c1_i    : std_logic_vector(6 downto 0) := (others => '0');
00695   signal irena_int    : std_logic_vector(5 downto 0) := (others => '0');
00696   signal ewa_int      : std_logic_vector(5 downto 0) := (others => '0');
00697   signal heinz_int    : std_logic_vector(5 downto 0) := (others => '0');
00698   signal andrej_int   : std_logic_vector(5 downto 0) := (others => '0');
00699   signal marko_int    : std_logic_vector(5 downto 0) := (others => '0');
00700   signal william_int  : std_logic_vector(5 downto 0) := (others => '0');
00701   signal harris_int   : std_logic_vector(5 downto 0) := (others => '0');
00702   signal helmut_int   : std_logic_vector(5 downto 0) := (others => '0');
00703   signal irena1_i     : std_logic_vector(7 downto 0) := (others => '0');
00704   signal ewa1_i       : std_logic_vector(7 downto 0) := (others => '0');
00705   signal heinz1_i     : std_logic_vector(7 downto 0) := (others => '0');
00706   signal andrej1_i    : std_logic_vector(7 downto 0) := (others => '0');
00707   signal marko1_i     : std_logic_vector(7 downto 0) := (others => '0');
00708   signal william1_i   : std_logic_vector(7 downto 0) := (others => '0');
00709   signal harris1_i    : std_logic_vector(7 downto 0) := (others => '0');
00710   signal helmut1_i    : std_logic_vector(7 downto 0) := (others => '0');
00711   signal irena1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00712   signal ewa1_bc      : std_logic_vector(5 downto 0) := (others => '0');
00713   signal heinz1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00714   signal andrej1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00715   signal marko1_bc    : std_logic_vector(5 downto 0) := (others => '0');
00716   signal william1_bc  : std_logic_vector(5 downto 0) := (others => '0');
00717   signal harris1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00718   signal helmut1_bc   : std_logic_vector(5 downto 0) := (others => '0');
00719   signal irena1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00720   signal ewa1_xy      : std_logic_vector(5 downto 0) := (others => '0');
00721   signal heinz1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00722   signal andrej1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00723   signal marko1_xy    : std_logic_vector(5 downto 0) := (others => '0');
00724   signal william1_xy  : std_logic_vector(5 downto 0) := (others => '0');
00725   signal harris1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00726   signal helmut1_xy   : std_logic_vector(5 downto 0) := (others => '0');
00727   signal irena2_i     : std_logic_vector(7 downto 0) := (others => '0');
00728   signal ewa2_i       : std_logic_vector(7 downto 0) := (others => '0');
00729   signal heinz2_i     : std_logic_vector(7 downto 0) := (others => '0');
00730   signal andrej2_i    : std_logic_vector(7 downto 0) := (others => '0');
00731   signal marko2_i     : std_logic_vector(7 downto 0) := (others => '0');
00732   signal william2_i   : std_logic_vector(7 downto 0) := (others => '0');
00733   signal harris2_i    : std_logic_vector(7 downto 0) := (others => '0');
00734   signal helmut2_i    : std_logic_vector(7 downto 0) := (others => '0');
00735   signal irena2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00736   signal ewa2_bc      : std_logic_vector(5 downto 0) := (others => '0');
00737   signal heinz2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00738   signal andrej2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00739   signal marko2_bc    : std_logic_vector(5 downto 0) := (others => '0');
00740   signal william2_bc  : std_logic_vector(5 downto 0) := (others => '0');
00741   signal harris2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00742   signal helmut2_bc   : std_logic_vector(5 downto 0) := (others => '0');
00743   signal irena2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00744   signal ewa2_xy      : std_logic_vector(5 downto 0) := (others => '0');
00745   signal heinz2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00746   signal andrej2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00747   signal marko2_xy    : std_logic_vector(5 downto 0) := (others => '0');
00748   signal william2_xy  : std_logic_vector(5 downto 0) := (others => '0');
00749   signal harris2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00750   signal helmut2_xy   : std_logic_vector(5 downto 0) := (others => '0');
00751   signal result_i     : std_logic_vector(6 downto 0) := (others => '0');
00752   signal temp1, temp2 : std_logic_vector(3 downto 0) := (others => '0');
00753 
00754 begin  -- double
00755 
00756   clk5x      <= CLK;
00757   DELTA_TOUT <= (others => '0');
00758 
00759   hit_irena   <= S_irena1 or S_irena2;
00760   hit_ewa     <= S_ewa1 or S_ewa2;
00761   hit_andrej  <= S_andrej1 or S_andrej2;
00762   hit_heinz   <= S_heinz1 or S_heinz2;
00763   hit_helmut  <= S_helmut1 or S_helmut2;
00764   hit_harris  <= S_harris1 or S_harris2;
00765   hit_william <= S_william1 or S_william2;
00766   hit_marko   <= S_marko1 or S_marko2;
00767 
00768   temp1 <= hit_irena & hit_ewa & hit_andrej & hit_andrej;
00769   temp2 <= hit_marko & hit_william & hit_harris & hit_helmut;
00770   with temp1 select
00771     one1 <=
00772     '1' when "0001" | "0010" | "0100" | "1000",
00773     '0' when others;
00774   with temp2 select
00775     one2 <=
00776     '1' when "0001" | "0010" | "0100" | "1000",
00777     '0' when others;
00778   with temp1 select
00779     two1 <=
00780     '1' when "0011" | "0101" | "0110" | "1001" | "1010" | "1100",
00781     '0' when others;
00782   with temp2 select
00783     two2 <=
00784     '1' when "0011" | "0101" | "0110" | "1001" | "1010" | "1100",
00785     '0' when others;
00786 
00787   set_hit_flag : process (clk5x)
00788   begin  -- process set_hit_flag
00789     if clk5x'event and clk5x = '1' then  -- rising clock edge
00790       if ((two1 or two2) = '1') or ((one1 and one2) = '1') then
00791         VLD <= '1';
00792       else
00793         VLD <= '0';
00794       end if;
00795     end if;
00796   end process set_hit_flag;
00797 
00798   HITCH_11 <= "000";
00799   HITCH_21 <= "000";
00800   HITCH_12 <= "000";
00801   HITCH_22 <= "000";
00802 
00803 end double;