incrementer.vhd

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--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/coin/incrementer.vhd,v $
--*  $Revision: 1.3.2.3 $                                          *
--*  $Name: dev $                                                 *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:42 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;




entity incrementer is
  
  port (
    CLK      : in  std_logic;
    RES      : in  std_logic;
    INC_1    : in  std_logic;
    INC_2    : in  std_logic;
    READ_OUT : in  std_logic;
    VALUE    : out std_logic_vector(31 downto 0)
    );

end incrementer;





architecture incrementer_arc of incrementer is

  signal val_i : std_logic_vector(31 downto 0) := (others => '0');

begin  -- incrementer_arc

  VALUE <= val_i;
  

  counter : process (CLK)
    variable cnt : integer := 0;
  begin  -- process counter
    if CLK'event and CLK = '1' then     -- rising clock edge      
      if RES = '1' then
        cnt := 0;
        val_i <= (others => '0');
      else
        
        if (INC_1 and INC_2) = '1' then
          cnt := cnt + 3;
        elsif INC_2 = '1' then
          cnt := cnt + 2;
        elsif INC_1 = '1' then
          cnt := cnt + 1;
        else
          cnt := cnt;
        end if;

        if READ_OUT = '1' then
          val_i <= std_logic_vector(to_unsigned(cnt,32));
          cnt := 0;
        else
          val_i <= val_i;
        end if;
        
      end if;
    end if;
  end process counter;

end incrementer_arc;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012