ddr2_mem_infrastructure_iobs_0.vhd

Go to the documentation of this file.

--**************************************************************
--*                                                            *
--*     The source code for the ATLAS BCM "AAA" FPGA is made   *
--*     available via the GNU General Public License (GPL)     *
--*     unless otherwise stated below.                         *
--*                                                            *
--*     In case of problems/questions/bug reports etc. please  *
--*     contact michael.niegl@cern.ch                          *
--*                                                            *
--**************************************************************

--**************************************************************
--*                                                            *
--*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr2/ddr2_mem_infrastructure_iobs_0.vhd,v $
--*  $Revision: 1.3.2.4 $                                      *
--*  $Name: dev $                                              *
--*  $Author: mniegl $                                         *
--*  $Date: 2008/11/03 17:57:44 $                              *


--*                                                            *
--**************************************************************

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;
use work.ddr2_mem_parameters_0.all;
-- pragma translate_off

library unisim;

use unisim.vcomponents.all;
-- pragma translate_on




entity ddr2_mem_infrastructure_iobs_0 is
  port (
    CLK      : in  std_logic;
    DDR_CK   : out std_logic;
    DDR_CK_N : out std_logic
    );
end entity;


architecture arc_infrastructure_iobs of ddr2_mem_infrastructure_iobs_0 is


  component OBUFDS
    port (
      I  : in  std_logic;
      O  : out std_logic;
      OB : out std_logic
      );
  end component;


  component ODDR
    generic(
      DDR_CLK_EDGE : string := "OPPOSITE_EDGE";
      SRTYPE       : string := "SYNC"
      );
    port(
      Q  : out std_ulogic;
      C  : in  std_ulogic;
      CE : in  std_ulogic;
      D1 : in  std_ulogic;
      D2 : in  std_ulogic;
      R  : in  std_ulogic;
      S  : in  std_ulogic
      );
  end component;

  signal DDR_CK_q   : std_logic;
  signal DDR_CK_N_q : std_logic_vector((clk_width-1) downto 0);
  signal vcc        : std_logic;
  signal gnd        : std_logic;

begin
  
  vcc <= '1';
  gnd <= '0';

  oddr_clk0 : ODDR
    generic map(
      DDR_CLK_EDGE => "OPPOSITE_EDGE",
      SRTYPE       => "SYNC"
      )
    port map(
      Q  => DDR_CK_q,
      C  => CLK ,
      CE => vcc ,
      D1 => gnd ,
      D2 => vcc ,
      R  => gnd ,
      S  => gnd 
      );

  OBUFDS0 : OBUFDS
    port map (
      I  => DDR_CK_q,
      O  => DDR_CK ,
      OB => DDR_CK_N
      );

end arc_infrastructure_iobs;

---

Author: M.Niegl

Generated on Tue Nov 4 00:47:04 2008 for BCM-AAA by  1.5.7.1-20081012