BCM-AAA: mem_interface_top.vhd Source File

00001 --**************************************************************
00002 --*                                                            *
00003 --*     The source code for the ATLAS BCM "AAA" FPGA is made   *
00004 --*     available via the GNU General Public License (GPL)     *
00005 --*     unless otherwise stated below.                         *
00006 --*                                                            *
00007 --*     In case of problems/questions/bug reports etc. please  *
00008 --*     contact michael.niegl@cern.ch                          *
00009 --*                                                            *
00010 --**************************************************************
00011 
00012 --**************************************************************
00013 --*                                                            *
00014 --*  $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/mem_interface_top.vhd,v $                                                  *
00015 --*  $Revision: 1.4.2.3 $                                                *
00016 --*  $Name: dev $                                                    *
00017 --*  $Author: mniegl $                                                  *
00018 --*  $Date: 2008/11/03 17:57:43 $                                                    *
00019 --*                                                            *
00020 --**************************************************************
00021 -------------------------------------------------------------------------------
00022 -- Copyright (c) 2005 Xilinx, Inc.
00023 -- This design is confidential and proprietary of Xilinx, All Rights Reserved.
00024 -------------------------------------------------------------------------------
00025 --   ____  ____
00026 --  /   /\/   /
00027 -- /___/  \  / Vendor: Xilinx
00028 -- \   \   \/ Version: 1.6
00029 --  \   \ Application : MIG
00030 --  /   / Filename: mem_interface_top.vhd
00031 -- /___/   /\ Date Last Modified:  Wed Jun 1 2005
00032 -- \   \  /  \Date Created: Mon May 2 2005
00033 --  \___\/\___\
00034 -- Device: Virtex-4
00035 -- Design Name: DDR1_SDRAM
00036 -- Description: It is the top most module which interfaces with the system and the 
00037 --              memory.
00038 -------------------------------------------------------------------------------
00039 
00040 
00041 library ieee;
00042 
00043 use ieee.std_logic_1164.all;
00044 
00045 library unisim;
00046 
00047 use unisim.vcomponents.all;
00048 use work.mem_interface_top_parameters_0.all;
00049 
00050 entity mem_interface_top is
00051         port
00052 (        
00053         cntrl0_DDR_DQ : inout  std_logic_vector(31  downto 0);  -- data to/from RAM
00054         cntrl0_DDR_A : out  std_logic_vector(12  downto 0);             -- address to RAM
00055         cntrl0_DDR_BA : out  std_logic_vector(1  downto 0);             -- Bank select to RAM
00056         cntrl0_DDR_CKE : out std_logic;                                                                 -- CLK Enable to RAM
00057         cntrl0_DDR_CS_N : out std_logic;                                                                        -- CS to RAM, must be 0
00058         cntrl0_DDR_RAS_N : out std_logic;                                                               -- RAS to RAM
00059         cntrl0_DDR_CAS_N : out std_logic;                                                               -- CAS to RAM
00060         cntrl0_DDR_WE_N : out std_logic;                                                                        -- Write EN to RAM
00061         cntrl0_DDR_DM : out  std_logic_vector(3  downto 0);             -- Data Mask to RAM, 0 = data valid, 1 = data masked
00062         SYS_CLK_P : in std_logic;                                                                                       -- diff 160 MHz p
00063         SYS_CLK_N : in std_logic;                                                                                       -- diff 160 MHz n
00064         CLK200_P : in std_logic;                                                                                        -- diff 200 MHz p
00065         CLK200_N : in std_logic;                                                                                        -- diff 200 MHz n
00066         CLK200 : out std_logic;
00067         SYS_RESET_IN : in std_logic;                                                                            -- reset
00068         LOCK : in std_logic;
00069         cntrl0_CLK_TB : out std_logic;                                                                  -- CLK to use for user interface
00070         cntrl0_RESET_TB : out std_logic;                                                                        -- reset avail. for UI
00071         cntrl0_WDF_ALMOST_FULL : out std_logic;                                         -- Write FIFO almost full Flag, stop writing data
00072         cntrl0_AF_ALMOST_FULL : out std_logic;                                                  -- Read Address FIFO almots full Flag, stop reading data
00073         cntrl0_READ_DATA_VALID : out std_logic;                                         -- read data valid, fetch data from Read FIFO when high
00074         cntrl0_APP_WDF_WREN : in std_logic;                                                             -- Enable for Write Data FIFO
00075         cntrl0_APP_AF_WREN : in std_logic;                                                              -- Enable for Write Address FIFO
00076         cntrl0_BURST_LENGTH : out  std_logic_vector(2  downto 0);-- Burst length indicator
00077         cntrl0_APP_AF_ADDR : in  std_logic_vector(35  downto 0); -- 35 X, 34:32 command, 31:27 X, 26 CS, 25:24 Bank Select, 23:11 RA, 10 Auto-Precharge (= X), 9 X, 8:0 CA
00078         cntrl0_APP_WDF_DATA : in  std_logic_vector(63  downto 0);-- write data in, 63:32 ris edge, 31:0 fal edge
00079         cntrl0_READ_DATA_FIFO_OUT : out  std_logic_vector(63  downto 0);-- read data out, same mapping
00080         cntrl0_APP_MASK_DATA : in  std_logic_vector(7  downto 0);-- mask data, 1 bit per data byte
00081         cntrl0_DDR_DQS : inout  std_logic_vector(3  downto 0);  -- data strobe to/from RAM
00082         cntrl0_DDR_CK : out  std_logic_vector(1  downto 0);             -- diff CLK to RAM p
00083         cntrl0_DDR_CK_N : out  std_logic_vector(1  downto 0)            -- diff CLK to RAM n
00084 );                      
00085 end mem_interface_top;
00086 
00087 architecture arch of mem_interface_top is
00088 
00089               COMPONENT mem_interface_top_top_0  port (DDR_DQ : inout  std_logic_vector(31  downto 0);
00090 DDR_A : out  std_logic_vector(12  downto 0);
00091 DDR_BA : out  std_logic_vector(1  downto 0);
00092 DDR_CKE : out std_logic;
00093 DDR_CS_N : out std_logic;
00094 DDR_RAS_N : out std_logic;
00095 DDR_CAS_N : out std_logic;
00096 DDR_WE_N : out std_logic;
00097 DDR_DM : out  std_logic_vector(3  downto 0);
00098 CLK_TB : out std_logic;
00099 RESET_TB : out std_logic;
00100 WDF_ALMOST_FULL : out std_logic;
00101 AF_ALMOST_FULL : out std_logic;
00102 READ_DATA_VALID : out std_logic;
00103 APP_WDF_WREN : in std_logic;
00104 APP_AF_WREN : in std_logic;
00105 BURST_LENGTH : out  std_logic_vector(2  downto 0);
00106 APP_AF_ADDR : in  std_logic_vector(35  downto 0);
00107 APP_WDF_DATA : in  std_logic_vector(63  downto 0);
00108 READ_DATA_FIFO_OUT : out  std_logic_vector(63  downto 0);
00109 APP_MASK_DATA : in  std_logic_vector(7  downto 0);
00110 DDR_DQS : inout  std_logic_vector(3  downto 0);
00111 DDR_CK : out  std_logic_vector(1  downto 0);
00112 DDR_CK_N : out  std_logic_vector(1  downto 0);
00113 
00114          clk_0                 : in std_logic;
00115      clk_90                : in std_logic;
00116      clk_50                : in std_logic;
00117          ref_clk                           : in std_logic;
00118      sys_rst               : in std_logic;
00119      sys_rst90             : in std_logic;
00120      sys_rst_ref_clk_1     : in std_logic; 
00121      idelay_ctrl_rdy       : in std_logic
00122 );
00123 END COMPONENT;
00124 
00125 
00126 component mem_interface_top_infrastructure
00127         port(        
00128              
00129               CLK               : out std_logic;
00130               CLK90             : out std_logic;
00131               CLK200            : out std_logic;
00132               CLK50             : out std_logic;
00133               REFRESH_CLK       : out std_logic; 
00134               sys_rst           : out std_logic;
00135               sys_rst90         : out std_logic;
00136               sys_rst_ref_clk_1 : out std_logic;
00137                SYS_CLK_P : in std_logic;
00138 SYS_CLK_N : in std_logic;
00139 CLK200_P : in std_logic;
00140 CLK200_N : in std_logic;
00141 SYS_RESET_IN : in std_logic;
00142 LOCK : in std_logic
00143             );
00144 end component;
00145 
00146 component mem_interface_top_idelay_ctrl
00147         port( CLK200    : in std_logic;    
00148               RESET     : in std_logic;     
00149               RDY_STATUS : out std_logic
00150             );
00151 end component;
00152 
00153 
00154 
00155 signal clk_0      : std_logic;                              
00156 signal clk_90     : std_logic;                            
00157 signal clk_200    : std_logic;        
00158 signal clk_50     : std_logic;                   
00159 signal ref_clk    : std_logic;                      
00160 signal sys_rst    : std_logic;
00161 signal sys_rst90  : std_logic;
00162 signal sys_rst_ref_clk_1 : std_logic;
00163 signal idelay_ctrl_rdy : std_logic; 
00164 begin
00165 
00166         CLK200 <= clk_200;
00167 
00168 
00169           top_00 :    mem_interface_top_top_0 port map (DDR_DQ  => cntrl0_DDR_DQ,
00170 DDR_A   => cntrl0_DDR_A,
00171 DDR_BA  => cntrl0_DDR_BA,
00172 DDR_CKE => cntrl0_DDR_CKE,
00173 DDR_CS_N => cntrl0_DDR_CS_N,
00174 DDR_RAS_N => cntrl0_DDR_RAS_N,
00175 DDR_CAS_N => cntrl0_DDR_CAS_N,
00176 DDR_WE_N => cntrl0_DDR_WE_N,
00177 DDR_DM  => cntrl0_DDR_DM,
00178 CLK_TB => cntrl0_CLK_TB,
00179 RESET_TB => cntrl0_RESET_TB,
00180 WDF_ALMOST_FULL => cntrl0_WDF_ALMOST_FULL,
00181 AF_ALMOST_FULL => cntrl0_AF_ALMOST_FULL,
00182 READ_DATA_VALID => cntrl0_READ_DATA_VALID,
00183 APP_WDF_WREN => cntrl0_APP_WDF_WREN,
00184 APP_AF_WREN => cntrl0_APP_AF_WREN,
00185 BURST_LENGTH    => cntrl0_BURST_LENGTH,
00186 APP_AF_ADDR     => cntrl0_APP_AF_ADDR,
00187 APP_WDF_DATA    => cntrl0_APP_WDF_DATA,
00188 READ_DATA_FIFO_OUT      => cntrl0_READ_DATA_FIFO_OUT,
00189 APP_MASK_DATA   => cntrl0_APP_MASK_DATA,
00190 DDR_DQS => cntrl0_DDR_DQS,
00191 DDR_CK  => cntrl0_DDR_CK,
00192 DDR_CK_N        => cntrl0_DDR_CK_N,
00193 --infrastructure signals
00194 clk_0           => clk_0,                              
00195 clk_90          => clk_90,                            
00196 idelay_ctrl_rdy => idelay_ctrl_rdy,
00197 ref_clk                 => ref_clk,
00198 clk_50          => clk_50,                   
00199 sys_rst         => sys_rst,
00200 sys_rst90       => sys_rst90,
00201 sys_rst_ref_clk_1 =>sys_rst_ref_clk_1
00202 );
00203 
00204 
00205 infrastructure0: mem_interface_top_infrastructure       port map
00206             ( 
00207                    CLK          => clk_0,
00208                    CLK90        => clk_90,
00209                    CLK200       => clk_200,
00210                    CLK50        => clk_50,
00211                    REFRESH_CLK  => ref_clk,
00212                    sys_rst      => sys_rst,
00213                    sys_rst90    => sys_rst90,        
00214                    sys_rst_ref_clk_1 => sys_rst_ref_clk_1,
00215               SYS_CLK_P => SYS_CLK_P,
00216 SYS_CLK_N => SYS_CLK_N,
00217 CLK200_P => CLK200_P,
00218 CLK200_N => CLK200_N,
00219 SYS_RESET_IN  => SYS_RESET_IN ,
00220 LOCK => LOCK                   
00221             );  
00222 
00223 idelay_ctrl0: mem_interface_top_idelay_ctrl port map
00224             ( CLK200            => clk_200,
00225               RESET             => sys_rst,
00226               RDY_STATUS        => idelay_ctrl_rdy
00227             );
00228 
00229 end arch;