00001 --**************************************************************
00002 --* *
00003 --* The source code for the ATLAS BCM "AAA" FPGA is made *
00004 --* available via the GNU General Public License (GPL) *
00005 --* unless otherwise stated below. *
00006 --* *
00007 --* In case of problems/questions/bug reports etc. please *
00008 --* contact michael.niegl@cern.ch *
00009 --* *
00010 --**************************************************************
00011
00012 --**************************************************************
00013 --* *
00014 --* $Source: /local/reps/bcmfpga/bcm_aaa/bcm_aaa/ddr/proc_data_buf.vhd,v $
00015 --* $Revision: 1.3.2.4 $ *
00016 --* $Name: dev $ *
00017 --* $Author: mniegl $ *
00018 --* $Date: 2008/11/03 17:57:44 $ *
00019
00020
00021 --* *
00022 --**************************************************************
00023 --------------------------------------------------------------------------------
00024 -- This file is owned and controlled by Xilinx and must be used --
00025 -- solely for design, simulation, implementation and creation of --
00026 -- design files limited to Xilinx devices or technologies. Use --
00027 -- with non-Xilinx devices or technologies is expressly prohibited --
00028 -- and immediately terminates your license. --
00029 -- --
00030 -- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
00031 -- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
00032 -- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
00033 -- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
00034 -- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
00035 -- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
00036 -- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
00037 -- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
00038 -- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
00039 -- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
00040 -- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
00041 -- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
00042 -- FOR A PARTICULAR PURPOSE. --
00043 -- --
00044 -- Xilinx products are not intended for use in life support --
00045 -- appliances, devices, or systems. Use in such applications are --
00046 -- expressly prohibited. --
00047 -- --
00048 -- (c) Copyright 1995-2006 Xilinx, Inc. --
00049 -- All rights reserved. --
00050 --------------------------------------------------------------------------------
00051 -- You must compile the wrapper file proc_data_buf.vhd when simulating
00052 -- the core, proc_data_buf. When compiling the wrapper file, be sure to
00053 -- reference the XilinxCoreLib VHDL simulation library. For detailed
00054 -- instructions, please refer to the "CORE Generator Help".
00055
00056 -- The synopsys directives "translate_off/translate_on" specified
00057 -- below are supported by XST, FPGA Compiler II, Mentor Graphics and Synplicity
00058 -- synthesis tools. Ensure they are correct for your synthesis tool(s).
00059
00060 library ieee;
00061 use ieee.std_logic_1164.all;
00062 -- synopsys translate_off
00063 library XilinxCoreLib;
00064 -- synopsys translate_on
00065
00066 entity proc_data_buf is
00067 port (
00068 addra : in (8 downto 0);
00069 addrb : in (6 downto 0);
00070 clka : in ;
00071 clkb : in ;
00072 dinb : in (255 downto 0);
00073 douta : out (63 downto 0);
00074 ena : in ;
00075 enb : in ;
00076 web : in
00077 );
00078 end proc_data_buf;
00079
00080
00081 architecture proc_data_buf_a of proc_data_buf is
00082 -- synopsys translate_off
00083
00084 component wrapped_proc_data_buf
00085 port (
00086 addra : in (8 downto 0);
00087 addrb : in (6 downto 0);
00088 clka : in ;
00089 clkb : in ;
00090 dinb : in (255 downto 0);
00091 douta : out (63 downto 0);
00092 ena : in ;
00093 enb : in ;
00094 web : in
00095 );
00096 end component;
00097
00098
00099 for all : wrapped_proc_data_buf use entity XilinxCoreLib.blkmemdp_v6_3(behavioral)
00100 generic map(
00101 c_reg_inputsb => 0,
00102 c_reg_inputsa => 0,
00103 c_has_ndb => 0,
00104 c_has_nda => 0,
00105 c_ytop_addr => "1024",
00106 c_has_rfdb => 0,
00107 c_has_rfda => 0,
00108 c_ywea_is_high => 1,
00109 c_yena_is_high => 1,
00110 c_yclka_is_rising => 1,
00111 c_yhierarchy => "hierarchy1",
00112 c_ysinita_is_high => 1,
00113 c_ybottom_addr => "0",
00114 c_width_b => 256,
00115 c_width_a => 64,
00116 c_sinita_value => "0",
00117 c_sinitb_value => "0",
00118 c_limit_data_pitch => 18,
00119 c_write_modeb => 2,
00120 c_write_modea => 0,
00121 c_has_rdyb => 0,
00122 c_yuse_single_primitive => 0,
00123 c_has_rdya => 0,
00124 c_addra_width => 9,
00125 c_addrb_width => 7,
00126 c_has_limit_data_pitch => 0,
00127 c_default_data => "0",
00128 c_pipe_stages_b => 0,
00129 c_yweb_is_high => 1,
00130 c_yenb_is_high => 1,
00131 c_pipe_stages_a => 0,
00132 c_yclkb_is_rising => 1,
00133 c_yydisable_warnings => 1,
00134 c_enable_rlocs => 0,
00135 c_ysinitb_is_high => 1,
00136 c_has_web => 1,
00137 c_has_default_data => 1,
00138 c_has_sinitb => 0,
00139 c_has_wea => 0,
00140 c_has_sinita => 0,
00141 c_has_dinb => 1,
00142 c_has_dina => 0,
00143 c_ymake_bmm => 0,
00144 c_sim_collision_check => "NONE",
00145 c_has_enb => 1,
00146 c_has_ena => 1,
00147 c_depth_b => 128,
00148 c_mem_init_file => "mif_file_16_1",
00149 c_depth_a => 512,
00150 c_has_doutb => 0,
00151 c_has_douta => 1,
00152 c_yprimitive_type => "32kx1"
00153 );
00154 -- synopsys translate_on
00155 begin
00156 -- synopsys translate_off
00157
00158 U0 : wrapped_proc_data_buf
00159 port map (
00160 addra => addra,
00161 addrb => addrb,
00162 clka => clka,
00163 clkb => clkb,
00164 dinb => dinb,
00165 douta => douta,
00166 ena => ena ,
00167 enb => enb ,
00168 web => web
00169 );
00170 -- synopsys translate_on
00171
00172 end proc_data_buf_a;
00173